JP3222967B2 - Digital signal processor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processor and, more particularly, to an inverse quantization circuit for decoding quantized data by inverse quantization.

[0002]

2. Description of the Related Art In recent years, it has been required to reduce the capacity of a recording medium and the size of a transmission line by compressing a digital signal.

For this purpose, a method has been proposed in which sampled data is grouped by an appropriate number into individual units, and quantization is performed for each unit. In this method, quantization is performed by allocating the number of quantization bits (hereinafter, referred to as a word length code) and the size of a normalized value (hereinafter, referred to as a scale factor value) to each unit, and performing quantization. Data (hereinafter referred to as sample data). That is, in general quantization, quantization is performed with a fixed word length, but in this method, usually, quantization is performed with a variable word length smaller than the fixed word length, so that the entire data amount can be compressed. Further, in this method, since a word length code and a scale factor value are assigned to each unit, an increase in the data is smaller than a decrease in the total data amount due to quantization with a variable word length.

[0004] In the inverse quantization in this method,
From the sample data A, the word length code WL of the unit corresponding to the sample data A, and the scale factor value SF, data B obtained by inversely quantizing the sample data A is obtained by, for example, an operation shown in Expression (1). That is, by performing the operation shown in Expression (1) in the inverse quantization circuit,
The compressed data can be expanded and decoded.

B = A · SF · F (WL) (1) (where F (WL) is a function of the word length code WL) In this method, an appropriate number of units are grouped together and 1 Writing and reading (or transmission / reception to / from a transmission path) to / from a recording medium are performed by serially transferring the data in groups.

FIG. 5 shows an array of serial data of one group. In FIG. 5, the transfer direction of the serial data is rightward. That is, the serial data read from the recording medium (or sent from the transmission path) is input to the inverse quantization circuit sequentially from the first bit to the right in the leftmost bit shown in FIG. It shall be.

One group of serial data starts from the beginning.
Word length codes, scale factor codes, and sample data are arranged in this order. Here, one group is composed of n units, each word length code corresponding to each unit is composed of m bits, and each scale factor code corresponding to each unit is composed of e bits. The scale factor code is converted by a decoder provided in the inverse quantization circuit to become the scale factor value.

FIG. 6 shows an example of the correspondence between each unit and each sample of the sample data. In this example, from the first sample of the sample data to the a-th sample (1
To a) correspond to the unit 1 and a + 1 of the sample data
From sample number b to sample number b (a + 1 to
b) corresponds to the unit 2. Then, (c to N) from the c-th sample to the last (N-th) sample of the sample data correspond to the unit n.

Here, the number of bits of each sample of the sample data is defined by the word length code of the corresponding unit (1 to n). That is, the number of bits of each word length code and each scale factor code are defined uniformly (m bits, e bits), but the number of bits of each sample of sample data is not uniform.
Therefore, the data length (k bytes) of the entire group is not uniform.

[0010] The quantization / inverse quantization by such a method is considered to be used for compression processing of data such as sound and image. For example, when using for audio signal processing, first, digital audio data obtained by A / D conversion of an audio signal on a time axis is cut out by an appropriate time window. Each piece of digital audio data cut out in the time window corresponds to the one group of data. Then, the cut-out digital audio data is transformed on the frequency axis by an appropriate orthogonal transform (such as a discrete Fourier transform (DFT), a discrete cosine transform (DCT), or an improved discrete cosine transform (MDCT)). The signal is decomposed into a plurality of signal components having an appropriate frequency width.

The plurality of signal components have a critical bandwidth (referred to as a critical band, the higher the frequency, the wider the bandwidth) based on the human perception of noise and the frequency analysis capability (frequency resolution). Put together a band that can be decided. A plurality of signal components put together in the band correspond to the data of one unit.

Then, each signal component is quantized using the word length code and the scale factor value, and written into a recording medium (optical disk, magneto-optical disk, magnetic tape, etc.) as a serial data string as shown in FIG. Or
Transmission to the transmission path). In the inverse quantization, as described above, data obtained by inversely quantizing the sample data (that is, the signal component) is obtained from the sample data, the word length code corresponding to the sample data, and the scale factor value. It is.

[0013]

By the way, in the above method, a buffer RAM is provided in the inverse quantization circuit, and one group of data serially transferred is temporarily stored in the buffer RAM. ing.

Then, from the word length code read from the buffer RAM, [1 / (2 ^WL−1 −
1)] and the value is stored in the register A. Further, the scale factor value SF is obtained from the scale factor code read from the buffer RAM, and the value is stored in the register B. Next, the values stored in the registers A and B are multiplied by the multiplier A, and the result [SF /
(2 ^WL-1 -1)] is stored in the register C.

Subsequently, each sample of the sample data corresponding to the unit of the word length code and the scale factor code is sequentially read from the buffer RAM. Then, each sample of the sample data read from the buffer RAM is multiplied by the multiplication result [SF / (2 ^WL-1 ) stored in the register C.
-1)] are successively multiplied by the multiplier B to obtain dequantized data for each unit.

That is, after the multiplication by the multiplier B is completed and the dequantized data is output from the multiplier B, the buffer RAM is again accessed to read the next sample of the sample data. I repeat. Therefore, while the next sample is being read from the buffer RAM, the multiplier B is not performing any processing. In other words, during access to the buffer RAM, multiplier B is "idle".

In recent years, it has been required to further reduce the circuit scale of the inverse quantization circuit and further increase the processing speed of the inverse quantization. Therefore, it is required to reduce the numbers of the three registers A to C and the two multipliers A and B provided by the above method. further,
By simultaneously accessing the buffer RAM and performing the arithmetic processing of the multiplier B, it is required to perform the processing efficiently and reduce the processing time. In addition, there is a demand for increasing the processing speed by reducing the number of accesses to the buffer RAM.

The above-described inverse quantization operation is performed by a fixed point method. Therefore, when the order of data in the entire group is large (that is, the maximum scale factor value in one group is large) and the word length used in the operation is small, the value of the small data becomes “0”. As a result, there is a problem that the precision of inverse quantization is reduced.

Therefore, it has been considered to increase the word length used for the operation and to allocate a sufficient word length even after the decimal point. However, when the word length used for the operation is increased, there is a problem that the circuit scale of the inverse quantization circuit increases. In addition, it is conceivable to set the data order of the entire group to be small while keeping the word length used for the operation small. However, in this case, there is a problem that the precision of the inverse quantization is reduced. For example, when used for processing an audio signal, there is a problem that a dynamic range is narrowed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above demands and problems, and an object of the first invention is to increase the processing speed of inverse quantization while reducing the circuit scale. An object of the present invention is to provide a digital signal processing device. A second object of the present invention is to provide a digital signal processing apparatus capable of improving the accuracy of inverse quantization without increasing the word length used for calculation even when the data order of the entire group is large. Is to do .

[0021]

According to a first aspect of the present invention, an appropriate number of sampled data are grouped together to form each unit, and a word length code, which is the number of bits of quantization, and a value when normalized A scale factor value, which is the size of, is assigned to each unit and quantization is performed, and an appropriate number of units are grouped together to form each group, and each sample of sample data that is quantized data, One group of data consisting of the scale factor code obtained by code conversion of the scale factor value and the word length code is serially transferred in units of groups, and the serially transferred data is inversely quantized for each unit of one group. A buffer RAM for storing one group of serially transferred data in the digital signal processing device;
A bit cutout shifter that reads one group of data stored in the buffer RAM, cuts out the readout data for each appropriate number of bits, and transfers the readout data, and reverses a word length code corresponding to an arbitrary unit cut out by the bit cutout shifter. First to convert to the data format required for quantization
, A second decoder for converting a scale factor code corresponding to an arbitrary unit extracted by the bit extraction shifter into a scale factor value, and data converted by the first decoder and a scale factor converted by the second decoder. A multiplier that multiplies the result by a value, multiplies the result of the multiplication by a sample of sample data corresponding to an arbitrary unit cut out by the bit cutout shifter, and outputs the result as dequantized data; A first register for storing either data or any sample of sample data corresponding to any unit cut out by the bit cutout shifter and outputting the same to the multiplier; a scale factor value converted by the second decoder; Or the data converted by the first decoder by the multiplier and the scale factor converted by the second decoder Further comprising a second register for the multiplier to store the one of the multiplication result between the gist of.

In the second invention, the sampled data is grouped by an appropriate number to form each unit, and a word length code, which is the number of bits of quantization, and a magnitude of a value when normalized. A certain scale factor value is assigned to each unit and quantization is performed, and an appropriate number of units are grouped together into groups, and each sample of the sample data that is the quantized data and the scale factor value are calculated. A serial transfer of one group of data consisting of the code-converted scale factor code and the word length code is performed in units of groups, and the serially transferred data is inversely quantized for each unit of the group, and the inversely quantized data In a digital signal processing device that outputs as a unit, a block in which each unit of one group is grouped by an appropriate number A third decoder for converting a scale factor code corresponding to an arbitrary unit into a scale factor order which is an exponent value when the scale factor value is displayed in a floating point using an appropriate radix; and a third decoder. And a block order calculation circuit for determining the maximum value of the scale factor order in one block to determine the position of the decimal point in accordance with the scale factor order obtained by the conversion, and a block order calculation circuit for a unit corresponding to the dequantized data. Subtracts the scale factor order converted by the third decoder from the maximum value of the scale factor order obtained by the subtractor, and based on the subtraction result of the subtractor,
The gist of the invention is to include a shifter that outputs the inversely quantized data in accordance with the decimal place determined by the block order calculation circuit.

[0023]

[0024]

Therefore, according to the first invention, for one unit, the data converted by the first decoder is stored in the first register, and the scale factor value converted by the second decoder is stored in the second register. To be stored. Next, the values stored in the first and second registers are multiplied by the multiplier, and the result is stored in the second register whose scale factor value has been read out and is empty.

Subsequently, each sample of the sample data corresponding to the unit is sequentially cut out from the buffer RAM by the bit cutout shifter. Then, each sample of the sample data and the multiplication result stored in the second register are successively multiplied by a multiplier, and each multiplication result is output as dequantized data. By repeatedly performing this for each unit, inverse quantization data is obtained for all units in one group.

At this time, while the multiplier multiplies each sample of the sample data by the multiplication result stored in the second register, the next sample data is read from the buffer RAM. Therefore, the read sample data is immediately stored in the first register, and the multiplier can immediately perform the next multiplication. That is, by temporarily storing the sample data read from the buffer RAM in the first register, the buffer R
The access to the AM and the arithmetic processing of the multiplier can be performed at the same time, and the processing is efficiently performed, so that the processing time can be reduced.

According to the second invention, the maximum value of the scale factor order is obtained for each block, and the maximum value of the scale factor order is determined by the scale factor order corresponding to each unit in the block. , The decimal point position of the inversely quantized data is shifted. That is, by adjusting the decimal point position in consideration of the maximum value of the data handled for each block, the decimal point position can be optimized and the calculation accuracy can be improved. As a result, the accuracy of the inverse quantization can be increased.

[0028]

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will now be described with reference to FIGS.
This will be described with reference to FIG. The configuration of the digital signal processed in this embodiment is the same as that of the conventional example shown in FIGS. 5 and 6, and a detailed description thereof will be omitted.

FIG. 1 is a block circuit diagram of the inverse quantization circuit 11 of the present embodiment. Quantized 1 as shown in FIG.
The serial data of the group is read from the recording medium (or sent from the transmission path) and input to the inverse quantization circuit 11.

A buffer RAM 1 is provided in the inverse quantization circuit 11.
2 are provided, and one group of data is temporarily stored in the buffer RAM 12. Bit cutout shifter 13
Reads one group of data stored in the buffer RAM 12, cuts out the read data for an appropriate number of bits, and transfers the data.

First, a word length code (m from the first bit)
× n-th bit), a desired (unit i-th;
i = 1 to n) Read data including the word length code from the buffer RAM 12. Then, the bit cutout shifter 13 cuts out a desired word length code (m bits) from the data and transfers it to the word length code register 14.

Next, from the buffer RAM 12, data including a desired (unit i-th) scale factor code is read out of the scale factor codes (n × n + 1 bits to m × n + e × n). Then, the bit cutout shifter 13 cuts out a desired scale factor code (e bits) from the data and transfers it to the scale factor code register 15.

Each of the word length code register 14 and the scale factor code register 15 stores data transferred from the bit cutout shifter 13.
Thus, the word length code register 14 stores one word length code of units 1 to n, and the scale factor code register 15 stores one scale factor code of units 1 to n.

[1 / (2 ^WL-1 -1)] value decoder 16
Reads the word length code stored in the word length code register 14 every m bits (that is, for each unit) from the beginning. Then, [1 / (2 ^WL-1 -1)]
The value decoder 16 calculates the equation (1) corresponding to each unit.
The value of [1 / (2 ^WL-1 -1)] is obtained and transferred to the register 17.

The scale factor value decoder 18 reads out the scale factor code stored in the scale factor code register 15 from the beginning every e bits (ie, every unit). Then, the scale factor value decoder 18
Converts the scale factor code by searching a predetermined table, finds a scale factor value SF corresponding to each unit, and transfers it to the register 19.

The register 17 stores the data transferred from the [1 / (2 ^WL-1 -1)] value decoder 16. On the other hand, the register 19 stores the data transferred from the scale factor value decoder 18. Thereby, the register 17 corresponds to an arbitrary unit (1 to n) [1 /
(2 ^WL-1 -1)], and the register 19 stores the scale factor value SF corresponding to the same unit (1 to n) as the register 17.

The multiplier 20 reads the data stored in each of the registers 17 and 19 and multiplies the two data to obtain the value of [SF / (2 ^WL-1 -1)] in the above equation (1). . When the multiplier 20 finishes reading the data stored in the registers 17, 19, both registers 17, 19 are empty. Therefore, the multiplier 20 transfers the obtained value to the register 19 and stores it. Thereby, the register 1
9 corresponds to an arbitrary unit [SF / (2 ^WL-1-
1)] is stored.

When the register 17 becomes empty, the bit cutout shifter 13 sets the number of bits (ie, the number of bits) based on the word length code from the head bit of a certain unit in one group of sample data stored in the buffer RAM 12. , For each sample of sample data). The bit cutout shifter 13 outputs the cutout data (that is, each sample of the sample data).
Are sequentially transferred to the empty register 17.

The register 17 is a bit cutout shifter 13
Stores an arbitrary sample of the sample data of a certain unit transferred from. On the other hand, the value of [SF / (2 ^WL−1 −1)] is stored in the register 19.

Then, the multiplier 20 determines whether each of the registers 17,
The data stored in No. 19 is read out, and the two data are multiplied to obtain the value of [A · SF / (2 ^WL−1 −1)] (ie, the inversely quantized data) in the above equation (1). .

At this time, the multiplier 20 sets each of the registers 17,
At the time when the data stored in No. 19 has been read,
Both registers 17, 19 are empty. Therefore, while the multiplier 20 is multiplying the value of [A · SF / (2 ^WL−1 −1)], the bit cutout shifter 13 cuts out the next sample of the sample data and transfers it to the register 17. Can be stored. Therefore, when the multiplier 20 finishes multiplying the value of [A · SF / (2 ^WL−1 −1)] for an arbitrary sample, the register 17 stores the next sample. Can immediately perform the next multiplication.

In other words, the multiplier 20 does not "play" while accessing the buffer RAM 12. That is, the buffer RAM 1 by the bit cutout shifter 13
Of each sample of the sample data from the sampler 2 and storage of the sampled sample in the register 17;
The reading of the sample from the register 17 by 0 and the arithmetic processing are performed in a pipeline manner.

The scale factor order decoder 21 sequentially reads one unit of scale factor code stored in the scale factor code register 15 for each block.

Here, the block is obtained by grouping the units of one group by an appropriate number. For example, when one group is divided into three blocks, units 1 to α correspond to block 1, units α + 1 to β correspond to block 2, and units β + 1 to n
Corresponds to the block 3.

That is, for each block, the scale factor order decoder 21 reads a scale factor code corresponding to the block from the head of the block for every e bits (that is, for each unit). Then, the scale factor order decoder 21 converts the scale factor code by searching a predetermined table, obtains a scale factor order corresponding to each unit, and transfers the scale factor order to the comparator 22.

Here, the scale factor order is a value of an exponent when the corresponding scale factor value is displayed as a floating point using 2 as a radix. The output of the comparator 22 is stored in the scale factor order maximum value register 23, and the scale factor order read from the scale factor order maximum value register 23 is returned to the comparator 22. Comparator 22
Compares the scale factor order transferred from the scale factor order decoder 21 with the scale factor order read from the scale factor order maximum value register 23, and stores the larger value in the scale factor order maximum value register 23. Output and store.

That is, when the scale factor order decoder 21 obtains the first scale factor code for one block, the scale factor order maximum value register 23 is left empty. Then, the comparator 22 outputs the first scale factor code obtained by the scale factor order decoder 21 to the scale factor order maximum value register 23 and stores the same. When the scale factor order decoder 21 obtains the second scale factor code for the same block, the comparator 22 compares the first scale factor code with the second scale factor code and outputs the larger scale factor code to the maximum scale factor order. It is output to the value register 23 and stored. This process is repeated for all scale factor codes in one block.

As a result, when the scale factor order decoder 21 has sequentially obtained and transferred all the scale factor codes of one block, the largest value stored in the scale factor order maximum value register 23 is the largest. It is a scale factor code.

The subtractor 24 subtracts the scale factor order corresponding to each unit obtained by the scale factor order decoder 21 from the maximum value of the scale factor order stored in the scale factor order decoder 21.

The shifter 25 adjusts the dequantized data output from the multiplier 20 based on the subtraction result of the subtractor 24 to the decimal point position determined from the maximum value of the scale factor order. Output as output data.

In this method, the decimal point position of each block is determined from the maximum value of the scale factor order for each block. Then, the dequantized data of the unit is shifted by the scale factor order corresponding to each unit in the block with respect to the determined maximum value of the scale factor order, and the data according to the decimal point position of each block is shifted. Is output. In other words, the position of the decimal point is freely determined for each block according to the order of the data handled in the calculation, and the floating point method is used for each block (hereinafter, this method is referred to as a block method). Floating-point method).

For example, as shown in FIG. 2, when the data to be handled is a decimal number of 0.01 to 100 and the word length used for the operation is 8 bits, the maximum data "100" is represented by the fixed-point method. Has 7 bits in binary notation (= 1
28) Required. At this time, data of 0.5 or less becomes “00000000” and all bits become “0”, and cannot be distinguished and represented.

On the other hand, in the block floating-point method, data handled in one group as a whole is 0.01 decimal.
Even if the data order is from 100 to 100, if the data order in one block is from 0.01 to 10 in decimal, only 4 bits are required in binary notation to represent the maximum data "10". , 4 bits can be assigned to the decimal point. In the block floating point method, 1
Data handled by the whole group is 0.01 to 10 in decimal
Even if it is 0, if the data order in one block is 0.01 to 1 in decimal, only one bit is required in binary notation to represent the maximum data "1". Seven bits can be allocated below the decimal point. Therefore, a block with a small data order can be accurately represented even if the data to be handled is small.

That is, by adjusting the position of the decimal point in consideration of the maximum value of the data handled for each block, the position of the decimal point can be optimized and the calculation accuracy can be improved. This improvement in the calculation accuracy is particularly effective for small data in which the calculation accuracy is significantly reduced in the conventional fixed point method. Further, since it is not necessary to increase the word length used for the operation, the inverse quantization circuit 11
Is not increased.

As described above, in this embodiment, first, 1
For one unit, [1 / (2 ^WL-1-1)]
Then, the value is stored in the register 17 and the scale
The factor value is obtained and stored in the register 19.
You. Next, the values stored in the registers 17 and 19 are
Multiplier 20 multiplies the result [SF / (2^WL-1−
1)], the scale factor code is read and emptied
Stored in the register 19.

Subsequently, each sample of the sample data corresponding to the unit is sequentially cut out from the buffer RAM 12. Then, each sample of the sample data and the multiplication result stored in the register 19 [SF / (2 ^WL-1 -1)]
Are successively multiplied by the multiplier 20 to obtain [A · SF /
(2 ^WL-1 -1)]. By repeatedly performing this for each unit, inversely quantized data is obtained for all units in one group.

At this time, the multiplier 20 sets [A · SF / (2
^While multiplying by the value of ^WL- 1-1)], the next sample of the sample data is stored in the register 17, and the multiplier 20 can immediately perform the next multiplication. That is, by temporarily storing the sample data read from the buffer RAM 12 in the register 17, the access to the buffer RAM 12 and the arithmetic processing of the multiplier 20 can be performed at the same time. Can be shortened.

Also, in this embodiment, the two registers B and C in the conventional example are replaced by one register 19 and the two multipliers A and B are replaced by one multiplier 20. In comparison, the circuit scale of the inverse quantization circuit 11 can be reduced.

Further, in this embodiment, the decimal point position of the block is determined based on the scale factor order obtained for each block. Then, by shifting the dequantized data by the scale factor order corresponding to each unit in the block with respect to the maximum value of the scale factor order, a block floating point that outputs data with the decimal point position adjusted is output. The decimal point system is used. That is,
The position of the decimal point is determined in consideration of the maximum value of the data handled for each block, and the output data is adjusted. Thus, the precision of the decimal point can be optimized and the calculation accuracy can be improved without increasing the word length used in the calculation and increasing the circuit scale. As a result, the accuracy of the inverse quantization can be increased.

For example, in the case of using for audio signal processing, it is conceivable that one group is divided into three groups corresponding to the low band, the middle band, and the high band, respectively, and the block floating point method is performed for each band. Can be In this case, it is particularly effective for a high-frequency audio signal whose level is low in a steady state but instantaneously becomes a high level, and it is possible to clearly reproduce from a low level to a high level according to the audibility.

As described above, the number of bits of each sample of the sample data is defined by the word length code of the corresponding unit. That is, the number of bits of each sample of the sample data is not uniform.
Therefore, for example, if the data width of the buffer RAM 12 is 8
If an arbitrary sample of sample data is 16 bits, the data of the sample may extend over three addresses of the buffer RAM 12 as shown in FIG.
On the other hand, when the data width of the buffer RAM 12 is 16 bits and an arbitrary sample of sample data is 16 bits, as shown in FIG.
It fits within two addresses of M12 and does not span three addresses. When an arbitrary sample of the sample data is 8 bits and the data width of the buffer RAM 12 is 8 bits, the data of the sample is stored in the buffer RAM 1.
In most cases, the address spans address 2 or 2. On the other hand, when an arbitrary sample of the sample data is 8 bits and the data width of the buffer RAM 12 is 16 bits, when the data of the sample extends over two addresses of the buffer RAM 12, the data is stochastically reduced by half.

Therefore, the data width of the buffer RAM 12 is determined at the time of circuit design in consideration of a trade-off relationship between an improvement in the processing speed of the inverse quantization circuit 11 and an increase in the circuit size of the inverse quantization circuit 11. Need to be kept.

That is, when the data width of the buffer RAM 12 is increased, the number of accesses to the buffer RAM 12 at the time of reading the sample data is reduced, so that the processing speed is improved. However, buffer RAM
If the data width of T.12 is set to the maximum value of the number of bits of each sample of one group of sample data, the improvement of the processing speed is saturated. Disappears. On the other hand, when the data width of the buffer RAM 12 is increased, the buffer RAM 12 and the bit
3, the width of the data bus connecting to the third and third bits increases, and the circuit scale of the bit cutout shifter 13 also increases, thereby increasing the circuit scale of the inverse quantization circuit 11. Therefore, the data width of the buffer RAM 12 is set to an optimum value according to a trade-off relationship between the two.

As a result, in this embodiment, the inverse quantization circuit 11
The processing speed can be increased without increasing the circuit scale. Note that the present invention is not limited to the above embodiment, and for example, the number of units in one group may be changed for each group.

In the conventional configuration, only the block floating point method may be performed. Furthermore, a data sequence of basic data required for inverse quantization may be added before a data sequence of one group.

Here, the basic data is data indicating the number of units of the word length code and the scale factor code when the number of units of the word length code and the scale factor code is smaller than the number of units of the sample data.

For example, the number of units of the word length code and the scale factor code is set to p, and the number of units of the sample data is set to r more than p (p <r).
Then, for the units 1 to p of the sample data, inverse quantization is performed based on the corresponding units 1 to p of the word length code and the scale factor code, and for the units p + 1 to r of the sample data, the word length code and the scale factor code Inverse quantization is performed on the basis of the unit p.

That is, an appropriate number of sample data units are grouped together to form a large unit, and a word length code and a scale factor code are assigned to the large unit to perform inverse quantization (in other words, the sample is sampled). "Coarse" inverse quantization is performed on the data units p + 1 to r). Accordingly, the data length of the entire group is shorter than that of the method described in the conventional example, so that the compression can be improved.

For example, when used for processing an audio signal, since the importance of a high frequency signal is lower than that of a low / mid frequency signal, a "coarse" inverse is applied to a high frequency signal as described above. By performing quantization (and quantization), data can be compressed without impairing the sense of hearing.

[0071]

As described in detail above, according to the first aspect, there is an excellent effect that the processing speed of the inverse quantization can be increased while the circuit scale is reduced. Further, according to the second invention, there is an excellent effect that the accuracy of inverse quantization can be increased without increasing the word length used for the operation even when the data order of the entire group is large .

[Brief description of the drawings]

FIG. 1 is a block circuit diagram of an embodiment embodying the present invention.

FIG. 2 is an explanatory diagram for explaining a fixed-point method and a block floating-point method.

FIG. 3 is an explanatory diagram for explaining a relationship between a data width of a buffer RAM 12 and sample data.

FIG. 4 is an explanatory diagram for explaining a relationship between a data width of a buffer RAM 12 and sample data.

FIG. 5 is an explanatory diagram for describing an array of serial data of one group.

FIG. 6 is an explanatory diagram for explaining the correspondence between each unit and sample data.

[Explanation of symbols]

12 buffer RAM 13 bit cutout shifter 16 [1 / (2 ^WL-1 -1)] as first decoder
Value decoder 18 Scale factor value decoder as second decoder 20 Multiplier 17 First register 19 Second register 21 Scale factor order decoder as third decoder 22 Comparator constituting block order calculation circuit unit 23 Scale Factor Value Order Maximum Value Register Constituting Block Order Calculation Circuit 24 Subtractor 25 Shifter

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03M 7/30

Claims (2)

(57) [Claims] 1. An appropriate number of sampled data are grouped together to form each unit, and a word length code, which is the number of quantization bits, and a scale factor value, which is a magnitude of a value when normalized, are defined. Quantization is performed by allocating each unit, and the appropriate number of units are grouped together into groups, and each sample of sample data that is quantized data and a scale factor code obtained by code-converting the scale factor value. And one group of data consisting of the word length code and the word length code, and serially transferred in a digital signal processing device that inversely quantizes the serially transferred data for each unit of the group. Buffer RAM for storing one group of data, and one group of data stored in the buffer RAM. A bit cutout shifter that reads out data and cuts out and transfers the read data for each appropriate number of bits, and converts a word length code corresponding to an arbitrary unit cut out by the bit cutout shifter into a data format required for inverse quantization. A first decoder, a second decoder for converting a scale factor code corresponding to an arbitrary unit extracted by the bit extraction shifter into a scale factor value, and data converted by the first decoder and converted by the second decoder A multiplier that multiplies the result of the multiplication by a scale factor value, multiplies the multiplication result by a sample of sample data corresponding to an arbitrary unit cut out by the bit cutout shifter, and outputs the result as dequantized data; Corresponds to converted data or any unit cut out by the bit cutout shifter A first register for storing any sample of the sample data and outputting the sampled data to the multiplier; a scale factor value converted by the second decoder, or data converted by the first decoder by the multiplier, and a second register. A second register for storing any one of the multiplication results with the scale factor value converted by the decoder and outputting the result to the multiplier. 2. An appropriate number of sampled data are grouped together to form each unit, and a word length code, which is the number of quantization bits, and a scale factor value, which is a magnitude of a value when normalized, are defined. Quantization is performed by allocating each unit, and the appropriate number of units are grouped together into groups, and each sample of sample data that is quantized data and a scale factor code obtained by code-converting the scale factor value. Digital signal processing for serially transferring data of one group consisting of the word length code and the word length code in a group unit, dequantizing the serially transferred data for each unit of the group, and outputting as inversely quantized data In the apparatus, an arbitrary number of units are grouped into blocks each of which is an appropriate number of units of one group. A third factor decoder that converts a scale factor code corresponding to the following into a scale factor order which is an exponent value when the scale factor value is displayed in a floating point using an appropriate radix; and a scale factor converted by the third decoder. A block order calculating circuit for determining a maximum value of a scale factor order in one block to determine a decimal point position according to the order; and a scale factor calculated by the block order calculating circuit for a unit corresponding to the inverse quantized data. A subtractor for subtracting the scale factor order converted by the third decoder from the maximum value of the order; and the dequantized data based on the subtraction result of the subtractor,
A digital signal processing device comprising: a shifter that outputs a signal in accordance with the position of the decimal point determined by the block order calculation circuit .