JP3566843B2 - Data reproducing method and data reproducing apparatus - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a data recording / reproducing method and apparatus, and more particularly to a method for relieving a read error caused by data duplication or data omission occurring when reading RLL (Run Length Limited) code data written on a storage medium such as a magnetic tape. Regarding treatment.
[0002]
Recent storage devices are required to have high storage density and high-speed data transfer due to their small size and large capacity.Therefore, a slight amount of scratches, dust, noise, etc. on the medium cause a read error and cause a data error. It is becoming very difficult to increase the reliability of the system.
[0003]
Particularly, in the case of a data reproducing apparatus that requires high reliability, the medium recording data is subjected to code conversion (decoding), and then data errors are recovered (error corrected) by means such as ECC (Error Correction Code). However, in the case of a read error generated for the above-described reason, a random error becomes a burst error, and the error becomes large, so that it may not be possible to relieve the error by means such as ECC. Therefore, it is necessary to restore the read data before sending the data to a means such as the ECC.
[0004]
[Prior art]
In the ECC of a conventional storage device, the result of decoding data written in RLL code on a recording medium is corrected. Since the RLL code written on the medium is once decoded, if a missing read bit or the like occurs at that time, even the ECC may become uncorrectable data due to the nature of the RLL code.
[0005]
For example, in the case of the 1-7 RLL code, when decoding is performed by referring to the last bit of the preceding data block and the foremost bit of the succeeding data block, when a position to be referred to is shifted, This will result in incorrect decoding.
[0006]
For this reason, in the conventional apparatus, an attempt has been made to improve the reliability by performing recovery measures such as re-reading (retry operation). Had been destroyed.
[0007]
[Problems to be solved by the invention]
As described above, in the related art, even important write data is discarded because it cannot be corrected, and there has been a problem in that data reliability is reduced.
[0008]
The present invention improves the ECC correction efficiency by detecting improper data by detecting a read error of write data on a medium, decoding it, and sending it to the ECC unit, thereby improving the reliability of the device. It is intended to make it happen.
[0009]
[Means for Solving the Problems]
The present invention reads out first data from a recording medium, extracts a clock from the first data, creates second data synchronized with the clock, and decodes third data from the second data. In the data reproducing method for correcting the error, when the number of the second data is smaller than the number of data defined from the recording area where the first data is recorded, and When a missing of a plurality of bits occurs, predetermined pseudo data having a data length corresponding to the number of differences between the two is inserted into a previously specified data missing portion of the second data to generate correction data. When a single bit is missing at a plurality of locations in the same data block, pseudo data for one clock is inserted into a plurality of previously specified missing locations of the second data. When the number of the second data is larger than the number of data determined from the recording area where the first data is recorded, and a plurality of bits are continuously formed in the same data block. When the data excess occurs, the excess data having the data length corresponding to the number of differences between the two is deleted from the previously specified data excess portion of the second data, and the correction data is created. When a single-bit data excess occurs at a plurality of locations in a block, excess data for one clock is deleted from a plurality of data excess locations specified in advance in the second data to generate correction data. Then, the correction data is decoded into third data, and the third data is subjected to error correction. Hereinafter, a specific description will be given.
[0010]
FIG. 1 is a diagram showing a data format near a recording area on a magnetic tape. Since a magnetic disk and a magneto-optical disk can be handled in the same manner, the description of those cases is omitted. An IBG (Inter Block Gap) portion is a gap between data blocks, and is a gap for guaranteeing a time until the tape running speed becomes constant. In the data block, an RLL-encoded data pattern is recorded.
[0011]
FIG. 2 shows a configuration diagram of a data recording / reproducing apparatus according to the present invention. The device having the same configuration is a magnetic device (or a magnetic disk device or a magneto-optical disk device), and a recording area is recorded on a certain recording medium by a reference clock (clock used for writing) having substantially the same frequency as the PLL clock frequency. It has a means for measuring (recording area measuring unit 1), and the recording area measuring unit starts its operation from the start detection timing by the recording area detecting unit 4 (IBG detection or the like) which is a means for detecting the head of the recording area.
[0012]
The recording code data is synchronized with the recording code data by a PLL clock generated from the data itself (the PLL 2 and the data synchronizing unit 3), and is sequentially recorded via the data storage and transmission means (data holding means 5). The data (data to be demodulated) is sent to a decoder 7 for decoding, and the data decoded by the decoder is error-corrected by an ECC error correction unit 6. Data correction can be realized by adding a clock loss correction unit 8 and an excessive clock correction unit 9 to the above configuration and correcting data output from the data holding unit 5.
[0013]
Note that the detection of the missing clock and the detection of the excessive clock are performed by the clock missing correction unit 8 or the excessive clock correction unit 9 and the size of the planned recording area obtained by measuring the reference clock by the recording area measuring unit 1. This is performed by comparing (taking a difference) with the actual data size obtained by measuring the PLL clock. As a result, the difference data becomes the number of erroneous data.
[0014]
Further, the error occurrence position is specified by the error position specifying means 10 and the data is replaced with the pseudo data by operating the data holding means 5 by the number of the difference data from the specified position. The error occurrence position may be specified by a known means as described later.
[0015]
FIG. 3 shows an example of data at the time of a clock drop in FIG. The number of bits in the recording area is measured by the recording area measuring unit 1 in FIG. 2, and as a result, if the number of bits is smaller than the expected number of measurements, an error signal due to a PLL clock loss (hereinafter, a bit loss error signal) ) Is recognized as having occurred. The error signal generation position (arrow (1)) is specified by a decoding error of the RLL code. Next, the number of PLL clocks generated in the area (range (3) and range (4)) is calculated from the number of measurements scheduled by the recording area measuring unit 1 (the number of recording area data indicated by the range (2)). ), That is,
Number of missing clocks = range (2) − [range (3) + range (4)]
Hold.
[0016]
By inserting the pseudo data corresponding to the number of missing clocks into the above-described bit missing error signal generation position (arrow (1)), there is a possibility that data after the bit missing position can be rescued. Naturally, the number of bits of the demodulated data must always match the number of bits of the recording area measuring means.
[0017]
The above description is a basic data correction method at the time of a clock dropout. However, the following method is used by using means that can be arbitrarily set for the following situations.
The first case is when the data in the data holding means is inverted by the PLL data polarity inversion. This case is dealt with by arbitrarily changing the pseudo data to be inserted.
[0018]
The second is a case where a bit missing error signal is not accurately generated. That is, the error signal is generated after the error occurs, but the position (time) at which the error signal occurs may not be the exact time at which the error occurred. In that case, the following method is used.
[0019]
For example, if the error position detecting means has poor characteristics and an error signal is generated after the position where the error actually occurred, it is necessary to correct the data earlier by the time when the error was detected later. The time during which the error position detection means actually generates an error signal (the delay time of error signal generation) can be theoretically obtained or can be checked by experiment. By inserting the pseudo data earlier than the error occurrence position generated by the error position detecting means by the data of the determined delay time of the error signal generation, the data correction can be finely adjusted.
[0020]
Third, there is a case where a plurality of error positions exist in a certain data block. This case is dealt with by providing a means for storing a plurality of error position detections (during RLL decoding).
[0021]
FIG. 4 shows an example of data at the time of excessive clock with respect to FIG. The number of bits in the recording area is measured by the recording area measuring unit 1 in FIG. 2, and as a result, if the number of bits is larger than the planned number, the clock generated by the influence of the external noise of the PLL or the like becomes excessive. It is recognized that the resulting error signal (hereinafter referred to as an excessive bit error signal) has occurred. The detection of the error position is performed by a decoding error of the RLL code (arrow (5)).
[0022]
Next, a value obtained by subtracting the expected number of measurements (the number of recording area data indicated by the range (6)) by the recording area measuring unit 1 from the PLL clock (indicated by the range (7)) generated in the area. A certain clock overload,
Clock excess = range (7)-range (6)
Hold.
[0023]
By subtracting the data number corresponding to the clock excess from the data (data in the bit excess position portion) subsequent to the error signal generation position (arrow (5)), there is a possibility that the data subsequent to the bit excess position portion can be rescued. is there. Of course, the number of bits of the demodulated data must always match the number of bits of the recording area measuring means.
[0024]
The above description is a basic data correction method when the clock is excessive, but a means that can be arbitrarily set for the following situations will be used.
The first is a case where the excessive bit error signal is not accurately generated. That is, the error signal is generated after the error has occurred. However, when the position where the error signal is generated is not the exact time when the error occurs, the following method is used.
[0025]
For example, if the error position detecting means has poor characteristics and an error signal is generated after the position where the error actually occurred, it is necessary to correct the data earlier by the time when the error was detected later. The time when the error position detecting means actually generates an error signal (delay time of error signal generation) can be theoretically obtained, and can also be checked by experiments or the like.
[0026]
Fine adjustment of data correction can be performed by subtracting excess data earlier than the error occurrence position generated by the error position detection means by the data corresponding to the determined error signal generation delay time.
[0027]
The second is a case where there are a plurality of error positions in a certain data block. In this case, this is dealt with by providing a means for storing a plurality of error position detections (during RLL decoding).
[0028]
The above two methods, namely, a method for coping with a missing clock and a method for coping with an excessive clock, include a planned number of recordings by the recording area measuring means (recording area data number range (2) or (6)); By comparing the number of PLL clocks generated in the area, the means for missing bits and the means for excess bits can be switched. Therefore, data that cannot be corrected by the ECC in the past becomes more likely to be corrected, and the reliability of the device can be improved.
[0029]
BEST MODE FOR CARRYING OUT THE INVENTION
A block diagram A in FIG. 5 is a block diagram including a configuration example of the clock loss correction unit 8 of the present invention and peripheral parts. The timing chart A1 in FIG. 6 shows the relationship between the data of each part when a plurality of bits are continuously missing in the same data block. The timing chart A2 in FIG. The case where one bit is missing will be described.
[0030]
A means for generating a bit missing error signal (A) generated by a RLL code shift due to a PLL clock missing can be configured using known means. For example, a means for measuring the PLL cycle using a clock several times the PLL carrier frequency may be used, or a means for judging an error from data output from the decoder may be used. The error signal generation position is measured by a counter 12 (for recording area measurement) in the recording area measuring unit 1 using a reference clock having substantially the same frequency as that of the PLL. The measurement result by the counter is latched by the FF 13 and used for grasping the position.
[0031]
The counter 12 is reloaded when IBG (or the head of the recording area) is detected (IBG detection signal (a)). To cope with the case where the error signal is generated a plurality of times, a plurality of types of FFs 13 (for example, FFs 14 (not shown), FFs 15 and the like) may be provided. The FF 16 holds the value currently held by the FF 13 even in the next recording area (that is, during reading of the next data).
[0032]
Next, the CMP 19 makes the enable for the planned number corresponding to the planned data measurement number (the number of recording area data) determined by the recording area measuring unit 1 (counter 12). Note that the scheduled number can be arbitrarily set from the MPU or the like. The number of PLL clocks generated in the area is measured by using a counter 20 that measures the PLL clock and when the enable of the CMP 19 is valid. The number of PLL clocks generated in the area where the enable is valid is compared with the expected number of data measurements using a comparator 21 or the like. If the number of PLL clocks is small, the clock missing correction unit is selected. I do.
[0033]
Simultaneously with the comparison, a value (the number of missing clocks) obtained by subtracting the number of PLL clocks measured by the counter 20 from the expected number of data measurement using the ALU 22 (may be a subtractor) is obtained, and the value is held by the FF 23. Is done. The pseudo data equivalent to the number of missing clocks held by the FF 23 is inserted into the above-mentioned bit missing error signal occurrence position. As a means for this, the MUX 24 switches and inserts the pseudo data of the number of missing clocks by the FF 23 into the position corresponding to the error occurrence position that was grasped by the FF 16 at the timing of outputting data from the data holding unit 5 to the error correction unit. I do.
[0034]
The CMP 25 corresponding to the pseudo data insertion enable for switching the MUX 24 is managed by the FF 16 and the FF 23 and a counter 26 which manages data holding means. The counter 26 is an (up) counter for managing an address for transmitting data from the data holding unit 5 to the error correction unit, and increments the data holding unit address up to the scheduled data measurement number. As a method of creating the enable of the CMP 25, the enable of the CMP 25 is enabled when the output of the counter 26 and the FF 16 become the same, and after the number of data of the FF 23 is sent to the error correction unit, the enable of the CMP 25 is disabled. A counter 35 is provided as a means for measuring the number of data of the FF 23. In FIG. 5, however, the enable of the CMP 25 is invalidated by counting up the counter 35 in FIG. While this enable is valid, the counter 26 stops. The pseudo data to be inserted in the MUX 24 is created in the RAM 27 so that it can be programmably changed from the MPU or the like.
[0035]
Also, an ALU 28 (a subtractor may be provided) is provided to subtract from the output of the FF 16 a value (set value) that can be arbitrarily changed from an MPU or the like. With this configuration, it is possible to insert the pseudo data from a position where the ALU output is smaller than the error occurrence position (FF16 output) by the set value, that is, a position that is an arbitrary clock before the error occurrence position. Become like
[0036]
Further, when an error is present at a plurality of locations, a counter 29 for detecting an error position using FF 17 (not shown), FF 18 and the like and counting the number of error locations is provided. The number of missing clocks is compared. As a result of the comparison, if the two are equal, one clock worth of pseudo data is inserted at the position indicated by each of the FFs 16. If they are not equal, an error is reported to an upper level as an uncorrectable error. Based on the report, the host performs processing such as read retry. The reason why pseudo data of only one clock is inserted into each error location is that there is a high possibility that one data is missing for one error. At a plurality of error occurrence positions, the counter 26 is stopped by one clock for each clock. At that time, switching is performed by the MUX 24 and pseudo data is inserted.
[0037]
A block diagram B of FIG. 8 is a block diagram including one configuration example of the excessive clock correction unit 9 of the present invention and peripheral parts. The timing chart B1 of FIG. 9 shows the relationship between the data of each part when the excess of a plurality of bits occurs continuously in the same data block, and the timing chart B2 of FIG. The case where an excess of one bit occurs will be described.
[0038]
Means for generating an excessive bit error signal (c) generated due to an RLL code shift due to excessive clocks can be configured using known means as in the case of FIG. As in the case where the clock is lost, the error signal generation position is measured by the counter 12 using the reference clock having substantially the same frequency as that of the PLL, and the measurement result is latched by the FF 13 to be used for grasping the error generation position.
[0039]
Even when the error signal is generated a plurality of times, similarly to the case of the missing clock, when the IBG or the head of the recording area is detected (IBG detection signal (a)), the data is reloaded. In response to a case where an error signal is generated a plurality of times, the FF 13 may be of a plurality of types (for example, FF14 (not shown), FF15, etc.). The FF 16 holds the value of the FF 13 even in the next recording area (that is, during reading of the next data).
[0040]
Next, the planned number of data measurements (the number of recording area data) by the recording area measuring unit 1 is enabled by the counter 12 using the counter 12 for the planned number. The number of PLL clocks generated in the area is measured by using a counter 20 that measures the PLL clock, and the number of PLL clocks is measured when the enable of the CMP 19 is enabled. The number of PLL clocks generated in the area where the enable is valid is compared with the planned number of data measurements using the CMP 21. If the number of PLL clocks is large, the clock excess correction unit is selected. At the same time as the comparison, the ALU 30 (which may be a subtractor, the ALU output is a negative number when shared with the ALU 22 (block diagram A)) is used to measure data from the number of PLL clocks measured by the counter 20. A value obtained by subtracting the number (too many clocks) is obtained, and the value is held by the FF 23.
[0041]
The excess clock data held by the FF 23 is deleted from the bit excess error signal occurrence position. Therefore, when the output of the (up) counter 36 that manages the address for outputting data from the data holding unit to the error correction unit and the error occurrence position that has been located by the FF 16 become the same, The ALU 31 (may be an adder) adds the number of clocks equal to the number of data held in the FF 23 to the output of the counter 36, and the data at the address indicated by the added output 32 is sent from the data holding unit 5 to the error correction unit. Send to By performing this addition, it is possible to prevent data in the clock excess part from being output to the error correction unit. Thereafter, the addition output 32 is incremented, but the addition output 32 continues to be incremented until it becomes the same as the output of the FF 37. The FF 37 holds the maximum value of the number of PLL clocks measured by the counter 20 when the enable is enabled by the CMP 19 in the next recording area.
[0042]
Further, it has an ALU 28 (a subtractor may be used) for subtracting a value (set value) that can be arbitrarily changed from the output of the FF 16 from an MPU or the like in a programmable manner. By doing so, the data can be corrected from the position where the ALU output is smaller by the set value than the error occurrence position (FF16 output), that is, the position before the error occurrence position by an arbitrary clock.
[0043]
A RAM (not shown) for storing set values may be divided into two dedicated to each case so that an error occurrence position can be set separately when the clock is lost and when the clock is excessive, but they are commonly used. It may be configured.
[0044]
Further, when an error is present in a plurality of locations, the FF 17 (not shown), the FF 18 and the like have a counter 29 for detecting an error position and counting the number of error locations, and the counter output and the FF 23 hold the counter output. Compare with too many clocks. As a result of the comparison, if they are equal, the data at the address indicated by the addition output 32 is sent from the data holding means 5 to the error correction unit. This operation is repeated by the number of error locations. If they are not equal, an error is reported to an upper-level as an uncorrectable error. The host performs processing such as read retry. The reason why data of only one clock is deleted at each error location is that there is a high possibility that one data is excessive for one error.
[0045]
【The invention's effect】
As described above, according to the present invention, it is possible to insert or delete appropriate bits with respect to read errors caused by bit omission or bit duplication of RLL code data, which cannot be corrected by the conventional ECC. This increases the possibility of correction by ECC, and greatly contributes to the improvement of the reliability of data storage of the storage device.
[Brief description of the drawings]
FIG. 1 Data format FIG. 2 Configuration diagram FIG. 3 Data with missing clocks FIG. 4 Data with excessive clocks FIG. 5 Block diagram A
FIG. 6 is a timing chart A1.
FIG. 7 is a timing chart A2.
FIG. 8 is a block diagram B.
FIG. 9 is a timing chart B1.
FIG. 10 is a timing chart B2.
[Explanation of symbols]
1 is a recording area measuring unit,
2 is PLL,
3 is a data synchronization unit,
4 is a recording area detection unit,
5 is data holding means,
6 is an ECC error correction unit,
7 is a decoder,
8 is a clock missing correction unit,
9 is a clock excess correction unit,
10 is an error position specifying means,
11 is error detection,
12, 20, 26, 29, 35, and 36 are counters,
13, 15, 16, 18, 23 and 37 are FF,
19, 21 and 25 are comparators (CMP),
22,28,30,31,38 are ALU,
24 is a MUX,
27 is RAM,
32 is an addition output.

Claims (2)

First data is read from a recording medium, a clock is extracted from the first data, second data is generated in synchronization with the clock, and third data decoded from the second data is subjected to error correction. The data playback method
A case where the number of the second data is smaller than the number of data determined from a recording area in which the first data is recorded,
When a plurality of missing bits occur consecutively in the same data block, predetermined pseudo data having a data length corresponding to the number of differences between the two bits is added to the previously specified data missing portion of the second data. Insert to create correction data,
When a single bit is missing at a plurality of locations in the same data block, pseudo data for one clock is inserted into a plurality of missing locations specified in advance of the second data to correct the correction data. make,
A case where the number of the second data is larger than the number of data determined from a recording area in which the first data is recorded,
If the excess data of a plurality of bits occurs consecutively in the same data block, the excess data having the data length corresponding to the number of differences between the two is deleted from the previously specified excess data portion of the second data. To create correction data,
In the case where single-bit data excess occurs at a plurality of locations in the same data block, excess data for one clock is deleted from the plurality of data excess locations specified in advance of the second data to correct the correction data. To create
A data reproducing method, wherein the correction data is decoded into third data, and the third data is subjected to error correction. A recording area measuring unit that detects the recording area of the recording medium having a plurality of recording areas, measures the number of data recorded in the recording area, and outputs the measured number as a planned number;
Data holding means for holding data read from the recording medium for each recording area;
Error position specifying means for specifying an error occurrence position of the read data;
Error position storage means for storing a plurality of error positions identified by the error position identification means,
A clock missing correction unit or / and an excessive clock correction unit,
The clock omission correction unit,
In the case where the number of the read data is smaller than the planned number of measurements,
When a plurality of missing bits occur consecutively in the same data block, predetermined pseudo data having a data length corresponding to the number of differences between them is stored in accordance with the position information from the error position specifying means. Insert into the data held in the means,
When a single bit is missing at a plurality of locations in the same data block, the pseudo data for one clock is replaced with the data held in the data holding unit in accordance with the position information from the error position specifying unit. To be inserted,
The clock excess correction unit,
In the case where the number of the read data is larger than the planned number of measurements,
In the case where data excess of a plurality of bits occurs consecutively in the same data block, the excess data having a data length corresponding to the number of differences between the two is written to the data holding unit in accordance with the position information from the error position identification unit. From the data stored in
When a single-bit data excess occurs at a plurality of locations in the same data block, the excess data for one clock is transferred to the data holding unit in accordance with the position information from the error location identification unit for each data excess occurrence location. A data reproducing apparatus for deleting data stored in the data reproducing apparatus.

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