JP3539077B2 - Division method by parallel operation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a division method by a parallel operation system used in an operation circuit such as a central processing unit.

[0002]

2. Description of the Related Art Conventionally, in a digital operation, a CPU is used.
In addition to the method performed by software in the (central processing unit), dedicated hardware must be used to perform high-speed calculations. In particular, when performing division, a dedicated high-speed divider is used.
It becomes one integrated circuit (LSI), which leads to an increase in circuit scale and cost. Therefore, a high-speed divider having an appropriate speed and circuit scale is desired.

[0003]

However, in the conventional dividing method, there is a problem in that the circuit scale becomes large when trying to improve the speed, and the speed is reduced when trying to reduce the circuit scale.

Accordingly, an object of the present invention is to provide a division method based on a parallel operation method capable of high-speed division without increasing the circuit scale.

[0005]

In order to achieve the above-mentioned object, a division method using a parallel operation system according to the present invention comprises:
While the dividend of bits is shifted upward by n bits, the upper n + i of the dividend (i = 1, 2,..., M;
N / n) bits and 2 ⁿ -1 shifted by one lower bit
And n N-bit divisors are added to each other, and an n-bit code indicating a divisor whose addition result is a positive maximum value among 2 ⁿ −1 N-bit divisors is added below the dividend. Is repeated m times, a code string indicating the divisor having the positive maximum value is defined as a quotient, and a code string including the code indicating the divisor when m = 1 and the dividend is remainder.

[0006]

Embodiments of the present invention will be described below with reference to the drawings.

A. Embodiment A-1. 1 is a flowchart showing a procedure (algorithm) of a division method by a parallel operation method according to an embodiment of the present invention, and FIG. 2 is a divider to which a division method by a parallel operation method of the present invention is applied. FIG. 3 is a conceptual diagram showing an example of the configuration of FIG. First,
With reference to FIG. 2, the configuration of a divider to which the division method according to the parallel operation method of the present invention is applied will be described. In the present invention, the division A is assumed to be A / B, and the dividend A is shifted by many bits in the division process. In this embodiment, an example in which division is performed by 2-bit shift will be described. . In FIG. 2, reference numeral 1 denotes a 65-bit shift register that stores a dividend A (32 bits). In an initial state, the dividend A is stored in lower 32 bits. In the division process, the dividend A is shifted upward by two bits, and the operation result (2 bits) obtained in the division process is input from the lower side.

Further, 2a, 2b and 2c are divisors B, respectively.
(32 bits) is a 35-bit addition unit, which is used for calculation by shifting the lower one bit in each division process. Further, as described above, in the present embodiment, division is performed by 2-bit shift,
A set of adder units is used.

In the division method according to the present embodiment, the upper 30 bits to the 34th bit (C in the figure) of the shift register 1 and the divisor B stored in the addition units 2a, 2b, 2c are each replaced by the lower 2 bits. A code (2 bits: 01, 10, 11) indicating an addition unit whose addition result takes a positive maximum value is input from the LSB side of the shift register 1, and the dividend A is shifted upward by 2 bits. The division is performed by repeating a series of operations of performing a predetermined number of times (16 times for a 32-bit shift and 16 times for a 16-bit shift in a 2-bit shift).

B. Operation of Embodiment Next, the procedure of the division method by the above-described parallel operation method will be described. First, prior to the division, if the dividend A and the divisor B are 16 bits, conversion to 32 bits is performed, and if the dividend A and the divisor B are 32 bits, they are left as they are.
Next, in step S10 shown in FIG. 1, the dividend A and the divisor B are encoded.

Next, in step S12, it is checked whether the dividend A and the divisor B have the same sign or different signs, and the dividend A is a positive integer and the divisor B is a negative integer. this is,
In the present invention, by performing sign extension and performing addition,
This is because the subtraction is performed. Next, step S14
As shown in FIG. 2, the upper 35 bits (including the upper 2 bits of the dividend A) C of the shift register 1 and the divisors B1, B2, and B3 (lower 2 bits) of the addition units 2a, 2b, and 2c.
(Divisor with shifted bits).

Next, in step S16, the addition unit having the maximum positive value is selected from the addition results (C + B1, C + B2, C + B3). For example, when the addition result (C + B3) corresponding to the addition unit 2c has a positive maximum value, the addition unit 2c is selected. Next, in step S18, the dividend A of the shift register 1 is shifted to the left (upper side) by 2 bits as shown in FIG.
In step S20, a code (in this case, "11") indicating the addition unit selected in the above step is input from the LSB of the shift register 1. Note that, in the operation process, the 30th to 64th bits of the shift register 1 are represented by the symbol D.

[0013] Then, in step S 22, it is determined whether or not performing an operation a predetermined number of times, does not reach the predetermined number, the flow returns to step S14. Hereinafter, steps Sl4 to
S20 is performed a predetermined number of times (16 times for 32 bits, 16 times
(8 times for bits). Here, FIG. 4 is a schematic diagram showing a state in the last operation process, and as shown, the dividend A is shifted to the 30th to 61st bits of the shift register l.
In this state, the above calculation is performed, and the addition result (D10B
1, D 十 B2, D 十 B3), the addition unit having the maximum positive value is selected, and the dividend A of the shift register 1 is shifted to the left (upper side) by 2 bits as shown in FIG. ,
The code indicating the addition unit selected in the above step is input from the LSB of the shift register 1.

As a result, as shown in FIG. 5, a division result (quotient) is obtained at the 0th to 31st bits of the shift register 1, and a remainder is obtained at the 30th to 64th bits of the shift register 1. . Next, in step S24,
If the division result is the same sign, the division result is used as it is. On the other hand, if the division result is a different sign, sign extension (encoding) is performed.
In the case of unsigned data, since the encoding time is not required, the division can be performed at higher speed.

As described above, in the above-described embodiment, 3
In the case of 2-bit data, calculation can be performed in 16 cycles, and in the case of 16-bit data, calculation can be performed in 8 cycles (including encoding, 18 and 10 cycles). Also, 3
Assuming a bit shift, for 32-bit data, 1
In one cycle, in the case of 16-bit data, calculation can be performed in six cycles (13 cycles and 8 cycles including encoding).

[0016]

As described above, according to the present invention, the upper n + i (i = 1, 2,..., M;
m = N / n) bits and 2 ⁿ shifted by 1 lower bit
−1 N-bit divisors are added, and 2 ⁿ −1
Of the N-bit divisors, a code indicating the divisor having the positive maximum value is repeated m times by adding an n-bit code indicating the divisor whose addition result is the maximum positive value to the lower part of the dividend. By using a string as a quotient and leaving a code string consisting of a code indicating the divisor when m = 1 and the dividend as a remainder, an advantage is obtained in that division can be performed at high speed without increasing the circuit scale. Can be

[Brief description of the drawings]

FIG. 1 is a flowchart illustrating a procedure (algorithm) of a division method using a parallel operation method according to an embodiment of the present invention.

FIG. 2 is a conceptual diagram illustrating a configuration example of a divider to which a division method based on a parallel operation method is applied.

FIG. 3 is a schematic diagram for explaining a division process.

FIG. 4 is a schematic diagram for explaining a division process.

FIG. 5 is a schematic diagram for explaining a division process.

[Explanation of symbols]

1 shift register, 2a, 2b, 2c addition unit.

Claims (4)

(57) [Claims] 1. While shifting an N-bit dividend upward by n bits, the highest n + i (i = 1, 2, 2)
..., M; m = N / n) bits and 2 ⁿ −1 N-bit divisors shifted by the lower one bit, respectively, and among the 2 ⁿ −1 N-bit divisors, Repeating the addition of an n-bit code indicating the divisor having a positive maximum value to the lower part of the dividend m times, the quotient is a code string indicating the divisor having the positive maximum value, and m = 1 And a code string consisting of a code indicating the divisor and the dividend as a remainder. 2. The method according to claim 1, wherein the shift is n = 2 bits. 3. The division method according to claim 1 , wherein when the dividend and the divisor are N = 16 bits, the dividend and the divisor are converted into 32 bits in advance. 4. The division method according to claim 1, wherein the dividend is converted into a positive integer and the divisor is converted into a negative integer before the m iterations.