JP2674507B2 - Bit error number calculation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit error number calculation circuit, and more particularly to a bit error number calculation circuit for a frame synchronization pattern in a frame synchronization detection circuit used for PCM communication.

[0002]

2. Description of the Related Art As shown in FIG. 6, a conventional bit error number calculating circuit outputs from a bit error judging section 1 for detecting an error of each bit in a frame synchronization pattern of PCM data and a bit error judging section. The carry-look-ahead adder 2 that calculates the number of error bits contained in the frame synchronization code from the error information for each bit by a cascade-structured adder and the error bit number from the carry-like ahead adder And a look-ahead comparator 3 that compares the number of error bits with the number.

An example of the structure of a conventional carry look-ahead adder 2 is shown in FIG. This example shows the case where the frame synchronization pattern is L = 32 bits. The error occurrence bit of the constituent bits of the frame synchronization pattern is "1" in the binary representation by the bit error determination unit 1 , and is composed of a cascaded full adder that sequentially adds each bit. There is. In this case, the final addition result is obtained by passing the full adder through 20 stages, and the obtained bit error number is compared with the allowable bit error number by the look-ahead comparator 3, and the result of the magnitude judgment is obtained. Is output.

In the carry look-ahead adder 2, as shown in FIG. 7, 1 to 3 bits are fully added by the full adder 00, and the addition output S and the next 4, 5 bits are fully added by the full adder 10. The addition output S and the next 6 and 7 bits are fully added by the full adder 20 until the 32nd bit. The full addition output S of the full adder 150 becomes bo which is the least significant bit (LSB) of the bit error number.

Carry output C of full adder 00-150
(16 bits) are full adders 01, 11, 21, ...
The total addition output S of the full adder 71 becomes the second bit b1 of the bit error number. These carry adders 01, 11, 21, ..., 71 carry outputs C
(8 bits) are fully added by the full adders 02, 12, 22, 32, and the full addition output S of the full adder 32 becomes the third bit b2 of the bit error number.

In the same manner, the final full adder 04
The addition output S and the carry output C are the fifth bit b4 of the bit error number and the most significant bit (MSB) b5.

In this case (L = 32 bits), the carry-look-ahead adder has 20 stages as shown in the lower part of FIG.

[0008]

In this conventional error bit number calculating circuit, since the carry-look-ahead adder having a cascade structure is used to add the bit error numbers, the frame synchronization pattern length is calculated. L, where N is the number of addition stages required to obtain the final addition result, N = {INT (L / 2) -1} + INT (log2L) ………… (1), which is calculated by increasing the number of addition stages. It caused a decrease in speed.

Further, using the result of addition by the carry-look-ahead addition method until the final stage of addition, a binary value (0, 0, 2 having a weight of 2 ⁱ represented by S = ΣS ⁱ 2 ⁱ (2) Since addition is performed until Si of 1) is obtained, the number of addition stages is increased as compared with carry-save addition, resulting in a reduction in calculation speed.

In the equations (1) and (2), INT
(X) indicates an integer value of X, Si corresponds to each bit of the addition result represented by bit binary, and S indicates the addition result. It is an object of the present invention to provide a bit error number calculation circuit that reduces the number of addition stages to improve the calculation speed.

[0011]

A bit error number calculation circuit according to the present invention calculates the number of errors by inputting bit error information indicating the error of each constituent bit of a data pattern consisting of a predetermined number of bits corresponding to each bit. A bit error number calculation circuit for dividing each of the constituent bits of the bit error information into a plurality of groups, for each group, performing full addition of each constituent bit, and adding outputs of these full additions and carry. totally adding outputs together each independently, which like repeated addition process to carry output of full adder result is 1 bit, overflow of the adder output in the middle of the addition process for each group-bi
Bit and the above-mentioned 1 bit are stored in the same weight bit respectively.
Carry save type full addition processing
It is characterized in that each addition output and each carry output of the addition processing are the number of bit errors.

Another bit error number calculating circuit according to the present invention detects a frame synchronization pattern in a data stream.
In the frame synchronization detector, the frame synchronization pattern
Error in each constituent bit of the
A bit error number calculation circuit for calculating the number of errors by inputting bit error information in which each error is displayed corresponding to each bit, and dividing each constituent bit of the bit error information into a plurality of groups. For each of them, each constituent bit is fully added, and the addition outputs of these full additions and carry outputs are independently added individually, and addition processing is performed until the carry output of these full addition results becomes 1 bit. Repeat,
The overflow bit of the addition output in the middle of the addition process for each group and the above-mentioned 1 bit are carry save type full addition process with the same weight bits, and each addition output and carry of these carry save type full addition process It is characterized in that the output and the number of bit errors are set.

[0013]

Since the error bit is "1" and it is sufficient to know the total number of "1" bits, each bit is added by a full adder instead of the conventional carry look ahead addition, and these additions are performed. By performing full addition of the result addition outputs and carry outputs independently and repeating the addition process until the carry output of these addition results becomes 1 bit, it is possible to obtain a fast result with a small number of addition stages. Become.

[0014]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. In this embodiment, the number of bits of the frame synchronization pattern is L
Is 32, the bit error detection unit 1 detects an error in each constituent bit of the frame synchronization pattern, and it is determined whether each bit of the input frame synchronization pattern matches each bit of the reference pattern. If they do not match, the corresponding bit of the input frame synchronization pattern is erroneous, so the corresponding bit is derived as "1", and if they match, the corresponding bit is derived as "0". .

The 32-bit bit error information output from the bit error determination unit 1 is input to so-called tree type carry look ahead adders 4a to 4c and subjected to high speed addition processing. In this example, three tree-type carry-look-ahead adders 4a to 4c are provided in parallel in order to obtain a higher speed operation, and 32-bit inputs to each of these adders 4a to 4c are shown as three groups (L / 3). It is designed to be supplied separately.

A concrete example of the tree-type carry-look-ahead adder is shown in FIG. 2, in which the first to twelfth 12 bits of the 32-bit bit error information output from the bit error determination unit 1 are sent to the adder 4a. , The 13th to 24th 12 bits are input to the adder 4b and the remaining 25th to 32nd 8 bits are input to the adder 4c to perform high-speed processing in parallel for each group.

In addition to performing parallel addition by dividing it into a plurality of groups, tree-type carry-look-ahead addition is further performed to increase the speed, and each bit of the input bit error information is weighted. First, as shown in FIG. 2, 3 of the 1st to 12th bits are not included.
Each bit is subjected to full addition processing by four full adders 00-03. It should be noted that each of the 13th to 24th bits, 3 bits at a time,
The addition is performed in parallel by the adder 4b and is also performed in parallel by the adder 4C for 3 bits × 2 and 2 bits of the 25th to 32nd bits, and the same applies hereinafter.

The three addition outputs S of the three full adders 00 to 02 are fully added by the next full adder 10, and the addition output S and the addition output S of the previous full adder 03 are sent to the next full adder 20. Is fully added.

The three carry outputs C of the three full adders 00 to 02 are fully added by the full adder 30, and the carry outputs C of the full adders 10, 20 and 03 are fully added by the full adder 31. At this time, full adder 20
Of the addition result S becomes an overflow bit, and this is output as the first bit (LSB) b00 of the addition result.

The addition outputs S of the full adders 30 and 31 are fully added by the full adder 40, and the carry output C
The carry output C of the full adder 30 and the carry output C of the full adder 31 are fully added by the full adder 50.
The addition outputs of the full adders 40 and 50 become overflow bits, which are output as the second bit b01 and the third bit b02 of the addition result.

The above addition process is repeated until the carry output C of the addition result finally becomes 1 bit. In this example, the carry output C of the full adder 50 corresponds to that.
This carry output C is the most significant bit (MS
B) It is output as b03.

In the free carry carry look-ahead adders 4b and 4c of the other groups, similarly, b10 to b13 and b20 to b23 are respectively obtained as addition results. Then, the addition result of each of these 4 bits is compared with the error allowable bit number (preset) by the carry save addition / comparator 5, and is derived as a comparison output (see FIG. 1). ).

If L = 32-bit addition is divided into three groups and processed in parallel using this tree-type carry-look-ahead adder, the number of addition stages becomes 6, as shown in FIG. It is clear that the addition speed is improved.

FIG. 3 is a diagram showing an example of the carry save adder / comparator 5 of FIG. The 4-bit addition results of the tree-type carry lookahead adders 4a to 4c shown in FIG.
In consideration of each weight, they are input to the full adders 5a to 5d, respectively. That is, 3 bits of (b00, b10, b20) are input to the full adder 5a, and (b01, b11, b2)
3 bits of 1) are input to the full adder 5b, and (b0
3 bits (2, b12, b22) are input to the full adder 5C, and 3 bits (b03, b13, b23) are input to the full adder 5d.

In this addition, the carry bits C1 to C4 of each bit are preserved and are not propagated to the full adder of the digit of the next bit on the MSB side, and are input to the carry save comparators (5e to 5i). The data input to this carry save comparator is always Si with a weight of 2 ^i.
And Ci, and is represented by bAi = (Si + Ci) 2 ⁱ = Vi2 ⁱ . Note that Vi has three values of (0, 1, 2).

Carry save comparators 5e to 5i carry out a carry save comparison between the addition result ΣbAi represented by a binary number having the ternary weight Vi and the allowable bit error number ΣbRi. This comparison is performed sequentially from the upper digit to the lower digit.

FIG. 4 shows the carry save comparators 5e-5.
It is a circuit diagram of a specific example of i. In the figure, the addition result bit bA input in 2 bits is the carry extraction unit 6a.
And a carry bit bAC and a sum bit bAS representing the sum of two bits are output.

The bA> bR determination unit 6b inputs the magnitude determination result bA> bR of bA and bR from the upper carry save comparator (hereinafter abbreviated as CSC), and bA is larger than bR (bA> bR signal). Of the carry bit bAC is "1" or the sum bit bAS is larger than the reference value bR (bAS> bR), the addition result bit bA is larger than the reference value bR. Then, the bA> bR signal is output as a logic “1”.

However, the signal of the judgment result (bA <bR) of bA and bR from the upper CSC is input to the upper CSC.
If bA is smaller than bR ((bA <bR) signal logic “1”), the bA> bR signal is output as logic “0”, and the bA <bR determination unit determines whether bA and bR are large or small. The magnitude is determined by the bA <bR signal and the (bA <bR) signal which are the result signals.

The bA <bR determination unit 6c outputs a bAS≠bR signal indicating that the sum bit bAS from the bA> bR determination unit 6b is not equal to the reference value bR, and bA indicating that bA is equal to or smaller than bR. If the signal ≦ bR is input and the logic is true, a signal (bA <bR) indicating that the addition result bit bA is smaller than the reference value bR is output. However, if the logic of the bA <bR signal is true (“1”), which indicates that the addition result bit bA is determined to be smaller than the reference bR as a result of the magnitude judgment of bA and bR from the upper CSS,
The (bA <bR) signal and the bA <bR signal are output as logic “1” and output to the lower CSC.

The bA <bR signal is in the higher CSC, the logic of the (bA <bR) signal is “1” (the addition result bit bA is smaller than the reference value bR), and the carry bit bAC is the same. When the logic is "0", the logic of the sum bit bAS is "0" (a carry to the upper CSC does not occur due to a carry from the lower CSC), or
The logic of the reference value bR is "1" (even if the carry from the lower CSC to the upper CSC occurs, the sum bit b
If AS is smaller than the reference value bR), it is determined that the addition result bit bA has a value smaller than the reference value bR, and the bA <bR signal is output as a logic “1”.

By carrying out the above-mentioned size judgment sequentially from the upper CSC 5i to the lower CSC 5e, it is possible to finally carry out the size comparison with respect to the reference value.

In the above embodiment, the constituent bits (L = 32) of the bit error information of the frame synchronization pattern are grouped into three groups. In this grouping, the number of bits in one group becomes an integral multiple of three. That is the most efficient way to use a full adder (because a full adder has 3 inputs). Therefore, in the 32-bit example, it is simply 3
It is 10.6 bits each when divided by, but the first group 4
It is more efficient to use 12 bits as the number of bits of a. Therefore, the first and second groups have 12 bits each, and the third group has the remaining 8 bits, so that the full adder is used most efficiently. .

The three groups are the full adders 5a to 5a of the carry save adder (FIG. 3) in the next stage.
5b is a 3-bit input,
This is because it can be used efficiently.

Even if the parallel processing is not performed as three groups and the input L = 32 bits is directly supplied to the single tree carry-look-ahead adder, the conventional addition stage number 20 shown in FIG. Has fewer steps. An example thereof is shown in FIG.

As can be seen from the example of FIG. 5, it is obvious that the conventional 20 stages has been completed by the addition process of 12 stages, which alone makes the speed higher.

[0038]

As described above, according to the present invention, since carry-look-ahead addition has a tree structure, the number of addition stages can be significantly reduced and high-speed processing can be performed. Furthermore, by dividing the input bits into a plurality of groups (3 groups are ideal) and performing the tree-type carry look-ahead addition in parallel for each group, the number of addition stages can be further reduced and the speed can be increased.

[Brief description of the drawings]

FIG. 1 is a system block diagram of an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a tree-type carry lookahead adder shown in FIG. 1;

3 is a diagram showing an example of a carry save adder / comparator in FIG. 1. FIG.

FIG. 4 is a specific circuit diagram of the carry-save comparator (CSC) shown in FIG.

FIG. 5 is a circuit diagram of another embodiment of the present invention.

FIG. 6 is a system block diagram of a conventional bit error calculation circuit.

7 is a circuit diagram showing an example of the carry look ahead adder shown in FIG. 6;

[Explanation of symbols]

 1-bit error determination unit 4a to 4c Tree type carry look-ahead adder 5 Carry save adder / comparator

Claims (3)

(57) [Claims] 1. A bit error number calculation circuit for calculating the number of errors by inputting bit error information in which an error of each constituent bit of a data pattern having a predetermined number of bits is displayed corresponding to each bit. Each configuration bit of each is divided into multiple groups, and each configuration
The total output of each
The carry outputs are added independently, and the totals are added together.
Repeat the addition process until the carry output of the result becomes 1 bit.
However, the overflow output of the addition output of the addition processing in the middle of each group
Bit and the above-mentioned 1 bit are stored in the same weight bit respectively.
Carry save type full addition processing
Number of bit errors between each addition output and each carry output of addition processing
The bit error rate computation circuit, characterized in that the the. 2. A frame synchronization pattern in a data stream.
In the frame synchronization detection unit for detecting frames, the frame
Error in each constituent bit of the system synchronization pattern is detected,
A bit error number calculation circuit for calculating the number of errors by inputting bit error information in which each error of the component bits is displayed corresponding to each bit, wherein each component bit of the bit error information is grouped into a plurality of groups. , Each constituent bit is fully added for each group, and the addition outputs of these full additions and carry outputs are independently added individually, and the carry output of these full addition results is 1 bit. The addition process is repeated until the following, and the overflow bit of the addition output of the addition process in the middle of each group and the above-mentioned 1 bit are carry-save full addition process with the same weight bits respectively, and carry-save full addition process is performed. A bit error number calculation circuit, wherein each addition output and each carry output is set as a bit error number. 3. The bit error number calculation circuit according to claim 1, wherein the bit error number calculation circuit is configured to perform magnitude comparison between the bit error number and a preset allowable error bit number.