JP3522482B2 - Method for manufacturing SOI substrate - Google Patents

Method for manufacturing SOI substrate

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Publication number
JP3522482B2
JP3522482B2 JP03884897A JP3884897A JP3522482B2 JP 3522482 B2 JP3522482 B2 JP 3522482B2 JP 03884897 A JP03884897 A JP 03884897A JP 3884897 A JP3884897 A JP 3884897A JP 3522482 B2 JP3522482 B2 JP 3522482B2
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JP
Japan
Prior art keywords
thin film
substrate
semiconductor substrate
heat treatment
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP03884897A
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Japanese (ja)
Other versions
JPH10242154A (en
Inventor
充 須藤
勝 高松
哲弥 中井
Original Assignee
三菱住友シリコン株式会社
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Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、酸化層が形成され
た第1半導体基板に水素イオン注入を行った後に、この
半導体基板を酸化層を接合面として、支持基板となる別
の第2半導体基板に接合し、第1半導体基板を水素イオ
ン注入部分で第2半導体基板から分離することにより、
第2半導体基板の表面に単結晶薄膜を有するSOI基板
を製造する方法に関するものである。
TECHNICAL FIELD The present invention relates to an oxide layer formed.
After performing hydrogen ion implantation on the first semiconductor substrate,
Separate the semiconductor substrate as the supporting substrate with the oxide layer as the bonding surface.
Bonded to the second semiconductor substrate of the
By separating from the second semiconductor substrate at the injection part,
SOI substrate having single crystal thin film on surface of second semiconductor substrate
The present invention relates to a method of manufacturing .

【0002】[0002]

【従来の技術】単結晶の薄膜を基板上に有する半導体基
板の代表例として、SOI基板が挙げられる。このSO
I基板は将来の超高集積回路(ULSI)基板として注
目されてきている。このSOI基板の製造方法には、
シリコン基板同士を絶縁膜を介して貼り合わせる方法、
絶縁性基板又は絶縁性薄膜を表面に有する基板の上に
シリコン薄膜を堆積させる方法、シリコン基板の内部
に高濃度の酸素イオンを注入した後、高温でアニール処
理してこのシリコン基板表面から所定の深さの領域に埋
込みシリコン酸化層を形成し、その表面側のSi層を活
性領域とするSIMOX法などがある。また最近、第1
半導体基板に水素イオン注入を行った後に、この半導体
基板をイオン注入面を接合面として、支持基板となる別
の第2半導体基板に接合し、第1半導体基板を水素イオ
ン注入部分で第2半導体基板から分離し、第2半導体基
板の表面に薄膜を有する半導体基板を製造する方法が提
案されている(特開平5−211128)。この方法で
は、イオンを半導体基板の内部に表面から均一に注入で
きれば、均一な厚さの薄膜を有する半導体基板が得られ
る。また支持基板となる第2半導体基板の表面に予め酸
化層を設けておけば、この方法によりSOI基板を製造
することができる。
2. Description of the Related Art An SOI substrate is a typical example of a semiconductor substrate having a single crystal thin film on the substrate. This SO
The I substrate has attracted attention as a future ultra-high integrated circuit (ULSI) substrate. This SOI substrate manufacturing method includes:
A method of bonding silicon substrates to each other via an insulating film,
A method of depositing a silicon thin film on an insulative substrate or a substrate having an insulative thin film on the surface, a high concentration of oxygen ions is implanted into the inside of the silicon substrate, and then annealed at high temperature to obtain a predetermined amount from the surface of the silicon substrate. There is a SIMOX method in which a buried silicon oxide layer is formed in the depth region and the Si layer on the surface side is used as the active region. Also recently, the first
After hydrogen ion implantation is performed on the semiconductor substrate, this semiconductor substrate is bonded to another second semiconductor substrate that serves as a supporting substrate with the ion implantation surface as a bonding surface, and the first semiconductor substrate is bonded to the second semiconductor substrate at the hydrogen ion implantation portion. A method has been proposed in which a semiconductor substrate having a thin film on the surface of the second semiconductor substrate is manufactured by separating it from the substrate (Japanese Patent Laid-Open No. 511128/1993). In this method, if the ions can be uniformly injected into the inside of the semiconductor substrate from the surface, a semiconductor substrate having a thin film having a uniform thickness can be obtained. Further, if an oxide layer is provided in advance on the surface of the second semiconductor substrate to be the supporting substrate, the SOI substrate can be manufactured by this method.

【0003】一方、近年マイクロエレクトロニクスデバ
イスの高集積化、デバイス最小寸法の縮小に伴い、ウェ
ーハ表面の清浄度とともにウェーハ表面の微視的ラフネ
ス、即ちマイクロラフネス(micro-roughness)が重要
視されてきている。特にマイクロラフネスはデバイスの
酸化膜耐圧などの電気特性に大きな影響を与えることが
認識されている((M.Morita, et al.,"Effect of Si wa
fer surface micro-roughness on electrical properti
es of very-thin gate oxide films", ULSI Science an
d Technology/1991,pp.400-408, Electrochem, Society
(1991))。なお、ここでマイクロラフネスは1μm以
下数nmのオーダの表面粗さをいう。
On the other hand, in recent years, with the high integration of microelectronic devices and the reduction of the minimum device size, the cleanliness of the wafer surface as well as the micro-roughness of the wafer surface have been emphasized. There is. In particular, it is recognized that microroughness has a great influence on the electrical characteristics such as the breakdown voltage of the oxide film of the device ((M. Morita, et al., "Effect of Si Wa
fer surface micro-roughness on electrical properti
es of very-thin gate oxide films ", ULSI Science an
d Technology / 1991, pp.400-408, Electrochem, Society
(1991)). Here, the microroughness means a surface roughness on the order of 1 μm or less and several nm.

【0004】上記特開平5−211128号公報に示さ
れた方法で、第1半導体基板を分離した直後の第2半導
体基板の表面に存する薄膜の平均粗さは、初期のシリコ
ン基板表面の平均粗さが0.1nm以下であるのに対し
て、この平均粗さの10倍以上であり、マイクロラフネ
スが比較的大きく、上述した酸化膜耐圧などの電気特性
に悪影響を及ぼすおそれがある。特にこの方法では、第
1半導体基板の分離により形成された薄膜の表面は、熱
処理に伴う微小な気泡の形状が残っているためにマイク
ロラフネスが大きく、デバイスの作製には適さない。こ
の点を解決するため、第1半導体基板を分離した後の第
2半導体基板上の薄膜表面をタッチポリッシュ(touch
polishing)と呼ばれる、軽い研磨を施して、これらの
表面粗さを初期の基板表面の粗さ程度のマイクロラフネ
スにしている(M.Bruel et al.,"A Promising New SOI
Material Technology" IEEE International SOI Confer
ence proceedings,pp.178-179 (1995))。
The average roughness of the thin film existing on the surface of the second semiconductor substrate immediately after the first semiconductor substrate is separated by the method disclosed in Japanese Patent Laid-Open No. 511128/1993 is the average roughness of the initial surface of the silicon substrate. Is 0.1 nm or less, the average roughness is 10 times or more, and the microroughness is relatively large, which may adversely affect the electrical characteristics such as the oxide film withstand voltage. In particular, according to this method, the surface of the thin film formed by separating the first semiconductor substrate has a large microroughness because the shape of minute bubbles due to the heat treatment remains, and is not suitable for device fabrication. In order to solve this problem, the thin film surface on the second semiconductor substrate after the first semiconductor substrate is separated is touch-polished.
The surface roughness is made to be microroughness equivalent to the roughness of the initial substrate surface, called "polishing" (M.Bruel et al., "A Promising New SOI").
Material Technology "IEEE International SOI Confer
ence proceedings, pp.178-179 (1995)).

【0005】[0005]

【発明が解決しようとする課題】しかしながら、現状の
タッチポリッシュの技術を、上記方法で作製した厚さ数
百nm以下の極めて薄い薄膜に適用した場合には、薄膜
表面を平坦化することはできるが、面内で研磨量のばら
つきがあるため、薄膜の厚さ分布が大きくなる不具合が
あった。この薄膜の厚さ分布が大きいため、研磨後の薄
膜半導体基板を用いてデバイスを作製した場合には、デ
バイスの特性がばらつく問題点があった。本発明の目的
は、第2半導体基板上に形成された単結晶薄膜が厚さ数
百nm以下の極めて薄い薄膜であっても、薄膜の厚さを
変えずにかつ面内の厚さのばらつきを大きくせずに、薄
膜の平均表面粗さを0.1nmオーダーに改善するSO
I基板の製造方法を提供することにある。
However, when the current touch polishing technique is applied to an extremely thin thin film having a thickness of several hundreds nm or less produced by the above method, the thin film surface can be flattened. However, there is a problem that the thickness distribution of the thin film becomes large due to the variation in the polishing amount within the surface. Since the thickness distribution of this thin film is large, there is a problem in that when the device is manufactured using the thin film semiconductor substrate after polishing, the device characteristics vary. An object of the present invention is to provide a single crystal thin film formed on a second semiconductor substrate, which is an extremely thin thin film having a thickness of several hundreds nm or less, without changing the thickness of the thin film and in-plane thickness variation. SO for improving the average surface roughness of thin films to the order of 0.1 nm without increasing the thickness
It is to provide a method for manufacturing an I substrate .

【0006】[0006]

【課題を解決するための手段】請求項1に係る発明は、
図1(a)〜(e)に示すように、基板表面に酸化層1
1aが形成された第1半導体基板11に水素イオンを注
入してこの第1半導体基板11内部にイオン注入による
損傷領域11bを形成し、この半導体基板11を上記酸
化層11aの表面を接合面として支持基板となる別の第
2半導体基板12に接合し、これら接合した2枚の半導
体基板11,12を熱処理することにより第1半導体基
板11を上記損傷領域11bのところで割って第2半導
体基板12から分離して第2半導体基板12の接合面に
単結晶薄膜13を残存させ、この分離直後又は上記単結
晶薄膜13を有する第2半導体基板12を熱処理してこ
の単結晶薄膜13の化学結合を強固にした直後に、上記
単結晶薄膜13を有する第2半導体基板12を活性雰囲
気中で1000〜1300℃の温度で10分〜5時間熱
処理することにより上薄膜の平均表面粗さを0.1nm
オーダーにすることを特徴とするSOI基板の製造方法 上記条件で半導体基板を熱処理すると、基板上の薄膜表
面の原子は活性な状態となって、移動し易くなり、薄膜
の平均表面粗さを0.1nmオーダーにする。請求項2
に係る発明は、請求項1に係る発明であって、薄膜13
がシリコン薄膜であって、活性雰囲気が水素雰囲気であ
って、熱処理温度が1000〜1300℃であるSOI
基板の製造方法である。上記条件でシリコン薄膜を水素
雰囲気中で熱処理することにより、薄膜の表面粗さを小
さくすることに加えて、シリコン中に存在する微小欠陥
を低減し、シリコン中にドーパントとして含まれるボロ
ンの濃度を制御することができる。
The invention according to claim 1 is
As shown in FIGS. 1A to 1E , an oxide layer 1 is formed on the substrate surface.
Inject hydrogen ions into the first semiconductor substrate 11 on which 1a is formed.
By ion implantation into the first semiconductor substrate 11
A damaged region 11b is formed, and the semiconductor substrate 11 is treated with the above acid.
Another surface that serves as a support substrate with the surface of the oxidization layer 11a as a bonding surface.
2 Joined to the semiconductor substrate 12, these two joined semiconductors
The first semiconductor substrate is formed by heat-treating the body substrates 11 and 12.
The plate 11 is divided at the damaged area 11b to separate the second semiconductor.
Separated from the body substrate 12 and attached to the bonding surface of the second semiconductor substrate 12.
Immediately after this separation or after the single crystal thin film 13 remains
The second semiconductor substrate 12 having the crystalline thin film 13 by heat treatment.
Immediately after strengthening the chemical bond of the single crystal thin film 13 of
The second semiconductor substrate 12 having the single crystal thin film 13 is heat-treated in an active atmosphere at a temperature of 1000 to 1300 ° C. for 10 minutes to 5 hours to obtain an average surface roughness of the upper thin film of 0.1 nm.
Method for manufacturing SOI substrate, which is characterized in that when the semiconductor substrate is heat-treated under the above conditions, atoms on the surface of the thin film on the substrate are in an active state and easily move, and the average surface roughness of the thin film is 0. Set to 1 nm order. Claim 2
The invention according to claim 1 is the invention according to claim 1, wherein the thin film 13
There a silicon thin film, inert atmosphere is a hydrogen atmosphere, SOI heat treatment temperature of about 1000 to 1300 ° C.
It is a method of manufacturing a substrate . By heat treating the silicon thin film in a hydrogen atmosphere under the above conditions, in addition to reducing the surface roughness of the thin film, minute defects existing in silicon are reduced, and the concentration of boron contained as a dopant in silicon is reduced. Can be controlled.

【0007】[0007]

【発明の実施の形態】本発明の熱処理時の活性雰囲気と
しては、水素雰囲気、塩酸雰囲気、フッ化炭素雰囲気が
あるが、表面処理の制御しやすさの点で水素雰囲気が望
ましい。熱処理温度が上記下限値未満で、熱処理時間が
上記下限値未満では、薄膜表面の原子の活性度が低く、
その表面粗さを0.1nmオーダーにすることができな
い。また熱処理温度が上記上限値を越え、熱処理時間が
上記上限値を越えると、活性元素によるエッチングが進
んで、熱処理前よりかえって薄膜表面が粗くなる。請求
項1及び請求項2とも、熱処理温度は1100〜120
0℃が好ましく、熱処理時間は1〜2時間が好ましい。
BEST MODE FOR CARRYING OUT THE INVENTION As the active atmosphere during the heat treatment of the present invention, there are a hydrogen atmosphere, a hydrochloric acid atmosphere, and a fluorocarbon atmosphere, and the hydrogen atmosphere is preferable from the viewpoint of easy control of the surface treatment. If the heat treatment temperature is less than the above lower limit and the heat treatment time is less than the above lower limit, the activity of atoms on the thin film surface is low,
The surface roughness cannot be set to the order of 0.1 nm. If the heat treatment temperature exceeds the upper limit value and the heat treatment time exceeds the upper limit value, etching by the active element proceeds, and the thin film surface becomes rough rather than before the heat treatment. In both claim 1 and claim 2, the heat treatment temperature is 1100 to 120.
The temperature is preferably 0 ° C., and the heat treatment time is preferably 1 to 2 hours.

【0008】また本発明の被処理物は、基板上に平均表
面粗さが少なくとも0.2nmである単結晶薄膜を有す
る半導体基板である。0.2nm未満では本発明の処理
方法でこの値以下に表面粗さを小さくできないからであ
る。こうした半導体基板の例としては、SIMOX法で
シリコン基板の内部に高濃度の酸素イオンを注入した
後、高温でアニール処理してこのシリコン基板表面から
所定の深さの領域に埋込みシリコン酸化層を形成したS
OI基板や、特開平5−211128号公報に示された
方法で第1半導体基板を分離した直後の薄膜を有する第
2半導体基板等が挙げられる。
The object to be treated of the present invention is a semiconductor substrate having a single crystal thin film having an average surface roughness of at least 0.2 nm on the substrate. If it is less than 0.2 nm, the surface roughness cannot be made smaller than this value by the treatment method of the present invention. As an example of such a semiconductor substrate, high-concentration oxygen ions are implanted into the silicon substrate by the SIMOX method and then annealed at a high temperature to form a buried silicon oxide layer in a region of a predetermined depth from the surface of the silicon substrate. Did S
Examples thereof include an OI substrate and a second semiconductor substrate having a thin film immediately after separating the first semiconductor substrate by the method disclosed in JP-A-5-211128.

【0009】この方法を図面を用いて説明する。図1
(a)に示すように、シリコンウェーハの第1半導体基
板11を熱酸化により基板表面に酸化層(SiO2層)
11aを形成した後、この基板11に水素イオンを2×
1016/cm2〜1×1017/cm2のドーズ量でイオン
注入する。11bは水素イオン注入による損傷領域であ
る。次いで図1(b)に示すように、上記と同一のシリ
コンウェーハからなる第2半導体基板12を用意する。
図1(c)に示すように、両基板11,12をRCA法
により洗浄した後、基板12上に基板11を室温で接合
する。基板12は支持基板として作用する。図1(d)
に示すように、接合した2枚の基板11,12をアルゴ
ン雰囲気中400〜600℃で第1次熱処理する。これ
により、基板11が損傷領域11bのところで割れ、基
板12から分離する。基板12の接合面には単結晶シリ
コン薄膜13が残存する。この第1次熱処理した後のシ
リコン薄膜13の平均表面粗さは約10nmである。図
1(e)に示すように、分離後、アルゴン雰囲気中約1
100℃で2次熱処理し、シリコン薄膜の化学結合を強
固にする。図1(f)に示すように、薄膜13を有する
基板12を水素雰囲気中で1000〜1300℃の温度
範囲で10分〜5時間の範囲で第3次熱処理する。この
熱処理によりシリコン薄膜13の厚さ及びその分布は変
わらず、平均表面粗さは0.1nmオーダーとなる。ま
た別の方法として1次熱処理の後に、上記第3次熱処理
と同じ水素雰囲気中の熱処理を行っても良い。この場
合、シリコン表面の平坦化とともに、上記第2次熱処理
と同じ効果(張り合わせ強度の増加)も得ることができ
る。
This method will be described with reference to the drawings. Figure 1
As shown in (a), the first semiconductor substrate 11 of the silicon wafer is thermally oxidized to form an oxide layer (SiO 2 layer) on the substrate surface.
After forming 11a, 2 × hydrogen ions are applied to the substrate 11.
Ion implantation is performed at a dose amount of 10 16 / cm 2 to 1 × 10 17 / cm 2 . Reference numeral 11b is a damaged region due to hydrogen ion implantation. Next, as shown in FIG. 1B, a second semiconductor substrate 12 made of the same silicon wafer as above is prepared.
As shown in FIG. 1C, after cleaning both the substrates 11 and 12 by the RCA method, the substrate 11 is bonded onto the substrate 12 at room temperature. The substrate 12 acts as a supporting substrate. Figure 1 (d)
As shown in, the two bonded substrates 11 and 12 are subjected to a first heat treatment at 400 to 600 ° C. in an argon atmosphere. As a result, the substrate 11 is broken at the damaged region 11b and separated from the substrate 12. The single crystal silicon thin film 13 remains on the bonding surface of the substrate 12. The average surface roughness of the silicon thin film 13 after the first heat treatment is about 10 nm. As shown in FIG. 1 (e), after separation, about 1 in argon atmosphere
A second heat treatment is performed at 100 ° C. to strengthen the chemical bond of the silicon thin film. As shown in FIG. 1F, the substrate 12 having the thin film 13 is subjected to the third heat treatment in a hydrogen atmosphere at a temperature range of 1000 to 1300 ° C. for 10 minutes to 5 hours. This heat treatment does not change the thickness of the silicon thin film 13 and its distribution, and the average surface roughness is on the order of 0.1 nm. As another method, after the first heat treatment, the heat treatment in the same hydrogen atmosphere as the third heat treatment may be performed. In this case, the same effect as the second heat treatment (increased bonding strength) can be obtained together with the flattening of the silicon surface.

【0010】[0010]

【実施例】次に本発明の実施例を比較例とともに説明す
る。 <実施例1>厚さ625μmの第1シリコンウェーハを
熱酸化して表面に厚さ500nmの熱酸化膜を形成し
た。このシリコンウェーハに120keV、ドーズ量5
×1016/cm2で水素イオンを注入した。熱酸化前の
上記と同一の第2シリコンウェーハを支持基板として、
第2シリコンウェーハに第1シリコンウェーハを接合し
た。接合前にRCA法により両ウェーハを洗浄した。接
合した両ウェーハを600℃で熱処理した。この熱処理
により第1シリコンウェーハ中の結晶の再配列及び微小
気泡の圧力作用により、ウェーハ内部のイオン注入した
箇所で第1シリコンウェーハが割れて分離し、第2シリ
コンウェーハ上に厚さ500nmのシリコン薄膜を有す
るSOI基板が得られた。このときの薄膜のウェーハ面
内のばらつきは±3nmであった。また表面の平均粗さ
Raは原子間力顕微鏡(AFM)で測定した結果、10
nmであった。このAFMによる薄膜の表面粗さを図2
に示す。このシリコン薄膜付きの第2シリコンウェーハ
を水素雰囲気中1100℃で3時間熱処理した。熱処理
後の薄膜の厚さはウェーハ面内で500±3nmと変わ
らず、表面の平均粗さRaはAFMで測定した結果、
0.1nmであった。この値は初期のシリコンウェーハ
の表面粗さ並みであった。この表面粗さを図3に示す。
EXAMPLES Next, examples of the present invention will be described together with comparative examples. Example 1 A first silicon wafer having a thickness of 625 μm was thermally oxidized to form a thermal oxide film having a thickness of 500 nm on the surface. This silicon wafer has 120 keV and a dose of 5
Hydrogen ions were implanted at × 10 16 / cm 2 . The same second silicon wafer as above before thermal oxidation is used as a supporting substrate,
The first silicon wafer was bonded to the second silicon wafer. Both wafers were cleaned by the RCA method before bonding. Both bonded wafers were heat treated at 600 ° C. Due to the rearrangement of crystals in the first silicon wafer and the pressure action of the minute bubbles by this heat treatment, the first silicon wafer is broken and separated at the ion-implanted portion inside the wafer, and the silicon having a thickness of 500 nm is formed on the second silicon wafer. An SOI substrate having a thin film was obtained. The variation of the thin film on the wafer surface at this time was ± 3 nm. The average surface roughness Ra is 10 as a result of measurement with an atomic force microscope (AFM).
was nm. The surface roughness of the thin film by this AFM is shown in FIG.
Shown in. The second silicon wafer with the silicon thin film was heat-treated in a hydrogen atmosphere at 1100 ° C. for 3 hours. The thickness of the thin film after heat treatment did not change to 500 ± 3 nm in the wafer surface, and the average surface roughness Ra was measured by AFM.
It was 0.1 nm. This value was similar to the surface roughness of the initial silicon wafer. This surface roughness is shown in FIG.

【0011】<実施例2>実施例1と同様にして作製し
たシリコン薄膜付きの第2シリコンウェーハを水素雰囲
気中1200℃で2時間熱処理した。熱処理後の薄膜の
厚さはウェーハ面内で500±3nmと変わらず、表面
の平均粗さRaはAFMで測定した結果、0.12nm
であった。この表面粗さを図4に示す。
Example 2 A second silicon wafer with a silicon thin film produced in the same manner as in Example 1 was heat-treated in a hydrogen atmosphere at 1200 ° C. for 2 hours. The thickness of the thin film after the heat treatment does not change to 500 ± 3 nm within the wafer surface, and the average surface roughness Ra is 0.12 nm as measured by AFM.
Met. This surface roughness is shown in FIG.

【0012】<比較例1>実施例1と同様にして作製し
たシリコン薄膜付きの第2シリコンウェーハをタッチポ
リッシュした。このときの薄膜の平均表面粗さRaは
0.15nmに改善されたが、薄膜の厚さはウェーハ面
内で480±7nmと悪くなった。
Comparative Example 1 A second silicon wafer with a silicon thin film prepared in the same manner as in Example 1 was touch-polished. The average surface roughness Ra of the thin film at this time was improved to 0.15 nm, but the thickness of the thin film was deteriorated to 480 ± 7 nm in the plane of the wafer.

【0013】<比較例2>実施例1と同様にして作製し
たシリコン薄膜付きの第2シリコンウェーハを水素雰囲
気中1350℃で1時間熱処理した。熱処理によりシリ
コン薄膜は水素でエッチングされ、薄膜の厚さはウェー
ハ面内で100±8nmと悪くなり、表面の平均粗さR
aもAFMで測定した結果、5nmと実施例1及び2よ
り悪化していた。
<Comparative Example 2> A second silicon wafer with a silicon thin film produced in the same manner as in Example 1 was heat-treated in a hydrogen atmosphere at 1350 ° C. for 1 hour. Due to the heat treatment, the silicon thin film is etched with hydrogen, and the thickness of the thin film deteriorates to 100 ± 8 nm within the wafer surface, and the average surface roughness R
The value of a was 5 nm, which was worse than that of Examples 1 and 2 as a result of measurement by AFM.

【0014】<比較例3>実施例1と同様にして作製し
たシリコン薄膜付きの第2シリコンウェーハを水素雰囲
気中900℃で5時間熱処理した。薄膜の厚さ、その面
内分布及び表面粗さに変化はなかった。
Comparative Example 3 A second silicon wafer with a silicon thin film prepared in the same manner as in Example 1 was heat-treated in a hydrogen atmosphere at 900 ° C. for 5 hours. There was no change in the thickness of the thin film, its in-plane distribution and the surface roughness.

【0015】[0015]

【発明の効果】以上述べたように、本発明によれば、
板表面に酸化層が形成された第1半導体基板に水素イオ
ンを注入してこの第1半導体基板内部にイオン注入によ
る損傷領域を形成し、この半導体基板を上記酸化層表面
を接合面として支持基板となる別の第2半導体基板に接
合し、これら接合した2枚の半導体基板を熱処理するこ
とにより第1半導体基板を上記損傷領域のところで割っ
て第2半導体基板から分離して第2半導体基板の接合面
に単結晶薄膜を残存させ、この分離直後又はこの単結晶
薄膜を有する第2半導体基板を熱処理してこの単結晶薄
膜の化学結合を強固にした直後に、上記単結晶薄膜を有
する半導体基板を活性雰囲気中で1000〜1300℃
の温度で10分〜5時間熱処理することにより、厚さ数
百nm以下の極めて薄い薄膜であっても、薄膜の厚さを
変えずにかつ面内の厚さのばらつきを大きくせずに、薄
膜の平均表面粗さを0.1nmオーダーに改善すること
ができる。
As described above, according to the present invention, the group
Hydrogen ion is formed on the first semiconductor substrate with an oxide layer formed on the plate surface.
Ion implantation into the first semiconductor substrate by ion implantation.
Forming a damaged region on the surface of the oxide layer.
To another second semiconductor substrate that serves as a supporting substrate
And heat treating the two bonded semiconductor substrates together.
And divide the first semiconductor substrate at the damaged area by
Separated from the second semiconductor substrate and bonded to the second semiconductor substrate
Immediately after this separation or after this single crystal
The second semiconductor substrate having the thin film is heat treated to obtain the single crystal thin film.
Immediately after the strong chemical bonding film, a semiconductor substrate having an upper SL single crystal thin film in an active atmosphere 1000 to 1300 ° C.
By performing the heat treatment at the temperature of 10 minutes to 5 hours, even an extremely thin thin film having a thickness of several hundreds nm or less, without changing the thickness of the thin film and without increasing the in-plane thickness variation, The average surface roughness of the thin film can be improved to the order of 0.1 nm.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施の形態のSOI基板の製造方法を
工程順に示す図。
FIG. 1 is a diagram showing a method of manufacturing an SOI substrate according to an embodiment of the present invention in the order of steps.

【図2】本発明実施例1の活性雰囲気で熱処理する前の
原子間力顕微鏡により基板表面粗さを示す図。
FIG. 2 is a diagram showing substrate surface roughness by an atomic force microscope before heat treatment in an active atmosphere of Example 1 of the present invention.

【図3】本発明実施例1の活性雰囲気で熱処理した後の
原子間力顕微鏡により基板表面粗さを示す図。
FIG. 3 is a diagram showing substrate surface roughness by an atomic force microscope after heat treatment in an active atmosphere of Example 1 of the present invention.

【図4】本発明実施例2の活性雰囲気で熱処理した後の
原子間力顕微鏡により基板表面粗さを示す図。
FIG. 4 is a diagram showing substrate surface roughness by an atomic force microscope after heat treatment in an active atmosphere of Example 2 of the present invention.

【符号の説明】[Explanation of symbols]

11 第1半導体基板(第1シリコンウェーハ) 11a 酸化層 12 第2半導体基板(第2シリコンウェーハ) 13 シリコン薄膜 11 First semiconductor substrate (first silicon wafer) 11a oxide layer 12 Second semiconductor substrate (second silicon wafer) 13 Silicon thin film

フロントページの続き (56)参考文献 特開 平5−217821(JP,A) 特開 平8−264552(JP,A) 特開 平9−162090(JP,A) 特開 平7−235534(JP,A) 特開 平10−275905(JP,A) M.Bruel,Silicon o n insulator materi al technology,Elec tronics Letters,1995 年 7月 6日,Vol.31,No14, PP.1201−1202 (58)調査した分野(Int.Cl.7,DB名) H01L 21/02 H01L 21/322 H01L 21/324 H01L 21/76 H01L 27/12 Continuation of the front page (56) Reference JP-A-5-217821 (JP, A) JP-A-8-264552 (JP, A) JP-A-9-162090 (JP, A) JP-A-7-235534 (JP , A) JP 10-275905 (JP, A) M.S. Bruel, Silicon on insulator material technology, Electronics Letters, July 6, 1995, Vol. 31, No 14, PP. 1201-1202 (58) Fields surveyed (Int.Cl. 7 , DB name) H01L 21/02 H01L 21/322 H01L 21/324 H01L 21/76 H01L 27/12

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 基板表面に酸化層 (11a) が形成された第
1半導体基板 (11) に水素イオンを注入して前記第1半導
体基板 (11) 内部にイオン注入による損傷領域 (11b) を形
成し、前記半導体基板 (11) を前記酸化層 (11a) の表面を
接合面として支持基板となる別の第2半導体基板 (12)
接合し、前記接合した2枚の半導体基板 (11,12) を熱処
理することにより前記第1半導体基板 (11) を前記損傷領
(11b) のところで割って前記第2半導体基板 (12) から
分離して前記第2半導体基板 (12) の接合面に単結晶薄膜
(13) を残存させ、前記分離直後又は前記単結晶薄膜 (13)
を有する第2半導体基板 (12) を熱処理して前記単結晶薄
(13) の化学結合を強固にした直後に前記単結晶薄膜 (1
3) を有する第2半導体基板(12)を活性雰囲気中で100
0〜1300℃の温度で10分〜5時間熱処理すること
により前記薄膜の平均表面粗さを0.1nmオーダーに
することを特徴とするSOI基板の製造方法。
1. A first substrate having an oxide layer (11a) formed on a substrate surface .
1 Injecting hydrogen ions into the semiconductor substrate (11) , the first semiconductor
Body substrate (11) form a damaged region (11b) by ion implantation in the interior
To form the semiconductor substrate (11) on the surface of the oxide layer (11a) .
On another second semiconductor substrate (12) which becomes a supporting substrate as a bonding surface
The two bonded semiconductor substrates (11, 12) are heat treated.
The first semiconductor substrate (11) is damaged by
From pass the divided at the (11b) second semiconductor substrate (12)
Separately , a single crystal thin film is formed on the bonding surface of the second semiconductor substrate (12).
(13) is left, immediately after the separation or the single crystal thin film (13)
The second semiconductor substrate (12) having
Immediately after strengthening the chemical bond of the film (13), the single crystal thin film (1
The second semiconductor substrate (12) having ( 3) is heated to 100 in an active atmosphere.
Heat treatment at a temperature of 0 to 1300 ° C. for 10 minutes to 5 hours
The average surface roughness of the thin film to the order of 0.1 nm
A method of manufacturing an SOI substrate, comprising :
【請求項2】 薄膜(13)がシリコン薄膜であって、活性
雰囲気が水素雰囲気であって、熱処理温度が1000〜
1300℃である請求項1記載のSOI基板の製造
法。
2. The thin film (13) is a silicon thin film, the active atmosphere is a hydrogen atmosphere, and the heat treatment temperature is from 1000 to 1000.
The method for manufacturing an SOI substrate according to claim 1, wherein the method is at 1300 ° C.
JP03884897A 1997-02-24 1997-02-24 Method for manufacturing SOI substrate Expired - Fee Related JP3522482B2 (en)

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Publication number Priority date Publication date Assignee Title
JP3754818B2 (en) * 1997-03-27 2006-03-15 キヤノン株式会社 Method for manufacturing semiconductor substrate
US6271101B1 (en) * 1998-07-29 2001-08-07 Semiconductor Energy Laboratory Co., Ltd. Process for production of SOI substrate and process for production of semiconductor device
US6287941B1 (en) * 1999-04-21 2001-09-11 Silicon Genesis Corporation Surface finishing of SOI substrates using an EPI process
FR2797713B1 (en) 1999-08-20 2002-08-02 Soitec Silicon On Insulator PROCESS FOR PROCESSING SUBSTRATES FOR MICROELECTRONICS AND SUBSTRATES OBTAINED BY THIS PROCESS
US6489241B1 (en) * 1999-09-17 2002-12-03 Applied Materials, Inc. Apparatus and method for surface finishing a silicon film
KR100730806B1 (en) 1999-10-14 2007-06-20 신에쯔 한도타이 가부시키가이샤 Method for manufacturing soi wafer, and soi wafer
FR2827423B1 (en) * 2001-07-16 2005-05-20 Soitec Silicon On Insulator METHOD OF IMPROVING SURFACE CONDITION
US6884696B2 (en) 2001-07-17 2005-04-26 Shin-Etsu Handotai Co., Ltd. Method for producing bonding wafer
JP4407127B2 (en) * 2003-01-10 2010-02-03 信越半導体株式会社 Manufacturing method of SOI wafer
JP5231449B2 (en) * 2006-12-28 2013-07-10 エムイーエムシー・エレクトロニック・マテリアルズ・インコーポレイテッド Method for producing a smooth wafer
KR100857386B1 (en) 2006-12-29 2008-09-05 주식회사 실트론 Method for thermal process of SOI wafer
WO2009084312A1 (en) * 2007-12-27 2009-07-09 Sharp Kabushiki Kaisha Semiconductor device, substrate with single-crystal semiconductor thin film and methods for manufacturing same
JP5493345B2 (en) 2008-12-11 2014-05-14 信越半導体株式会社 Manufacturing method of SOI wafer

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M.Bruel,Silicon on insulator material technology,Electronics Letters,1995年 7月 6日,Vol.31,No14,PP.1201−1202

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