JP3412449B2 - Method for manufacturing SOI substrate - Google Patents

Method for manufacturing SOI substrate

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Publication number
JP3412449B2
JP3412449B2 JP13903197A JP13903197A JP3412449B2 JP 3412449 B2 JP3412449 B2 JP 3412449B2 JP 13903197 A JP13903197 A JP 13903197A JP 13903197 A JP13903197 A JP 13903197A JP 3412449 B2 JP3412449 B2 JP 3412449B2
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JP
Japan
Prior art keywords
thin film
substrate
semiconductor substrate
temperature
laminated body
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP13903197A
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Japanese (ja)
Other versions
JPH10335616A (en
Inventor
涼子 高田
和成 高石
憲治 富澤
Original Assignee
三菱住友シリコン株式会社
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Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、単結晶の薄膜を支
持基板上に有するSOI基板の製造方法に関するもので
ある。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an SOI substrate having a single crystal thin film on a supporting substrate.

【0002】[0002]

【従来の技術】この種のSOI基板は将来の超高集積回
路(ULSI)基板として注目されてきている。このS
OI基板の製造方法には、シリコン基板同士を絶縁膜
を介して貼り合わせる方法、絶縁性基板又は絶縁性薄
膜を表面に有する基板の上にシリコン薄膜を堆積させる
方法、シリコン基板の内部に高濃度の酸素イオンを注
入した後、高温でアニール処理してこのシリコン基板表
面から所定の深さの領域に埋込みシリコン酸化層を形成
し、その表面側のSi層を活性領域とするSIMOX法
などがある。
2. Description of the Related Art This type of SOI substrate has been drawing attention as a future ultra high integrated circuit (ULSI) substrate. This S
The method of manufacturing an OI substrate includes a method of bonding silicon substrates to each other via an insulating film, a method of depositing a silicon thin film on an insulating substrate or a substrate having an insulating thin film on its surface, and a high concentration inside a silicon substrate. After the implantation of oxygen ions, an annealing process is performed at a high temperature to form a buried silicon oxide layer in a region of a predetermined depth from the surface of the silicon substrate, and a SIMOX method using the Si layer on the surface side as an active region is available. .

【0003】また最近、半導体基板に水素イオン注入を
行った後に、この半導体基板をイオン注入面を重ね合せ
面として支持基板に重ね合せ、この積層体を500℃を
越える温度に昇温して上記半導体基板を水素イオン注入
部分で支持基板から分離し、支持基板の表面に薄膜を有
する薄い半導体材料フィルムの製造方法が提案されてい
る(特開平5−211128)。この方法では、イオン
を半導体基板の内部に表面から均一に注入できれば、均
一な厚さの薄膜を有する半導体基板が得られる。また支
持基板の表面に予め酸化層を設けておけば、この方法に
よりSOI基板を製造することができる。なお、半導体
基板を水素イオン注入部分で支持基板から分離するとき
の雰囲気は、通常大気圧と同一の窒素雰囲気中で行われ
る。
In addition, recently, after hydrogen ion implantation has been performed on a semiconductor substrate, this semiconductor substrate is superposed on a supporting substrate with the ion implantation surface as a superimposing surface, and this laminated body is heated to a temperature exceeding 500 ° C. A method of manufacturing a thin semiconductor material film having a thin film on the surface of the supporting substrate by separating the semiconductor substrate from the supporting substrate at the hydrogen ion-implanted portion has been proposed (JP-A-5-211128). In this method, if the ions can be uniformly injected into the inside of the semiconductor substrate from the surface, a semiconductor substrate having a thin film having a uniform thickness can be obtained. If an oxide layer is provided on the surface of the supporting substrate in advance, the SOI substrate can be manufactured by this method. The atmosphere for separating the semiconductor substrate from the supporting substrate at the hydrogen ion-implanted portion is usually the same nitrogen atmosphere as the atmospheric pressure.

【0004】一方、近年マイクロエレクトロニクスデバ
イスの高集積化、デバイス最小寸法の縮小に伴い、ウェ
ーハ表面の清浄度とともにウェーハ表面の微視的ラフネ
ス、即ちマイクロラフネス(micro-roughness)が重要
視されてきている。特にマイクロラフネスはデバイスの
酸化膜耐圧などの電気特性に大きな影響を与えることが
認識されている((M.Morita, et al.,"Effect of Si wa
fer surface micro-roughness on electrical properti
es of very-thin gate oxide films", ULSI Science an
d Technology/1991,pp.400-408, Electrochem, Society
(1991))。なお、ここでマイクロラフネスは1μm以
下数nmのオーダの表面粗さをいう。
On the other hand, in recent years, with the high integration of microelectronic devices and the reduction of the minimum device size, the cleanliness of the wafer surface and the micro-roughness of the wafer surface, that is, the micro-roughness, have been emphasized. There is. In particular, it is recognized that microroughness has a great influence on the electrical characteristics such as the breakdown voltage of the oxide film of the device ((M. Morita, et al., "Effect of Si Wa
fer surface micro-roughness on electrical properti
es of very-thin gate oxide films ", ULSI Science an
d Technology / 1991, pp.400-408, Electrochem, Society
(1991)). Here, the microroughness means a surface roughness on the order of 1 μm or less and several nm.

【0005】上記特開平5−211128号公報に示さ
れた方法で半導体基板を分離した直後の支持基板の表面
に存する薄膜の表面の平均粗さは、分離前の半導体基板
表面の平均粗さの10倍以上であり、マイクロラフネス
が比較的大きく、上述した酸化膜耐圧などの電気特性に
悪影響を及ぼすおそれがある。特にこの方法では、半導
体基板の分離により形成された薄膜の表面は、熱処理に
伴う微小気泡の形状が残っているためにマイクロラフネ
スが大きく、デバイスの作製には適さない。
The average roughness of the surface of the thin film existing on the surface of the supporting substrate immediately after the semiconductor substrate is separated by the method disclosed in the above-mentioned Japanese Patent Laid-Open No. 511128/1 is the average roughness of the surface of the semiconductor substrate before separation. It is 10 times or more, the microroughness is relatively large, and there is a possibility that the electrical characteristics such as the oxide film withstand voltage described above are adversely affected. In particular, in this method, the surface of the thin film formed by separating the semiconductor substrate has a large microroughness because the shape of the fine bubbles due to the heat treatment remains, and is not suitable for device fabrication.

【0006】この点を解決するため、半導体基板を分離
した後の支持基板上の薄膜表面をタッチポリッシュ(to
uch polishing)と呼ばれる、軽い研磨を施すことによ
り、この薄膜の表面を平坦化している(M.Bruel et a
l.,"A Promising New SOI Material Technology" IEEE
International SOI Conference proceedings,pp.178-17
9 (1995))。
In order to solve this problem, the thin film surface on the supporting substrate after the semiconductor substrate is separated is touch-polished (to
The surface of this thin film is planarized by performing a light polishing called uch polishing (M.Bruel et a
l., "A Promising New SOI Material Technology" IEEE
International SOI Conference proceedings, pp.178-17
9 (1995)).

【0007】[0007]

【発明が解決しようとする課題】しかしながら、現状の
タッチポリッシュの技術を、上記方法で作製した厚さ数
百nm以下の極めて薄い薄膜に適用した場合には、薄膜
表面を平坦化することはできるが、面内で研磨量のばら
つきがあるため、薄膜の厚さ分布が大きくなる不具合が
あった。この薄膜の厚さ分布が大きいため、研磨後の薄
膜半導体基板を用いてデバイスを作製した場合に、デバ
イスの特性がばらつく問題点があった。
However, when the current touch polishing technique is applied to an extremely thin thin film having a thickness of several hundreds nm or less produced by the above method, the thin film surface can be flattened. However, there is a problem that the thickness distribution of the thin film becomes large due to the variation in the polishing amount within the surface. Since the thickness distribution of this thin film is large, there is a problem that the device characteristics vary when the device is manufactured using the thin film semiconductor substrate after polishing.

【0008】本発明の目的は、薄膜表面のタッチポリッ
シュによる研磨を極力低減若しくは不要にでき、しかも
厚さが極めて薄い薄膜であっても、膜厚が均一で表面粗
さが良好な薄膜を得ることができるSOI基板の製造方
法を提供することにある。本発明の別の目的は、薄膜表
面の平坦化と薄膜の支持基板への貼合せを同時に行うこ
とにより製造工程の負荷を低減できるSOI基板の製造
方法を提供することにある。
The object of the present invention is to obtain a thin film which can minimize or eliminate the polishing of the surface of the thin film by touch polishing as much as possible, and has a uniform film thickness and a good surface roughness even if the film is extremely thin. It is to provide a manufacturing method of an SOI substrate that can be manufactured. Another object of the present invention is to provide a method for manufacturing an SOI substrate which can reduce the load of the manufacturing process by simultaneously flattening the surface of the thin film and bonding the thin film to a supporting substrate.

【0009】[0009]

【課題を解決するための手段】請求項1に係る発明は、
図1及び図2に示すように、表面に絶縁層11aが形成
された半導体基板11に水素イオンを注入して半導体基
板11内部に絶縁層11aに平行な損傷領域11bを形
成する工程と、半導体基板11を支持基板12に重ね合
せて積層体13を形成する工程と、積層体13を1×1
-6〜1×10-11torrの真空中で400〜500℃の
範囲に昇温して半導体基板11を損傷領域11bで厚肉
部11c及び薄膜11dに分離する工程とを含むSOI
基板の製造方法である。この請求項1に記載されたSO
I基板の製造方法では、半導体基板11が厚肉部11c
と薄膜11dとに分離されるのは、半導体基板11に注
入した水素イオンを起因とする微小気泡の内圧と半導体
基板11外部の圧力との差が十分に大きくなることによ
り起こると考えられる。この結果、半導体基板11外部
の圧力が小さい方が薄膜11d分離に必要な微小気泡の
内圧が小さくて済むため、1×10-6〜1×10-11tor
rと極めて真空度の高い雰囲気中で加熱すると、微小気
泡の成長が比較的少ない状態で薄膜11dを分離でき
る。従って、薄膜11dの分離面の表面粗さが小さくな
ると考えられる。
The invention according to claim 1 is
As shown in FIGS. 1 and 2, a step of implanting hydrogen ions into a semiconductor substrate 11 having an insulating layer 11a formed on its surface to form a damaged region 11b parallel to the insulating layer 11a inside the semiconductor substrate 11, and The step of stacking the substrate 11 on the support substrate 12 to form the laminated body 13 and the laminated body 13 of 1 × 1
SOI including a step of raising the temperature to a range of 400 to 500 ° C. in a vacuum of 0 −6 to 1 × 10 −11 torr and separating the semiconductor substrate 11 into a thick portion 11c and a thin film 11d at a damaged region 11b.
It is a method of manufacturing a substrate. SO described in claim 1
In the method of manufacturing the I substrate, the semiconductor substrate 11 has the thick portion 11c.
It is considered that the separation into the thin film 11d and the thin film 11d is caused by a sufficiently large difference between the internal pressure of the fine bubbles caused by the hydrogen ions implanted in the semiconductor substrate 11 and the pressure outside the semiconductor substrate 11. As a result, the smaller the pressure outside the semiconductor substrate 11 is, the smaller the internal pressure of the fine bubbles necessary for the separation of the thin film 11d is, so that the pressure is 1 × 10 −6 to 1 × 10 −11 tor.
When heated in an atmosphere with a very high degree of vacuum of r, the thin film 11d can be separated in a state in which the growth of fine bubbles is relatively small. Therefore, it is considered that the surface roughness of the separation surface of the thin film 11d becomes small.

【0010】請求項2に係る発明は、請求項1に係る発
明であって、更に図1及び図2に示すように、積層体1
3の温度を所定の温度まで下げて半導体基板11の厚肉
部11cを除去した後に、積層体13を1×10-6〜1
×10-11torrの真空中で900〜1200℃の範囲に
昇温して薄膜11d表面を平坦化しかつ薄膜11dを支
持基板12に貼合せることを特徴とする。この請求項2
に記載されたSOI基板の製造方法では、1×10-6
1×10-11torrと極めて真空度の高い雰囲気中で70
0℃まで昇温すると、半導体基板11に注入された水素
イオンの薄膜11dからの脱離が完了し、これに伴って
薄膜11dの表面粗さが小さくなる。一方、薄膜11d
と支持基板12との貼合せ熱処理は通常900〜120
0℃の範囲で行われる。この結果、上記熱処理は薄膜1
1d表面の平坦化熱処理と薄膜11dの貼合せ熱処理と
を兼ねるので、SOI基板14の製造工数を低減でき
る。
The invention according to claim 2 is the invention according to claim 1, further comprising a laminate 1 as shown in FIGS. 1 and 2.
After lowering the temperature of 3 to a predetermined temperature to remove the thick portion 11c of the semiconductor substrate 11, the laminated body 13 is set to 1 × 10 −6 −1.
It is characterized in that the temperature is raised to a range of 900 to 1200 ° C. in a vacuum of × 10 -11 torr to flatten the surface of the thin film 11d and the thin film 11d is bonded to the support substrate 12. This claim 2
In the method for manufacturing an SOI substrate described in 1), 1 × 10 −6
70 in an extremely high vacuum of 1 × 10 -11 torr
When the temperature is raised to 0 ° C., the desorption of hydrogen ions implanted in the semiconductor substrate 11 from the thin film 11d is completed, and the surface roughness of the thin film 11d is accordingly reduced. On the other hand, the thin film 11d
And the heat treatment for laminating the support substrate 12 are usually 900 to 120.
It is carried out in the range of 0 ° C. As a result, the above heat treatment is applied
Since the heat treatment for flattening the surface of 1d and the heat treatment for laminating the thin film 11d are combined, the number of manufacturing steps of the SOI substrate 14 can be reduced.

【0011】請求項3に係る発明は、請求項1に係る発
明であって、更に損傷領域で分離した厚肉部を薄膜に重
ねたまま積層体を1×10-6〜1×10-11torrの真空
中で900〜1200℃の範囲に更に昇温して、薄膜表
面を平坦化しかつ薄膜を支持基板に貼合せた後に、降温
して厚肉部を除去することを特徴とする。この請求項3
に記載されたSOI基板の製造方法では、半導体基板の
薄膜の分離後に降温せずに、更に900〜1200℃の
範囲まで昇温するので、上記請求項2に係るSOI基板
の製造方法より熱処理の工数及び熱エネルギの損失を低
減できる。
The invention according to claim 3 is the invention according to claim 1, further comprising a laminated body of 1 × 10 −6 to 1 × 10 −11 while the thick portions separated in the damaged region are stacked on the thin film. It is characterized by further increasing the temperature in the range of 900 to 1200 ° C. in a torr vacuum to flatten the surface of the thin film and bonding the thin film to a supporting substrate, and then lowering the temperature to remove the thick portion. This claim 3
In the method of manufacturing an SOI substrate according to claim 1, since the temperature is further raised to a range of 900 to 1200 ° C. without lowering the temperature after the thin film of the semiconductor substrate is separated, the method for manufacturing an SOI substrate according to claim 2 is characterized by heat treatment. The number of steps and the loss of heat energy can be reduced.

【0012】[0012]

【発明の実施の形態】次に本発明の実施の形態を図面に
基づいて説明する。図1及び図2(a)に示すように、
本発明のSOI基板を製造するには、先ずシリコンウェ
ーハからなる半導体基板11を熱酸化により基板11表
面に絶縁層である酸化層11a(SiO2層)を形成し
た後、この基板11に水素イオンを3.5×1016H/
cm2〜1×1017H/cm2のドーズ量でイオン注入す
る(図1(a))。符号11bは水素イオン注入により
半導体基板11内部に形成された損傷領域であり、この
損傷領域11bは酸化層11aに平行に形成される。次
いで上記と同一のシリコンウェーハからなる支持基板1
2を用意し(図1(b))、両基板11,12をRCA
法により洗浄した後、支持基板12上に半導体基板11
を室温で重ね合せて積層体13を形成する(図1
(c))。次に上記積層体13を1×10-6〜1×10
-11torr、好ましくは1×10-7〜1×10-9の真空中
で400〜500℃(図2)、好ましくは400〜45
0℃の範囲に昇温し、この温度範囲に0〜10分間(図
2)、好ましくは1〜2分間保持して薄膜分離熱処理を
行う。これにより半導体基板11が損傷領域11bのと
ころで割れて上部の厚肉部11cと下部の薄膜11dに
分離する(図1(d))。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings. As shown in FIGS. 1 and 2 (a),
In order to manufacture the SOI substrate of the present invention, first, a semiconductor substrate 11 made of a silicon wafer is thermally oxidized to form an oxide layer 11a (SiO 2 layer) which is an insulating layer on the surface of the substrate 11, and then hydrogen ions are added to the substrate 11. 3.5 × 10 16 H /
Ion implantation is performed with a dose amount of cm 2 to 1 × 10 17 H / cm 2 (FIG. 1A). Reference numeral 11b is a damaged region formed inside the semiconductor substrate 11 by hydrogen ion implantation, and the damaged region 11b is formed parallel to the oxide layer 11a. Next, a supporting substrate 1 made of the same silicon wafer as above.
2 is prepared (FIG. 1B), and both substrates 11 and 12 are RCA.
After cleaning by the method, the semiconductor substrate 11 is formed on the supporting substrate 12.
Are laminated at room temperature to form a laminate 13 (see FIG. 1).
(C)). Next, the laminated body 13 is mixed with 1 × 10 −6 to 1 × 10.
-11 torr, preferably 1 × 10 −7 to 1 × 10 −9 in a vacuum of 400 to 500 ° C. (FIG. 2), preferably 400 to 45
The temperature is raised to a range of 0 ° C., and the thin film separation heat treatment is performed by maintaining this temperature range for 0 to 10 minutes (FIG. 2), preferably 1 to 2 minutes. As a result, the semiconductor substrate 11 is cracked at the damaged region 11b and separated into an upper thick portion 11c and a lower thin film 11d (FIG. 1 (d)).

【0013】ここで、上記薄膜分離熱処理の雰囲気を1
×10-6〜1×10-11torrの真空に限定したのは、1
×10-6torr未満では分離面の平坦化が不十分となる不
具合があり、1×10-11torrを越えると装置の設計上
の実現が難しいからである。また上記熱処理の温度を4
00〜500℃に限定したのは、400℃未満では水素
による気泡内圧の上昇が十分でない不具合があり、50
0℃を越えると気泡の成長が進んで表面粗さが増大する
不具合があるからである。
Here, the atmosphere for the thin film separation heat treatment is set to 1
The limit of the vacuum of × 10 -6 to 1 × 10 -11 torr is 1
This is because if it is less than × 10 -6 torr, the flattening of the separation surface becomes insufficient, and if it exceeds 1 × 10 -11 torr, it is difficult to realize the design of the device. In addition, the temperature of the heat treatment is 4
The reason why the temperature is limited to 00 to 500 ° C. is that if the temperature is lower than 400 ° C., the internal pressure of bubbles is not sufficiently increased by hydrogen.
This is because if the temperature exceeds 0 ° C., the growth of bubbles proceeds and the surface roughness increases.

【0014】更に上記半導体基板11が損傷領域11b
で割れた積層体13の温度を200〜300℃まで下げ
て半導体基板11の厚肉部11cを除去し、支持基板1
2の上面に単結晶シリコンの薄膜11dを積層した状態
で(図1(e))、1×10-6〜1×10-11torr、好
ましくは1×10-7〜1×10-9torrの真空中で900
〜1200℃(図2(a))、好ましくは1000〜1
100℃の範囲に昇温しこの温度範囲に30〜120分
間、好ましくは40〜60分間保持する熱処理を行う。
この熱処理は薄膜11d表面の平坦化熱処理と薄膜11
dの支持基板12への貼合せ熱処理とを兼ねる熱処理で
ある。
Further, the semiconductor substrate 11 has a damaged region 11b.
The temperature of the laminated body 13 cracked in step 2 is lowered to 200 to 300 ° C. to remove the thick portion 11c of the semiconductor substrate 11, and the supporting substrate 1
In the state where the thin film 11d of single crystal silicon is laminated on the upper surface of 2 (FIG. 1 (e)), 1 × 10 −6 to 1 × 10 −11 torr, preferably 1 × 10 −7 to 1 × 10 −9 torr. In the vacuum of 900
~ 1200 ° C (Fig. 2 (a)), preferably 1000-1
A heat treatment is performed by raising the temperature to a range of 100 ° C. and maintaining this temperature range for 30 to 120 minutes, preferably 40 to 60 minutes.
This heat treatment includes the heat treatment for flattening the surface of the thin film 11d and the thin film 11d.
This is a heat treatment that also serves as a heat treatment for laminating d on the support substrate 12.

【0015】即ち、1×10-6〜1×10-11torrと極
めて真空度の高い雰囲気中で700℃まで昇温すると、
半導体基板11に注入された水素イオンの薄膜11dか
らの脱離が完了し、これに伴って薄膜11dの表面粗さ
が小さくなる。これは昇温脱離ガス分析装置(TDS)
を用いて測定して判明した。一方、薄膜11dと支持基
板12との貼合せ熱処理は通常900〜1200℃の範
囲で行われる。この結果、上記真空中で900〜120
0℃の範囲に昇温することにより、薄膜11d表面を平
坦化し、同時に薄膜11dを支持基板12に貼合せるこ
とができるので、SOI基板14の製造工数を低減でき
る。また上記平坦化熱処理及び貼合せ熱処理を行う前に
積層体13の温度を200〜300℃まで下げて厚肉部
11cを除去したのは、枚葉処理ではなく、バッチ処理
により生産したときに、その生産効率を向上するためで
ある。
That is, when the temperature is raised to 700 ° C. in an atmosphere having a very high degree of vacuum of 1 × 10 -6 to 1 × 10 -11 torr,
The desorption of hydrogen ions implanted in the semiconductor substrate 11 from the thin film 11d is completed, and the surface roughness of the thin film 11d is accordingly reduced. This is a thermal desorption gas analyzer (TDS)
It was found by measuring with. On the other hand, the heat treatment for laminating the thin film 11d and the supporting substrate 12 is usually performed in the range of 900 to 1200 ° C. As a result, in the above vacuum, 900 to 120
By raising the temperature in the range of 0 ° C., the surface of the thin film 11d can be flattened, and at the same time, the thin film 11d can be bonded to the supporting substrate 12, so that the manufacturing steps of the SOI substrate 14 can be reduced. Further, the temperature of the laminated body 13 is reduced to 200 to 300 ° C. to remove the thick portion 11c before the flattening heat treatment and the bonding heat treatment are performed. This is to improve its production efficiency.

【0016】なお、上記実施の形態では、半導体基板の
表面に熱酸化により絶縁層である酸化層(SiO2層)
を形成したが、半導体基板の表面に窒化処理等により絶
縁層を形成してもよい。また、上記実施の形態では、積
層体の温度を所定の温度まで下げて半導体基板の厚肉部
を除去した後に、積層体を1×10-6〜1×10-11tor
rの真空中で900〜1200℃の範囲に昇温して、薄
膜表面を平坦化しかつ薄膜を支持基板に貼合せたが、こ
れに限らず、損傷領域で分離した厚肉部を薄膜に重ねた
まま積層体を1×10-6〜1×10-11torr、好ましく
は1×10-7〜1×10-9torrの真空中で900〜12
00℃(図2(b))、好ましくは1000〜1100
℃の範囲に更に昇温してこの温度範囲に30〜120分
間、好ましくは40〜60分間保持することにより、薄
膜表面を平坦化しかつ薄膜を支持基板に貼合せ、その後
に降温して厚肉部を除去してもよい。この場合、半導体
基板の薄膜の分離後に降温せずに、更に900〜120
0℃の範囲まで昇温するので、上記実施の形態に係るS
OI基板の製造方法より熱処理の工数及び熱エネルギの
損失を低減できる。
In the above embodiment, an oxide layer (SiO 2 layer), which is an insulating layer, is formed on the surface of the semiconductor substrate by thermal oxidation.
However, an insulating layer may be formed on the surface of the semiconductor substrate by nitriding treatment or the like. Further, in the above embodiment, the temperature of the laminated body is lowered to a predetermined temperature to remove the thick portion of the semiconductor substrate, and then the laminated body is subjected to 1 × 10 −6 to 1 × 10 −11 tor.
In a vacuum of r, the temperature was raised to a range of 900 to 1200 ° C. to flatten the surface of the thin film and the thin film was attached to a supporting substrate. 900 to 12 in a vacuum of 1 × 10 −6 to 1 × 10 −11 torr, preferably 1 × 10 −7 to 1 × 10 −9 torr.
00 ° C. (FIG. 2 (b)), preferably 1000 to 1100
By further raising the temperature to a range of ℃ and holding this temperature range for 30 to 120 minutes, preferably 40 to 60 minutes, the thin film surface is flattened and the thin film is attached to a supporting substrate, and then the temperature is lowered to obtain a thick wall. Parts may be removed. In this case, after the thin film of the semiconductor substrate is separated, the temperature is further lowered to 900 to 120 without lowering the temperature.
Since the temperature is raised to the range of 0 ° C., S according to the above-described embodiment
The number of heat treatment steps and the loss of heat energy can be reduced as compared with the OI substrate manufacturing method.

【0017】[0017]

【実施例】次に本発明の実施例を図面に基づいて詳しく
説明する。 <実施例1>厚さ625μmのシリコンウェーハからな
る半導体基板を熱酸化して表面に厚さ400nmの熱酸
化膜を形成した。この半導体基板に100keV、ドー
ズ量5×1016H/cm2で水素イオンを注入した。熱
酸化前の上記と同一のシリコンウェーハからなる支持基
板に上記半導体基板を重ね合せて積層体を形成した。重
ね合せる前にRCA法により両基板を洗浄した。この積
層体を1×10-8torrの真空中で400℃まで昇温して
薄膜分離の熱処理を行った(図3(a))。この熱処理
により半導体基板中の結晶の再配列及び微小気泡の圧力
作用にて、半導体基板内部のイオン注入した箇所で半導
体基板が割れて分離し、支持基板上に厚さ120nmの
単結晶シリコンの薄膜を有するSOI基板が得られた。
このときの薄膜の厚さのばらつきは±4nmであった。
また薄膜表面の平均粗さRaを、測定領域を10μm角
及び2μm角として、原子間力顕微鏡(以下、AFMと
いう)によりそれぞれ測定した。この結果、測定領域が
10μm角及び2μm角のときの薄膜表面の平均粗さR
aはそれぞれ6.26nm(図4(a))及び5.11n
m(図4(b))であった。
Embodiments of the present invention will now be described in detail with reference to the drawings. Example 1 A semiconductor substrate made of a silicon wafer having a thickness of 625 μm was thermally oxidized to form a thermal oxide film having a thickness of 400 nm on the surface. Hydrogen ions were implanted into this semiconductor substrate at 100 keV and a dose of 5 × 10 16 H / cm 2 . The semiconductor substrate was superposed on a supporting substrate made of the same silicon wafer as the above before thermal oxidation to form a laminated body. Both substrates were cleaned by the RCA method before stacking. This laminated body was heated to 400 ° C. in a vacuum of 1 × 10 −8 torr and subjected to heat treatment for thin film separation (FIG. 3A). Due to the rearrangement of crystals in the semiconductor substrate and the pressure action of the minute bubbles by this heat treatment, the semiconductor substrate is broken and separated at the ion-implanted portion inside the semiconductor substrate, and a thin film of single-crystal silicon having a thickness of 120 nm is formed on the supporting substrate. An SOI substrate having
The variation in the thickness of the thin film at this time was ± 4 nm.
Further, the average roughness Ra of the thin film surface was measured with an atomic force microscope (hereinafter referred to as AFM), with the measurement regions being 10 μm square and 2 μm square. As a result, the average roughness R of the thin film surface when the measurement area is 10 μm square and 2 μm square
a is 6.26 nm (FIG. 4 (a)) and 5.11 n, respectively.
m (FIG. 4 (b)).

【0018】<実施例2>実施例1と同様にして作製し
た単結晶シリコンの薄膜付きの支持基板を厚肉部薄膜上
に重ねたまま、実施例1と同一の真空中、即ち1×10
-8torrの真空中で850℃まで昇温して、薄膜の平坦化
熱処理を行った(図3(b))。このときの薄膜の厚さ
は120±4nmと実施例1と殆ど変らなかった。また
測定領域が10μm角及び2μm角のときの薄膜表面の
平均粗さRaはAFMで測定した結果、それぞれ1.1
6nm(図5(a))及び0.38nm(図5(b))であっ
た。この結果、薄膜表面の平均粗さRaは実施例1の約
1/5(測定領域10μm角)及び約1/13(測定領
域2μm角)となり、実施例1と比べて極めて小さくな
った。
<Embodiment 2> In the same vacuum as in Embodiment 1, that is, in the same vacuum as in Embodiment 1, ie, 1 × 10 4, the supporting substrate with a thin film of single crystal silicon produced in the same manner as in Embodiment 1 is stacked on the thin film of the thick portion.
The thin film was heated to 850 ° C. in a vacuum of −8 torr to perform flattening heat treatment on the thin film (FIG. 3B). The thickness of the thin film at this time was 120 ± 4 nm, which was almost the same as in Example 1. The average roughness Ra of the thin film surface when the measurement area is 10 μm square and 2 μm square is 1.1 as a result of measurement by AFM.
It was 6 nm (FIG. 5 (a)) and 0.38 nm (FIG. 5 (b)). As a result, the average roughness Ra of the thin film surface was about ⅕ (measurement area 10 μm square) and about 1/13 (measurement area 2 μm square) of Example 1, which was extremely smaller than that of Example 1.

【0019】<比較例1>実施例1と同様にして作製し
た半導体基板及び支持基板の積層体を大気圧の窒素雰囲
気中で450℃まで昇温して薄膜分離熱処理を行った。
この熱処理により半導体基板内部のイオン注入した箇所
で半導体基板が割れて分離し、支持基板上に厚さ120
nmの単結晶シリコンの薄膜を有するSOI基板が得ら
れた。このときの薄膜の厚さは120±4nmと実施例
1と殆ど変らなかった。また測定領域が10μm角及び
2μm角のときの薄膜表面の平均粗さRaはAFMで測
定した結果、それぞれ12.7nm(図6(a))及び1
0.3nm(図6(b))であった。この結果、薄膜表面
の平均粗さRaは、測定領域が10μm角及び2μm角
のいずれの場合にも、実施例1の約2倍と大きくなっ
た。
<Comparative Example 1> A laminated body of a semiconductor substrate and a supporting substrate manufactured in the same manner as in Example 1 was heated to 450 ° C. in a nitrogen atmosphere at atmospheric pressure and subjected to thin film separation heat treatment.
By this heat treatment, the semiconductor substrate is cracked and separated at the ion-implanted portion inside the semiconductor substrate, and the thickness of the semiconductor substrate is 120
An SOI substrate having a thin film of single crystal silicon of nm was obtained. The thickness of the thin film at this time was 120 ± 4 nm, which was almost the same as in Example 1. The average roughness Ra of the thin film surface when the measurement region is 10 μm square and 2 μm square is 12.7 nm (FIG. 6 (a)) and 1 respectively as a result of measurement by AFM.
It was 0.3 nm (FIG. 6 (b)). As a result, the average roughness Ra of the thin film surface was about twice as large as that in Example 1 in both cases where the measurement area was 10 μm square and 2 μm square.

【0020】<比較例2>比較例1と同様にして作製し
た単結晶シリコンの薄膜付きの支持基板を厚肉部薄膜上
に重ねたまま大気圧の窒素雰囲気中で更に昇温して10
00℃に60分間保持し、薄膜の支持基板への貼合せ熱
処理を行った。このときの薄膜の厚さは120±4nm
と実施例2と殆ど変らなかった。また測定領域が10μ
m角及び2μm角のときの薄膜表面の平均粗さRaはA
FMで測定した結果、それぞれ10.2nm(図7
(a))及び9.69nm(図7(b))であった。この結
果、薄膜表面の平均粗さRaは比較例1より僅かに改善
されたが、実施例2のそれぞれ約9倍(測定領域10μ
m角)及び約25倍(測定領域2μm角)となり、実施
例2と比べて極めて大きくなった。
<Comparative Example 2> A supporting substrate with a thin film of single crystal silicon produced in the same manner as in Comparative Example 1 was further heated in a nitrogen atmosphere at atmospheric pressure while being stacked on the thin film of the thick portion,
The film was held at 00 ° C. for 60 minutes, and heat treatment for laminating the thin film on the supporting substrate was performed. The thickness of the thin film at this time is 120 ± 4 nm
There was almost no difference from Example 2. The measurement area is 10μ
The average roughness Ra of the thin film surface at m-square and 2 μm-square is A
As a result of measurement by FM, each is 10.2 nm (Fig. 7).
(a)) and 9.69 nm (FIG. 7 (b)). As a result, the average roughness Ra of the thin film surface was slightly improved as compared with Comparative Example 1, but was about 9 times that of Example 2 (measurement area 10 μm).
m square) and about 25 times (measurement area 2 μm square), which is much larger than that in Example 2.

【0021】[0021]

【発明の効果】以上述べたように、本発明によれば、表
面に絶縁層が形成された半導体基板に水素イオンを注入
して半導体基板内部に絶縁層に平行な損傷領域を形成
し、半導体基板を支持基板に重ね合せて積層体を形成
し、更に積層体を1×10-6〜1×10-11torrの真空
中で400〜500℃の範囲に昇温して半導体基板を損
傷領域で厚肉部及び薄膜に分離したので、表面粗さが良
好な薄膜を得ることができる。これは半導体基板外部の
圧力を小さくできれば、薄膜分離に必要な水素イオンの
微小気泡の内圧が小さて済むので、微小気泡の成長が比
較的少ない状態で薄膜を分離でき、この結果、薄膜の分
離面の表面粗さを小さくできるためである。またタッチ
ポリッシュにより薄膜表面を研磨する必要が極めて少な
いので、厚さが極めて薄い薄膜であっても薄膜の厚さ分
布が大きくなることはなく、本発明のSOI基板を用い
てデバイスを作製しても、デバイスの特性はばらつかな
い。
As described above, according to the present invention, hydrogen ions are implanted into a semiconductor substrate having an insulating layer formed on the surface thereof to form a damaged region parallel to the insulating layer inside the semiconductor substrate. The substrate is superposed on the support substrate to form a laminated body, and the laminated body is further heated to a range of 400 to 500 ° C. in a vacuum of 1 × 10 −6 to 1 × 10 −11 torr to damage the semiconductor substrate. Since it is separated into a thick portion and a thin film by, it is possible to obtain a thin film having a good surface roughness. This is because if the pressure outside the semiconductor substrate can be made small, the internal pressure of the hydrogen ion microbubbles required for thin film separation can be small, so that the thin film can be separated with relatively little growth of the microbubbles. This is because the surface roughness of the surface can be reduced. Further, since it is extremely unnecessary to polish the surface of the thin film by touch polishing, the thickness distribution of the thin film does not increase even if the thin film is extremely thin, and a device is manufactured using the SOI substrate of the present invention. However, the device characteristics do not vary.

【0022】また積層体の温度を所定の温度まで下げて
半導体基板の厚肉部を除去した後に、積層体を1×10
-6〜1×10-11torrの真空中で900〜1200℃の
範囲に昇温する熱処理を行えば、薄膜表面の平坦化と薄
膜の支持基板への貼合せを同時に行うことができるの
で、SOI基板の製造工程への負荷を低減できる。これ
は極めて真空度の高い雰囲気中で700℃まで昇温する
と、半導体基板に注入された水素イオンの薄膜からの脱
離が完了して薄膜の表面粗さが小さくなり、薄膜と支持
基板との貼合せ熱処理は通常900〜1200℃の範囲
で行われるためである。更に損傷領域で分離した厚肉部
を薄膜に重ねたまま積層体を1×10-6〜1×10-11t
orrの真空中で900〜1200℃の範囲に更に昇温し
て、薄膜表面を平坦化しかつ薄膜を支持基板に貼合せた
後に、降温して厚肉部を除去すれば、薄膜分離熱処理後
に一旦降温する上記SOI基板の製造方法より熱処理の
工数及び熱エネルギの損失を低減できる。
After the temperature of the laminated body is lowered to a predetermined temperature to remove the thick portion of the semiconductor substrate, the laminated body is subjected to 1 × 10.
By performing a heat treatment in the range of 900 to 1200 ° C. in a vacuum of −6 to 1 × 10 −11 torr, the thin film surface can be flattened and the thin film can be bonded to the supporting substrate at the same time. The load on the manufacturing process of the SOI substrate can be reduced. This is because when the temperature is raised to 700 ° C. in an atmosphere with a very high degree of vacuum, desorption of hydrogen ions implanted in the semiconductor substrate from the thin film is completed and the surface roughness of the thin film becomes small, so that the thin film and the supporting substrate are separated from each other. This is because the heat treatment for laminating is usually performed in the range of 900 to 1200 ° C. Further, the laminated body is 1 × 10 −6 to 1 × 10 −11 t with the thick portion separated in the damaged region being stacked on the thin film.
After further raising the temperature in the range of 900 to 1200 ° C. in the vacuum of orr to flatten the thin film surface and bonding the thin film to the supporting substrate, the temperature is lowered to remove the thick portion, and once the thin film separation heat treatment is performed. The number of man-hours of heat treatment and loss of heat energy can be reduced as compared with the method of manufacturing an SOI substrate in which the temperature is lowered.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明実施形態のSOI基板の製造方法を工程
順に示す図。
FIG. 1 is a diagram showing a method of manufacturing an SOI substrate according to an embodiment of the present invention in process order.

【図2】(a)はそのSOI基板の熱処理温度条件を示す
図。(b)は別の実施形態のSOI基板の熱処理温度条件
を示す図。
FIG. 2A is a diagram showing heat treatment temperature conditions of the SOI substrate. (b) The figure which shows the heat processing temperature condition of the SOI substrate of another embodiment.

【図3】(a)は本発明の実施例1のSOI基板の熱処理
温度条件を示す図。(b)は本発明の実施例2のSOI基
板の熱処理温度条件を示す図。
FIG. 3A is a diagram showing heat treatment temperature conditions for the SOI substrate of Example 1 of the present invention. FIG. 6B is a diagram showing heat treatment temperature conditions for the SOI substrate of Example 2 of the present invention.

【図4】(a)は本発明の実施例1を示し、400℃に加
熱して半導体基板を損傷領域で分離した直後の薄膜表面
を、AFMにより測定領域を10μm角として示す図。
(b)は本発明の実施例1を示し、400℃に加熱して半
導体基板を損傷領域で分離した直後の薄膜表面を、AF
Mにより測定領域を2μm角として示す図。
FIG. 4A is a diagram showing Example 1 of the present invention, in which the thin film surface immediately after being heated to 400 ° C. to separate the semiconductor substrate in the damaged region shows a measurement region of 10 μm square by AFM.
(b) shows Example 1 of the present invention, in which the thin film surface immediately after the semiconductor substrate was separated at the damaged region by heating to 400 ° C.
The figure which shows the measurement area | region as 2 micrometers square by M.

【図5】(a)は本発明の実施例2を示し、400℃に加
熱して半導体基板を損傷領域で分離し更に850℃まで
加熱した直後の薄膜表面を、AFMにより測定領域を1
0μm角として示す図。(b)は本発明の実施例2を示
し、400℃に加熱して半導体基板を損傷領域で分離し
更に850℃まで加熱した直後の薄膜表面を、AFMに
より測定領域を2μm角として示す図。
FIG. 5 (a) shows Example 2 of the present invention, in which the thin film surface immediately after being heated to 400 ° C. to separate the semiconductor substrate in the damaged region and further heated to 850 ° C.
The figure shown as a 0-micrometer square. (b) shows Example 2 of the present invention, showing the thin film surface immediately after being heated to 400 ° C. to separate the semiconductor substrate at the damaged region and further heated to 850 ° C., with the measurement region being 2 μm square by AFM.

【図6】(a)は比較例1を示し、450℃に加熱して半
導体基板を損傷領域で分離した直後の薄膜表面を、AF
Mにより測定領域を10μm角として示す図。(b)は比
較例1を示し、450℃に加熱して半導体基板を損傷領
域で分離した直後の薄膜表面を、AFMにより測定領域
を2μm角として示す図。
FIG. 6 (a) shows Comparative Example 1, in which the thin film surface immediately after the semiconductor substrate was separated at the damaged region by heating at 450 ° C.
The figure which shows the measurement area | region as 10 micrometers square by M. (b) shows Comparative Example 1, showing the thin film surface immediately after heating to 450 ° C. to separate the semiconductor substrate in the damaged region, and the measurement region measured by AFM as 2 μm square.

【図7】(a)は比較例2を示し、450℃に加熱して半
導体基板を損傷領域で分離し更に1000℃まで加熱し
た直後の薄膜表面を、AFMにより測定領域を10μm
角として示す図。(b)は比較例2を示し、450℃に加
熱して半導体基板を損傷領域で分離し更に1000℃ま
で加熱した直後の薄膜表面を、AFMにより測定領域を
2μm角として示す図。
FIG. 7 (a) shows Comparative Example 2, in which the thin film surface immediately after being heated to 450 ° C. to separate the semiconductor substrate in the damaged region and further heated to 1000 ° C. was measured by AFM to have a measurement region of 10 μm.
Figure shown as a corner. (b) shows Comparative Example 2, and shows the thin film surface immediately after being heated to 450 ° C. to separate the semiconductor substrate at the damaged region and further heated to 1000 ° C., where the measurement region is 2 μm square by AFM.

【符号の説明】[Explanation of symbols]

11 半導体基板 11a 酸化層(絶縁層) 11b 損傷領域 11c 厚肉部 11d 薄膜 12 支持基板 13 積層体 14 SOI基板 11 Semiconductor substrate 11a Oxide layer (insulating layer) 11b Damage area 11c thick part 11d thin film 12 Support substrate 13 laminate 14 SOI substrate

フロントページの続き (56)参考文献 特開 平5−211128(JP,A) 特開 平9−162090(JP,A) (58)調査した分野(Int.Cl.7,DB名) H01L 27/12 H01L 21/265 Continuation of the front page (56) Reference JP-A-5-212128 (JP, A) JP-A-9-162090 (JP, A) (58) Fields investigated (Int.Cl. 7 , DB name) H01L 27 / 12 H01L 21/265

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 表面に絶縁層(11a)が形成された半導体
基板(11)に水素イオンを注入して前記半導体基板(11)内
部に前記絶縁層(11a)に平行な損傷領域(11b)を形成する
工程と、 前記半導体基板(11)を支持基板(12)に重ね合せて積層体
(13)を形成する工程と、 前記積層体(13)を1×10-6〜1×10-11torrの真空
中で400〜500℃の範囲に昇温して前記半導体基板
(11)を前記損傷領域(11b)で厚肉部(11c)及び薄膜(11d)
に分離する工程とを含むSOI基板の製造方法。
1. A damaged region (11b) parallel to the insulating layer (11a) inside the semiconductor substrate (11) by implanting hydrogen ions into the semiconductor substrate (11) having an insulating layer (11a) formed on the surface thereof. And a step of forming the semiconductor substrate (11) on the supporting substrate (12) to form a laminated body.
The step of forming (13); and heating the laminated body (13) to a temperature in the range of 400 to 500 ° C. in a vacuum of 1 × 10 −6 to 1 × 10 −11 torr.
(11) in the damaged region (11b) thick part (11c) and thin film (11d)
A method of manufacturing an SOI substrate, the method comprising:
【請求項2】 積層体(13)の温度を所定の温度まで下げ
て半導体基板(11)の厚肉部(11c)を除去した後に、前記
積層体(13)を1×10-6〜1×10-11torrの真空中で
900〜1200℃の範囲に昇温して薄膜(11d)表面を
平坦化しかつ前記薄膜(11d)を支持基板(12)に貼合せる
請求項1記載のSOI基板の製造方法。
2. The laminated body (13) is cooled down to a predetermined temperature to remove the thick portion (11c) of the semiconductor substrate (11), and then the laminated body (13) is subjected to 1 × 10 −6 -1. The SOI substrate according to claim 1, wherein the thin film (11d) is flattened by raising the temperature in the range of 900 to 1200 ° C. in a vacuum of × 10 -11 torr and bonding the thin film (11d) to the supporting substrate (12). Manufacturing method.
【請求項3】 損傷領域で分離した厚肉部を薄膜に重ね
たまま積層体を1×10-6〜1×10-11torrの真空中
で900〜1200℃の範囲に更に昇温して、前記薄膜
表面を平坦化しかつ前記薄膜を支持基板に貼合せた後
に、降温して前記厚肉部を除去する請求項1記載のSO
I基板の製造方法。
3. The laminated body is further heated to a temperature of 900 to 1200 ° C. in a vacuum of 1 × 10 −6 to 1 × 10 −11 torr while the thick portions separated in the damaged region are stacked on the thin film. The SO according to claim 1, wherein after the thin film surface is flattened and the thin film is bonded to a supporting substrate, the temperature is lowered to remove the thick portion.
I substrate manufacturing method.
JP13903197A 1997-05-29 1997-05-29 Method for manufacturing SOI substrate Expired - Fee Related JP3412449B2 (en)

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Application Number Priority Date Filing Date Title
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Publications (2)

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JP3412449B2 true JP3412449B2 (en) 2003-06-03

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Publication number Priority date Publication date Assignee Title
JP3395661B2 (en) 1998-07-07 2003-04-14 信越半導体株式会社 Method for manufacturing SOI wafer
US6489241B1 (en) * 1999-09-17 2002-12-03 Applied Materials, Inc. Apparatus and method for surface finishing a silicon film
JP2008028415A (en) * 1999-10-14 2008-02-07 Shin Etsu Handotai Co Ltd Method for manufacturing soi wafer, and soi wafer
JP4103391B2 (en) 1999-10-14 2008-06-18 信越半導体株式会社 Manufacturing method of SOI wafer and SOI wafer
JP2001274368A (en) * 2000-03-27 2001-10-05 Shin Etsu Handotai Co Ltd Producing method for semiconductor bonding wafer and semiconductor bonding wafer produced by the same
JP4581348B2 (en) * 2003-08-26 2010-11-17 信越半導体株式会社 Method for manufacturing bonded wafer and SOI wafer
JP4508021B2 (en) * 2005-07-19 2010-07-21 パナソニック電工株式会社 Manufacturing method of semiconductor light emitting device
FR2914495B1 (en) * 2007-03-29 2009-10-02 Soitec Silicon On Insulator IMPROVING THE QUALITY OF A THIN FILM BY THERMAL RECOVER HIGH TEMPERATURE.
JP2009283582A (en) * 2008-05-21 2009-12-03 Shin Etsu Handotai Co Ltd Bonded wafer manufacturing method and bonded wafer

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