JP3501280B2 - Manufacturing method of semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device including a step of forming a wiring layer and a via of a multi-layer wiring structure by a dual damascene method.

[0002]

2. Description of the Related Art In recent years, with the miniaturization of semiconductor devices, the width of wiring has become narrower and the spacing between wirings has become narrower. Therefore, the wiring resistance increases and the parasitic capacitance due to the wiring increases, which delays the signal speed, which hinders the speeding up of the semiconductor device according to the scaling law.

Under these circumstances, in order to reduce the parasitic capacitance between wirings and the wiring resistance, it is necessary to review the method of forming multilayer wirings and the insulating material and metal wiring material. An insulating material with a low dielectric constant is effective for reducing the wiring capacitance, and aluminum (Al) is also used to reduce the wiring resistance when selecting the material for the metal wiring.
To copper (Cu), which has a low resistivity.

The damascene method is used for processing the copper film because it is difficult to apply conventional dry etching. The damascene method is roughly classified into a single damascene method and a dual damascene method. The single damascene method is a method of forming a plug (via) connecting between the lower wiring and the upper wiring and forming the wiring in separate steps, and the dual damascene method forms the wiring and the plug at the same time. Is the way to do it.

The wiring layers of semiconductor devices have become multi-layered with the miniaturization. For example, the number of wirings reaches 6 in a semiconductor device having a wiring width of 0.18 μm. In this case, in the single damascene method, for example, similar steps are repeated 12 times (wiring formation 6 times and plug formation 6 times), whereas in the dual damascene method to obtain such a structure, All you have to do is repeat the above steps 6 times.

The dual damascene method requires half the number of steps as compared with the single damascene method because the wiring and the plug can be simultaneously formed as described above. Therefore, the dual damascene method is advantageous for suppressing the production cost and increasing the production efficiency. In addition, the dual damascene method
Since the contact resistance between the lower layer wiring and the plug connected thereto is low, it is easy to avoid such contact failure, and the reliability of the wiring is further enhanced.

Regarding the dual damascene method, there is a description that it is applied to an interlayer insulating film having a low dielectric constant insulating film, for example, in Japanese Patent Laid-Open Nos. 9-55429 and 10-112503. First, the process of forming a copper plug and a copper wiring by the dual damascene method disclosed in Japanese Patent Laid-Open No. 9-55429 is shown in FIG.
It is as shown in FIGS. 1 (a) to 1 (d). First, Fig. 1
As shown in (a), a first silicon oxide film 2, an organic low dielectric constant film 3, and a second silicon oxide film 4 are sequentially formed on a silicon substrate 1. In this case, a fluorine-containing resin such as polytetrafluoroethylene is used as the material of the organic low dielectric constant film. Then, the second silicon oxide film 4 is patterned to form an opening 4a having a wiring shape. Next, as shown in FIG. 1B, a resist is formed on the second silicon oxide film 4 and the opening 4a, and this is exposed to light,
After development, a plug window 5a is formed on a part of the opening 4a, and this is used as a resist pattern 5. Then, as shown in FIG. 1C, the organic low dielectric constant film 3 and the first silicon oxide film 2 are sequentially etched through the plug window 5a of the resist pattern 5 to form a via hole 6. Further, as shown in FIG. 1D, the organic low dielectric constant film 3 is selectively etched by oxygen plasma through the opening 4a of the second silicon oxide film 4 to form a wiring groove 7. Then, although not shown in the drawing, copper is embedded in the via hole 6 and the wiring groove 7 to simultaneously form a plug and a wiring.

Next, the steps of forming the copper plug and the copper wiring by the dual damascene method shown in Japanese Patent Laid-Open No. 10-112503 are as shown in FIGS. 2 (a) to 2 (c). First, as shown in FIG. 2A, a wiring groove is formed in the silicon oxide film 12 on the semiconductor substrate 11, and the lower wiring 13 is formed in the wiring groove.
Embed. Then, a low dielectric constant resin film 14 and a low-sensitivity first photoresist film 15 are sequentially formed on the silicon oxide film 12 and the lower wiring 13, and then the first resist film 1 is formed.
5 is exposed to form a latent image 15a for holes. further,
A highly sensitive second photoresist film 16 is applied on the first photoresist film 15 and exposed to form a latent image 16a for wiring. A part of the wiring latent image 16a is formed so as to overlap the hole latent image 15a. Then, as shown in FIG. 2B, the latent image for wiring 16a is removed by continuously developing the first photoresist film 15 and the second photoresist film 16 to form the wiring window 16b. Along with the formation, the latent image 15a for holes is removed to form the window 15b for holes. After that, as shown in FIG. 2 (c), the first and second resists 15 and 16 and the low dielectric constant resin film 14 are sequentially etched from above to form the shapes of the first and second resists 15 and 16. When transferred to the low dielectric constant resin film 14, the vertical connection hole 17 and the wiring groove 18 are formed in the low dielectric constant resin film 14.
Will be formed. Copper (not shown) is simultaneously embedded in the vertical connection hole 17 and the wiring groove 18, and the copper is used as a plug in the vertical connection hole 17 and as a wiring in the wiring groove 18.

[0009]

By the way, in the step shown in FIG. 1A, when a hydrocarbon resin is used as the material of the organic low dielectric constant film 3, the patterning of the second silicon oxide film 4 is performed. When the photoresist 8 used for the above is removed by oxygen plasma, the organic low dielectric constant film 3 thereunder is etched into a wiring shape by oxygen plasma. Therefore, it is formed on the first silicon oxide film 4 thereunder. The pattern accuracy of the via hole is reduced. This is because the low dielectric constant organic material containing hydrocarbon has a chemical property similar to that of the photoresist 8, and therefore only the photoresist 8 cannot be selectively removed.

The reason why the hydrocarbon type resin is used as the organic low dielectric constant film is that the adhesion to the silicon oxide film is better than that of the fluorine type resin. Also, FIG. 2 (a)-
In the step shown in (c), three different types of resin materials, that is, the low dielectric constant resin film 14, the first and second resists 15 and 16 must be etched at the same rate. However, the etching rate of these resin materials is
However, since wiring grooves having different shapes and widths or vertical connection holes having different diameters are to be formed in the same layer, they are different in each layer. On the other hand, it is difficult to control the etching so that the dimensions are as designed.

An object of the present invention is to provide a method for manufacturing a semiconductor device having a step of patterning an interlayer insulating film capable of accurately forming wiring trenches and holes even when a hydrocarbon resin is used as a low dielectric constant film. To provide.

[0012]

[Means for Solving the Problems] (1) The above problems are
As illustrated in FIGS. 3 to 8, a third substrate is formed on the semiconductor substrate .
Insulating film, the first insulating film, the first organic insulating film, the second insulating film, forming a metal film in this order, the first opening having a wiring pattern of the metal film is partially etched Forming a second opening having a via pattern shape by etching a portion of the second insulating film that overlaps a part of the first opening, and forming the second insulating film. Using as a mask to etch the first organic insulating film through the second opening to form a third opening having the via pattern shape in the first organic insulating film; By etching the second insulating film through the first opening of the film, a fourth opening having the wiring pattern shape is formed in the second insulating film, and at the same time, the fourth organic insulating film is formed. The first through the third opening Forming a fifth opening with the via pattern by etching the insulating film on the second insulating film, a portion of the via hole openings said fifth
And a step of etching the first organic insulating film through the fourth opening of the second insulating film to form a sixth opening having the wiring pattern shape in the first organic insulating film. A step of applying the sixth opening and the fourth opening as a wiring groove, and the step of applying the third insulating layer through the sixth opening.
Form the seventh opening by etching the edge film
Semiconductor device having a step of forming a part of the via hole
And a third insulating film and the third insulating film.
The step of forming a second organic insulating film between the insulating films is further performed.
The second organic insulating film has the first organic insulating film.
At the same time as forming the sixth opening in the membrane, the first insulation
The eighth layer is etched through the fifth opening in the border film.
An opening is formed, and the eighth opening is the fifth opening.
It is applied as the via hole together with the seventh opening.
A step of forming a via in the via hole and a wiring in the wiring groove by simultaneously embedding a conductor in the via hole and the wiring groove; and a step of removing the metal film. It is solved by having a.

[0013]

Next, the operation of the present invention will be described. According to the present invention, a first insulating film, an organic insulating film, a second insulating film and a metal film are sequentially formed above a substrate, and then a wiring pattern-shaped opening is formed in the metal film by photolithography. Further, a via pattern-shaped opening is formed in the second insulating film by a photolithography method, and then the organic film is etched using the second insulating film as a mask, and the metal film and the organic film are used as a mask. The second insulating film and the first insulating film are etched at the same time, and then the organic insulating film is etched using the second insulating film as a mask. At this stage, wiring grooves are formed in the organic insulating film and the second insulating film. To form a via hole in the first insulating film.

Therefore, since the organic insulating film can be protected by the second insulating film when the resist used for forming the opening in the metal film is removed, the organic insulating film is removed by the resist removing etchant. It will not be etched. Further, when the second insulating film is used as a mask to etch the organic insulating film thereunder, the resist existing on the second insulating film is removed simultaneously with the etching of the organic insulating film. . This eliminates the need to remove the resist alone, and does not adversely affect the organic insulating film exposed below when removing the resist. As a result, not only the fluorine-containing resin but also the carbon-hydrogen based resin can be applied as the material forming the organic insulating film to form the wiring groove and the via with high accuracy.

Moreover, since the first and second insulating films and the organic insulating film are sequentially etched under the optimum conditions, the via hole or the wiring groove can be formed in these films with high accuracy. (2) The problem described above is that a third insulating film, a first insulating film, a first organic insulating film, and a second insulating film are sequentially provided on a semiconductor substrate as illustrated in FIGS. 9 to 11. A step of forming, a step of partially etching the second insulating film to form a first opening having a via pattern shape, and a step of forming the first opening through the first opening of the second insulating film. Etching the organic insulating film to form a second opening having the via pattern shape in the first organic insulating film; and etching a region of the second insulating film including the first opening. To form a third opening having a wiring pattern shape, and etching the first insulating film under the second opening of the first organic insulating film to form a fourth opening. is formed on the first insulating film, the opening of said fourth via hole one Step and the second the first organic insulating film through said third opening of the insulating film to form a fifth opening is etched into the first organic insulating film, said fifth opening to And a step of applying the third opening as a wiring groove, and the third insulation through the fourth opening.
Before forming the sixth opening by etching the film
Semiconductor device having a step of forming part of the via hole
And a third insulating film.
The process further includes forming a second organic insulating film between the edge films.
The second organic insulating film is the first organic insulating film.
Forming the fifth opening at the same time as forming the first insulation
The seventh opening is etched through the fourth opening in the membrane.
A mouth is formed and the seventh opening is in front of the fourth opening.
Apply as the via hole together with the sixth opening
And a step of forming a via in the via hole and forming a wiring in the wiring groove by simultaneously embedding a conductor in the via hole and the wiring groove. This is solved by the method of manufacturing the device.

[0017]

Next, the operation of the present invention will be described. According to the present invention, a first insulating film, an organic insulating film, and a second insulating film are sequentially formed, and then a via pattern-shaped opening is formed in the second insulating film by photolithography. Forming a via pattern-shaped opening in the organic insulating film through the opening of the insulating film, and then forming a wiring pattern-shaped opening in the second insulating film by the photolithography method, and at the same time using the organic insulating film as a mask. The insulating film is etched to form a via pattern-shaped opening, and the second insulating film is used as a mask to etch the organic insulating film to form a wiring pattern-shaped opening.

As described above, by forming the via pattern-shaped opening in the second insulating film, the step of removing the resist used in forming the opening and the organic insulating film using the second insulating film as a mask. The step of forming a via pattern-shaped opening in the film can be performed simultaneously. Therefore, when removing the resist, it is possible to avoid patterning the organic insulating film thereunder into an unnecessary shape.
Further, when removing the resist on the second insulating film, the organic insulating film is not etched to an unnecessary size,
The accuracy of the opening of the organic insulating film is not reduced.

Moreover, after the wiring pattern shaped openings are formed in the second insulating film and the via pattern shaped openings are formed in the underlying organic insulating film, the shapes of these openings are formed in the film below them. Since the wiring groove and the via hole are formed in the first and second insulating films and the organic insulating film by sequentially transferring, the first and second insulating films and the organic insulating film can be individually optimized. The etching can be performed under the conditions, and the wiring groove and the via hole can be formed with high accuracy.

As described above, the dual damascene method can be applied to the formation of a multilayer wiring layer using a copper wiring and a low dielectric constant organic insulating film without selecting the material of the organic insulating film. Can improve the performance, reliability and production efficiency. Note that a lower organic insulating film may be interposed between the first insulating film and the second insulating film, and etching of the lower organic insulating film is different from etching of the upper organic insulating film. Can be done at the same time. (3) The above-mentioned problems are, as illustrated in FIGS. 17 to 21, a step of sequentially forming a first insulating film and a second insulating film on a semiconductor substrate, and a first window having a via pattern shape. Forming a first photoresist having a via pattern shape on the second insulating film by etching the second insulating film using the first photoresist as a mask. Forming a first opening, forming a second opening having the via pattern shape by etching the first insulating film through the first opening, and forming a second opening having a wiring pattern Forming a photoresist on the second insulating film, and etching the second insulating film using the second photoresist as a mask to form a third opening having the wiring pattern Do And extent, by etching the upper portion of the first insulating film through the third opening,
Forming a fourth opening having the wiring pattern,
A conductive film is embedded in the second opening, the third opening, and the fourth opening to form wiring in the third and fourth openings, and a via is formed in the second opening. A method of manufacturing a semiconductor device, the method comprising:
After forming the second opening, the first photoresist is formed.
The strike is removed using a hydroxylamine-based stripper.
And a semiconductor device manufacturing method.

In the method of manufacturing a semiconductor device described above,
After forming the second opening, the first photoresist may be removed using a hydroxylamine-based stripping solution. In the above-described method for manufacturing a semiconductor device, the second photoresist may be removed using a hydroxylamine-based stripping solution after forming the fourth opening.

In the method of manufacturing a semiconductor device described above,
It is preferable that the first insulating film is made of a hydrocarbon insulating material and the second insulating film is made of a silicon-containing insulating material. In this case, the first photoresist may be etched at the same time when the first insulating film is etched to form the second opening, and the first insulating film may be etched. The second photoresist may be etched simultaneously with the formation of the fourth opening.

Next, the operation of the present invention will be described. According to the present invention, a first insulating film and a second insulating film are sequentially formed above a substrate, and then a via hole pattern is formed on the first and second insulating films using a first photoresist. The opening having a shape is formed, and then the second insulating film and the upper portion of the first insulating film are etched by using the second photoresist to form the opening having a wiring pattern shape.

As described above, when the organic insulating material is used as the first insulating film, by forming the via pattern-shaped opening in the second insulating film, the first insulating film used in forming the opening is used. The step of removing the resist and the step of forming the via pattern by etching the first insulating film can be performed in the same manner. Therefore, when the first resist is removed, the first insulating film made of the organic material thereunder is not etched to an unnecessary size, and the opening accuracy of the organic insulating film is not deteriorated.

Therefore, when the dual damascene method is applied to the formation of the multilayer wiring structure using the copper wiring and the low dielectric constant organic insulating film without selecting the organic insulating material forming the first insulating film, Performance, reliability and production efficiency can be improved. Furthermore, in the present invention, since the via and the wiring are formed in the first insulating film made of an organic material, it is possible to effectively reduce the wiring capacitance as compared with the multilayer wiring structure using silicon oxide or silicon nitride. And again
The number of times of exchanging the etching gas for forming the via hole and the wiring groove in the insulating film is reduced, and the inexpensive multilayer wiring can be formed.

[0027]

DETAILED DESCRIPTION OF THE INVENTION An embodiment of the present invention will be described below with reference to the drawings. (First Embodiment) FIGS. 3 to 8 show a step of forming a wiring of a semiconductor device by a dual damascene method.

First, the process of forming the lower wiring layer will be described with reference to FIGS. 3 (a) to 3 (d). FIG. 3A shows a silicon substrate 2
1 shows a state in which a first silicon oxide film (SiO ₂ film) 22, a first organic insulating film 23, a second silicon oxide film 24, and a photoresist film 25 are formed on top of No. 1. The first silicon oxide film 22 and the second silicon oxide film 24 are formed by plasma CVD to have a thickness of 200 nm and a thickness of 100 nm, respectively.

The first organic insulating film 23 is, for example, a low dielectric constant insulating material manufactured by Allied Signal Co. under the trade name F.
LARE 2.0 is formed by spin coating to a thickness of 400 nm. Trade name FLARE 2.0 is an aromatic polymer, its dielectric constant is 2.8 and SiO ₂
The dielectric constant of the film is lower than 4.1, and the heat resistance is 400 ° C.
That is all. Here, F is used as the first organic insulating film 23.
Although LARE 2.0 was used, it is also possible to use the product name SiLK, which is a hydrocarbon polymer manufactured by Dow Chemical Company. Further, other hydrocarbon-containing resin, fluorine-containing resin, or the like may be used as the first organic insulating film 23.

The photoresist film 25 is a photosensitive polymer, on which a wiring pattern window 25a is formed by exposure and development. Next, as shown in FIG. 3 (b), a second Si film is passed through the window 25a of the photoresist film 25.
The O ₂ film 24 is etched to form a wiring pattern-shaped opening 24.
a is formed. The etching of the second SiO ₂ film 24 is performed using CF ₄
It is performed by a plasma etching method using gas, CH ₂ F ₂ gas and Ar gas. Since such an etching gas is fluorocarbon-based, the second SiO ₂ film 24 is selectively etched to form the wiring openings 24a, while
The first organic insulating film 23 thereunder is hardly etched.

Next, as shown in FIG. 3C, the wiring opening 24a of the second SiO ₂ film 24 of the first organic insulating film 23.
The exposed portion is removed by plasma etching to form a wiring pattern-shaped opening 23a. The etching of the first organic insulating film 23 is performed in an atmosphere in which O ₂ gas and Ar gas are introduced. Since the etchant in this case is oxygen, the first organic insulating film 23 and the photoresist film 25 are selectively etched with respect to the SiO ₂ films 22 and 24, and the SiO ₂ film 24 is not etched. However, since the photoresist film 25 is etched by oxygen, the photoresist film 25 can be removed in parallel with the etching of the first organic insulating film 23.

The opening 24a of the second SiO ₂ film 24 and the opening 23a of the first organic insulating film 23 formed by the patterning process as described above form a first wiring groove 26. The same etching gas as described above is used for etching the organic insulating film and the SiO ₂ film in the subsequent steps.

The opening 23a of the first organic insulating film 23 and the opening 24a of the second SiO ₂ film 24 on it are vertically overlapped, and these are used as the first wiring groove 26. Next, as shown in FIG. 3D, a refractory metal is formed on the inner surface of the first wiring groove 26 and the upper surface of the second SiO ₂ film 24 as a refractory metal.
A first barrier metal film 27 made of TiN or TaN is formed to a thickness of 50 nm by sputtering, and then a first copper (Cu) film 28 is similarly sputtered on the first barrier metal film 27. The film was formed to a thickness of 800 nm.

Since unevenness is generated on the upper surface of the Cu film 28, the Cu film 28 is flattened by 0.1 To in order to flatten the upper surface.
Annealing is performed in a hydrogen gas atmosphere of rr pressure at 400 ° C. for 5 minutes. After this annealing treatment, the Cu film 28 is completely embedded in the first wiring groove 26. Then, as shown in FIG. 4 (a), a chemical mechanical polishing method (CM
P method) is used to polish the Cu film 28 and the first barrier metal film 27 to leave the Cu film 28 and the first barrier metal film 27 only in the first wiring trench 26, and these are used as the first wiring. Used as 29.

Next, as shown in FIG. 4B, a plurality of insulating films, metal films and the like as described below are formed on the first wiring 29 and the second SiO ₂ film 24. That is, the first wiring 2
A silicon nitride film 30 having a film thickness of 50 nm and a third SiO ₂ film 31 having a film thickness of 600 nm are respectively formed on the 9 and the second SiO ₂ film 24 by the plasma CVD method. Further, a second organic insulating film 32 is formed on the third SiO ₂ film 31 by spin coating so as to have a thickness of 400 nm. In this case, as the second organic insulating film 32, one of the above-mentioned materials used for the first organic insulating film 23 is selected. Then, a fourth SiO ₂ film 33 is formed on the second organic insulating film 32 by a plasma CVD method.
To a thickness of 100 nm. Furthermore, the fourth SiO ₂ film 3
An intermediate metal film 34 made of TiN is formed on the substrate 3 by sputtering to a thickness of 100 nm. The intermediate metal film 34
It is also possible to use another refractory metal or a refractory metal compound other than TiN, for example, tantalum (Ta) or tantalum nitride (TaN).

After the formation of the film as described above is completed, a photoresist 35 is applied on the intermediate metal film 34, which is exposed and developed to develop a window 35a corresponding to the shape of the second wiring.
To form. Then, the intermediate metal film 34 is formed by the photolithography method using the photoresist 35 as a mask.
A wiring opening 34a having a shape corresponding to the second wiring is formed. The shape of the wiring pattern is not particularly limited.

Next, as shown in FIG. 4C, the photoresist 35 is ashed by oxygen plasma, but at that time, the second organic insulating film 32 is not exposed from the opening 34a of the intermediate metal film 34. Therefore, the ashing does not adversely affect the second organic insulating film 32. Next, as shown in FIG. 5 (a), a photoresist film 36 is applied on the intermediate metal film 34 and in the opening 34a, and the photoresist film 36 is exposed and developed to form the wiring opening 34a. There is the first wiring 2
A window 36a is formed in the photoresist film 36 so as to face part of the photoresist film 9. The window 36a has a shape corresponding to a contact via. Then, as shown in FIG. 5 (b),
The fourth SiO ₂ film 33 is etched through the window 36a of the photoresist film 36, thereby forming an opening 33a having a shape corresponding to the contact via.

With the etching completed, FIG. 6 (a)
As shown in FIG. 5, the second organic insulating film 32 is etched through the opening 33a by anisotropic plasma etching using oxygen and argon to form the opening 32a therein. During this etching, the entire photoresist film 36 is etched in parallel and removed. Therefore, the step of independently removing the photoresist film 36 becomes unnecessary, and the second organic insulating film 32 is not unnecessarily etched.

Next, as shown in FIG. 6 (b), using the intermediate metal film 34 as a mask, the fourth SiO ₂ film 33 is formed into a wiring shape by plasma etching using a fluorine-based gas through the opening 34a. The opening 33b is formed by etching. During this etching, the second organic insulating film 32 is used as a mask, and the opening 3 of the second organic insulating film 32 is removed.
The third SiO ₂ film 31 thereunder is also etched through 2a, whereby an opening 31a is formed in the third SiO ₂ film 31.

Subsequently, when the second organic insulating film 32 is etched by oxygen plasma through the opening 34a of the intermediate metal film 34, the second organic insulating film 32 is patterned into a wiring shape, and the second organic insulating film 32 is formed therein as shown in FIG. 6 (c). Wiring opening 32 shown in
b is formed. The wiring opening 32b of the second organic insulating film 32 is used as a second wiring groove 37 together with the wiring opening 33b of the fourth SiO ₂ film 33.

Next, as shown in FIG. 7 (a), a second SiO ₂
By using the film 31 as a mask and etching the silicon nitride film 30 under the opening 31a by plasma etching using C ₄ F ₈ gas and O ₂ gas, the opening 30a is formed therein.
To form. The opening 30a of the silicon nitride film 30 and the third
The opening 31a of the SiO ₂ film 31 is formed in the contact via hole 3
It is used as 8, and a part of the first wiring 29 is exposed below it.

Next, as shown in FIG. 7B, along the inner surfaces of the third wiring groove 37 and the contact via hole 38 and the upper surface of the intermediate metal film 34, a first layer of TiN or TaN is formed by sputtering. The second barrier metal film 39 is set to 5
The second Cu film 40 was formed to a thickness of 0 nm, and then the second Cu film 40 was formed to a thickness of 100 nm by sputtering. Further, as shown in FIG. 8A, the second Cu film 40 was used as a seed layer, and a third Cu film 41 was formed thereon to a thickness of 1500 nm by electrolytic plating. 400 for the third Cu film 41
Annealing was performed in a hydrogen atmosphere at 30 ° C. for 30 minutes. The annealing treatment is performed to grow particles in the third Cu film 41 and improve the reliability of the wiring.

Next, as shown in FIG. 8 (b), the third Cu film 41 to the intermediate metal film 34 are sequentially polished by the CMP method, whereby these conductive films are formed into the second wiring trenches. 37
And leave only in the contact via hole 38. And
The conductive film in the second wiring groove 37 is used as the second wiring 42, and the conductive film remaining in the contact via hole 38 is used as the plug 43.

As a result, the dual damascene method of the present invention is completed, and the step of forming another wiring thereon is started. By the way, as described above, after the opening 34a having a shape corresponding to the second wiring is formed in the intermediate metal film 34,
Since the second organic insulating film 32 thereunder is covered with the fourth SiO ₂ film 33, it is not exposed from the opening 34a, and the photoresist film 35 used for patterning the metal film 34 is oxygen-containing. The second organic insulating film 32 is not etched during the plasma etching. As a result, not only the fluorine-containing resin but also the hydrocarbon-containing resin can be used as the material forming the second organic insulating film 32.

Further, since the opening 32a is formed in the second organic insulating film 32 by using the fourth SiO ₂ film 33 having the opening 33a having a shape corresponding to the contact via hole as a mask, the second organic insulating film 32 is formed. The organic insulating film 32 is not unnecessarily etched. Also, as shown in FIG. 6 (a),
The lower inorganic film 31 and the organic insulating film 3 are formed on the first wiring 29.
2, the upper inorganic film 33 and the metal film 34 are sequentially formed, the opening 34a corresponding to the wiring shape is formed in the metal film 34, and the via hole-shaped opening 33a corresponding to the upper inorganic film 33 is formed. From the above, the shape of the opening 33a corresponding to the via hole shape is sequentially transferred to the organic insulating film 32 and the lower inorganic film 31 to form the openings 32a and 31a, and the opening 34a corresponding to the wiring shape is formed from the upper inorganic film 33 and the organic insulating film. The openings 32b and 32b are formed by sequentially transferring to the film 32.

For this reason, since the optimum etching for the type of film can be performed, the shape of the opening formed in each film can be accurately formed. Furthermore, FIG. 5 (b)
In the initial photolithography for forming the via pattern in the step shown in FIG. 2, when the pattern displacement of the photoresist film 36 becomes large when exposed and developed, the photoresist film 36 is exposed to oxygen plasma. The process can be restarted after the removal. This is because the silicon oxide film 3 is formed under the photoresist film 36.
3 is present and the organic insulating film 32 thereunder is not damaged. Therefore, the via diameter can be processed according to the dimension without depending on the positional deviation accuracy of photolithography.

Instead of the above-mentioned SiO ₂ film, Si ₃ N _{4 is used.}
A silicon-containing insulating film such as a film, a SiON film, or a SiC film may be used. This also applies to the embodiments described below. (Second Embodiment) In the first embodiment, the fourth Si
An intermediate metal film 34 is formed on the O ₂ film 33, and a second wiring opening 34a is formed in the intermediate metal film 34.

In this embodiment, a method of forming the wiring groove 37 and the contact via hole without using the intermediate metal film 34 will be described. First, FIG. 9A shows a state in which the intermediate metal film 34 is not formed in the laminated structure shown in FIG. 4B. Then, in this state, a photoresist 44 is applied on the fourth SiO ₂ film 33, and the photoresist 44 is exposed and developed to form a contact via hole window 44.
A is formed on the photoresist 44. The window 44a is
It is located above a part of the first wiring 29.

Next, as shown in FIG. 9B, the fourth SiO ₂ film 33 is etched through the window 44a of the photoresist 44 to form an opening 33c. Then, as shown in FIG. 10A, the window 44a of the photoresist 44 and the fourth Si
The second organic insulating film 32 is etched through the opening 33c of the O ₂ film 33, thereby forming the opening 32c in the second organic insulating film 32. In this case, the second organic insulating film 32 is etched by using an anisotropic plasma etching method using oxygen, whereby the photoresist 44 is simultaneously etched and removed.

After that, as shown in FIG. 10B, a photoresist 45 is formed on the fourth SiO ₂ film 33, and this is exposed and developed to form a window having a pattern for the second wiring. Four
5a is formed. The opening 32 of the second organic insulating film 32 may be formed depending on the developing solution for developing the photoresist 45.
c hardly expands. Next, as shown in FIG. 11 (a),
The fourth SiO ₂ film 3 is passed through the window 45a of the photoresist 45.
When 3 is etched, a wiring opening 33d is formed in the fourth SiO ₂ film 33. When the fourth SiO ₂ film 33 is etched, the third SiO ₂ film 31 is also etched through the opening 32c of the second organic insulating film 32, so that contact vias are formed on the third SiO ₂ film 31. An opening 31c to be the hole 38 is formed.

After that, the step moves to the step shown in FIG. First, when the second organic insulating film 32 is etched through the wiring opening 33d of the fourth SiO ₂ film 33, the opening 3
A wiring opening 32d is formed at a position where 2c is absorbed.
In this case, an anisotropic plasma etching method using an oxygen-containing gas is used for etching the second organic insulating film 32, whereby the photoresist 45 is simultaneously etched and removed. A wiring groove 37 is formed by the wiring opening 33d of the fourth SiO ₂ film 33 and the wiring opening 32d of the second organic insulating film 32.

Subsequently, the silicon nitride film 30 is etched through the opening 31c of the third SiO ₂ film 31 to form the opening 30c to be the contact via hole 38. As a result, a part of the first wiring 29 is exposed from the contact via hole 38. After that, through the same steps as in the first embodiment, as shown in FIG. 11C, a via 43 made of copper is embedded in the contact via hole 38, and the second wiring 42 is formed in the wiring groove 37. Embed.

Unlike the first embodiment, the second embodiment uses a photoresist instead of a metal film as a mask for forming an opening corresponding to a contact via in the fourth SiO ₂ film 33. Therefore, the step of forming the intermediate metal film 34 used in the first embodiment and the step of patterning the intermediate metal film 34 are unnecessary, and the number of steps is smaller than that in the first embodiment, and the forming process is easy. However, the positional deviation that occurs when the photoresist 45 is exposed in FIG. 10B affects the diameters of the openings 30c and 31c, and the diameter of the opening is reduced by the amount of positional deviation. It is effective for forming the wiring opening in the upper layer portion that does not depend so much on the positional deviation accuracy of photolithography.

In this embodiment, unlike the prior art shown in FIG. 1, after forming an opening 33c for forming a contact via hole in the fourth SiO ₂ film 33, an opening 33d for forming a second wiring is formed. And removing the two photoresists 44 and 45 applied on the fourth SiO ₂ film 33 respectively, the opening 3 of the second organic insulating film 32 is removed.
2c and 32d are formed. Therefore, when the photoresist formed on the fourth SiO ₂ film 33 is removed by oxygen plasma, the second organic insulating film 32 is not adversely affected.

By the way, when the relationship between the diameter and the yield of the contact vias formed according to the first and second embodiments described above was investigated by an experiment, FIG.
The results shown in are obtained. FIG. 12 shows that the contact resistance of the via plug including the wirings of the first layer and the wiring of the second layer in the two-layer wiring formed by using the first and second embodiments is measured, and is 10% or more larger than the theoretical value. It is a collection of the yields of items. The horizontal axis of the figure is the via contact diameter. As shown by these results, a high yield of 97% or more could be obtained at any via diameter.

Next, when the lateral distance between the wirings formed in each of the above-described first and second embodiments and the lateral capacitance ratio of the wirings were investigated by an experiment, the result is shown in FIG. The results shown were obtained. FIG. 13 shows the wiring capacitance ratio when the inter-wiring capacitance of the same layer in the two-layer wiring created by the first and second embodiments is measured and compared with the case where only the conventional SiO ₂ film is used. Is shown. The horizontal axis of the figure is the wiring distance. As the result shows, the wiring capacity ratio could be reduced from 60% to 65%. This ratio is almost the same as the ratio between the dielectric constant 4.3 of SiO ₂ and the dielectric constant 2.8 of the organic insulating film, which shows that the wiring was successfully formed. (Third Embodiment) In the first or second embodiment, another organic insulating film may be formed between the silicon nitride film 30 and the third SiO ₂ film 31.

According to this, as shown in FIG. 14, before forming the opening in the silicon nitride 30, the openings 32b and 32d to be wiring grooves are formed in the second organic insulating film 32, and at the same time, the third organic insulating film 32 is formed. Through the openings 31a and 31c of the SiO ₂ film 31, the opening 50a to be a contact via hole is formed in the other organic insulating film 50. After forming the opening 50a, the silicon nitride film 30 is etched through the opening 50a to expose a part of the first wiring, and thereafter,
Similar to the first and second embodiments, the conductive film is buried in the via hole and the wiring groove to form the via and the second wiring.

Incidentally, in FIG. 14, FIG. 6 (c) and FIG.
The same symbols as in (a) indicate the same elements. (Fourth Embodiment) In the first and second embodiments, the insulating layer in which the second copper wiring and the via (plug) are embedded has not only the organic insulating film but also the silicon oxide film. Therefore, in this embodiment, a method of forming a multilayer wiring structure in which the second copper wiring and the via (plug) are embedded in the organic insulating film will be described.

First, as shown in FIG. 15A, a first silicon oxide (SiO ₂ ) film 52 and a first silicon nitride (Si ₃ N ₄ ) film 53 are formed on a silicon substrate 51 by a plasma CVD method. Are sequentially formed to have a thickness of 500 nm and 50 nm, respectively. In this embodiment, silane (SiH ₄ ) and nitric oxide (N ₂ ) are used as a source gas for growing silicon oxide.
O 2) and silane and ammonia (NH ₃ ) as source gas for the growth of the silicon nitride film. Also,
The etching of silicon oxide is similar to that of the first embodiment.
It is performed by a plasma etching method using CF ₄ gas or a mixed gas of CH ₂ F ₂ and Ar. Further, the etching of silicon nitride is performed by a plasma etching method using a mixed gas of CHF ₃ and Ar.

Further, a first organic insulating film 54 having a low dielectric constant is formed on the first silicon nitride film 53. As the first organic insulating film 54, for example, a hydrocarbon-based low dielectric constant organic insulating material containing aromatic is used as the first silicon nitride film 53.
There is one in which spin coating is performed to a thickness of 300 nm on the above, and this is cured by thermal annealing in a nitrogen (N ₂ ) atmosphere at a temperature of 400 ° C. for 30 minutes. As a hydrocarbon-based low dielectric constant organic insulating material containing an aromatic, there is, for example, a product name “SiLK” manufactured by Dow Chemical Company, and its dielectric constant is about 2.7.

Then, a second SiO ₂ film 55 is formed on the first organic insulating film 54 by plasma CVD to a thickness of 100 nm. Next, as shown in FIG. 15 (b), the second Si
A photoresist 56 is applied onto the O ₂ film 55, and the photoresist 56 is exposed and developed to form a window 56a having a wiring pattern. In this embodiment, for example, polyvinylphenol is used as the material of the photoresist.

After that, as shown in FIG. 15C, a part of the second SiO ₂ film 55 exposed from the window 56a is removed by anisotropic plasma etching using the photoresist 56 as a mask. To form the opening 55a, and then, as shown in FIG.
As shown in 6 (a), the opening 54a is formed by removing a part of the first organic insulating film 54 through the opening 55a by the plasma etching method. In this case, nitrogen (N ₂ ) and hydrogen (H ₂ ) are used as the etching gas for the first organic insulating film 54. According to the etching gas, the photoresist 56 is etched simultaneously with the etching of the first organic insulating film 54.
Is also etched away.

A first wiring groove 57 is formed by the opening 55a of the second SiO ₂ film 55 and the opening 54a of the first organic insulating film 54. Next, as shown in FIG. 16B, a first barrier made of tantalum nitride (TaN) as a refractory metal is formed on the inner surface of the first wiring groove 57 and the upper surface of the second SiO ₂ film 55. The metal film 58 was formed to a thickness of 20 nm by sputtering, and then a first copper (Cu) film 59 was formed to a thickness of 800 nm on the first barrier metal film 58 by sputtering.

Since unevenness is generated on the upper surface of the Cu film 59, the Cu film 59 is formed in an atmosphere of a mixed gas of nitrogen and oxygen.
Is annealed at 400 ° C. for 15 minutes to flatten its upper surface. After this annealing treatment, the first wiring groove 5
The Cu film 59 is completely embedded in the inside 7. Then, as shown in FIG. 16 (c), a chemical mechanical polishing method (C
Cu film 59 and the first barrier metal film 58 by using the MP method)
Is polished to leave the Cu film 59 and the first barrier metal film 58 only in the first wiring groove 57, and these are used as the first wiring 60.
To use as.

Next, as shown in FIG. 17A, a plurality of insulating films, metal films and the like as described below are formed on the first wiring 60 and the second SiO ₂ film 55. First, plasma C
Second silicon nitride (Si ₃ N ₄ ) with a film thickness of 50 nm by VD method
The film 61 is formed on the first wiring 60 and the second SiO ₂ film 55. Then, the second organic insulating film 6 having a thickness of about 1000 nm is formed.
2 is formed on the second Si ₃ N ₄ film 61. The second organic insulating film 62 is formed in the same manner as the first organic insulating film 54 using an insulating material such as “SiLK”.

Further, a third SiO ₂ film 63 is formed on the second organic insulating film 62 by plasma CVD to a thickness of 100 nm. Next, as shown in FIG. 17 (b), the third Si
A photoresist 64 is applied on the O ₂ film 63, and this is exposed and developed to form a via-hole-shaped window 64a.
Then, as shown in FIG.
A part of the third SiO ₂ film 63 is removed by a plasma etching method through the window 64a to form an opening 63a in the third SiO ₂ film 63. Subsequently, the opening 62a is formed in the second organic insulating film 62 by etching the second organic insulating film 62 through the opening 63a. Third SiO ₂
The opening 63a of the film 63 and the opening 62 of the second organic insulating film 62
a is used as a contact hole (via hole) 65.

When the anisotropic plasma etching method using a mixed gas of nitrogen and hydrogen as an etching gas is used at the time of etching the second organic insulating film 62, the photoresist 64 is also etched at the same time. It is not necessary to remove the resist 64 in a separate step, and after the photoresist is removed, the second organic insulating film 62 is etched using the third SiO ₂ film 63 as a mask. That is,
The SiO ₂ film and the Si ₃ N ₄ film have an extremely low etching rate with such an etching gas, and thus the second organic insulating film 62
Is etched with high selectivity.

If the photoresist 64 remains after the etching of the second organic insulating film 62, it may be removed by using a hydroxylamine-based solvent. The hydroxylamine-based solvent does not etch the second organic insulating film 62 made of "SiLK". Next, FIG. 18 (b)
As shown in, the photoresist 66 third SiO ₂ film 63
Is applied to the above, and this is exposed and developed to form a window 66a having a wiring pattern. This photoresist 66 is
Depending on the type, it is often difficult to remove it because it accumulates at the bottom of the contact hole 65 after development. If the photoresist 66 in the contact hole 65 is removed with a photoresist solvent, the third SiO ₂ film 6 is removed.
Since the photoresist 66 on 3 is also etched at the same time and the window 66a is deformed, it will be removed in the subsequent steps.

Then, as shown in FIG. 19A, the third SiO ₂ film 63 is etched by using the photoresist 66 as a mask, and the second organic insulating film 62 is further formed to the wiring thickness. Etching is performed in a plasma atmosphere to a depth corresponding to. As a result, the second wiring groove 67 is formed on the third SiO ₂ film 63 and the second organic insulating film 62. When hydrogen and nitrogen are used as the etching gas for the second organic insulating film 62, the photoresist 66 is also etched at the same time.

After forming the second wiring groove 67,
When the photoresist 66 remains on the bottom of the contact hole 65, or when the photoresist 66 remains on the third SiO ₂ film 63, as shown in FIG. The photoresist 66 is removed with a good solvent. The photoresist 66 accumulated at the bottom of the contact hole 65 is formed by the second organic insulating film 6
Since it was exposed to plasma during the etching of No. 2 and its surface was modified, it was difficult to remove it with a good solvent for photoresist, and a hydroxylamine system was effective.

Next, as shown in FIG.
The second Si directly under the toru 65 ₃N_FourMembrane C_FourF₈And O₂To
Removed by the plasma etching method used,
A part of the first wiring 60 is exposed. Then, FIG.
As shown in (b), the second wiring groove 67 and the contact
Inner surface of the cut hole 65 and the third SiO₂Along the top surface of the membrane 63
As a barrier metal, TaN film 6 by sputtering
8 to a thickness of 20 nm, and then by sputtering.
A copper seed film 69 on the TaN film 68 to a thickness of 150 nm.
Form.

Subsequently, as shown in FIG. 21A, a copper film 70 having a thickness of 800 nm is formed on the copper seed layer 69 by electrolytic plating. Then, as shown in FIG. 21B, the copper film 70 and the copper seed film 6 existing on the third SiO ₂ film 63 are formed.
9 and the TaN film 68 are polished and removed by the CMP method. Those metal films remaining in the contact holes 65 after this polishing are used as plugs (vias) 71,
Further, those metal films remaining in the second wiring groove 67 thereon are applied as the second wiring 72.

As described above, in the present embodiment, a process which does not require disposing a material having a high dielectric constant, such as SiO ₂ or Si ₃ N ₄ , which is an inorganic material, around the second wiring 72 and the plug 71 is performed. Since it is used, the wiring capacitance can be effectively reduced as compared with the other dual damascene method. In addition, it is not necessary to separately secure the step of removing the resist, and the number of insulating film layers in which the plug and the second wiring are embedded is smaller than in the conventional case, so the number of steps is reduced.

In this embodiment, “SiLK” is used as the low dielectric constant organic insulating films 54 and 62, but other organic insulating films such as the product name “BCB” of Dow Chemical Co., Allied Signal Co. The product name “FLARE” and the product name “VELOX” of Shoe Macker Company may be used. By the way, the above-described embodiment is based on the following invention. (1) A step of sequentially forming a first insulating film, a first organic insulating film, a second insulating film, and a metal film on a semiconductor substrate, and having a wiring pattern shape by partially etching the metal film. Forming a first opening, etching a portion of the second insulating film overlapping a portion of the first opening to form a second opening having a via pattern shape, Using the second insulating film as a mask, etching the first organic insulating film through the second opening to form a third opening having the via pattern shape in the first organic insulating film. And etching the second insulating film through the first opening of the metal film to form a fourth opening having the wiring pattern shape in the second insulating film, and at the same time, the first opening is formed. Through the third opening of the organic insulation film Etching the first insulating film to form a fifth opening having the via pattern shape in the second insulating film, and applying the fifth opening as a via hole. Etching the first organic insulating film through the fourth opening of the second insulating film to form a sixth opening having the wiring pattern shape in the first organic insulating film; and A step of applying the fourth opening as a wiring groove, and a step of forming a via in the via hole and forming a wiring in the wiring groove by simultaneously embedding a conductor in the via hole and the wiring groove And a step of removing the metal film, a method of manufacturing a semiconductor device. (2) A step of forming a third insulating film under the first insulating film, and a step of forming the seventh opening by etching the third insulating film through the sixth opening to form the via The method for manufacturing a semiconductor device according to (1), further including the step of forming a part of the hole. (3) The method further includes the step of forming a second organic insulating film between the first insulating film and the third insulating film, wherein the second organic insulating film has the first organic insulating film. Simultaneously with forming the sixth opening in the film, the eighth opening is formed by etching through the fifth opening of the first insulating film, and the eighth opening is formed with the fifth opening and the fifth opening. The method of manufacturing a semiconductor device according to (2), further comprising the step of applying the via hole together with the seventh opening. (4) The conductive film is also formed on the second insulating film, and the conductive film on the second insulating film is removed before the metal film ( The method of manufacturing a semiconductor device according to 1). (5) The method for manufacturing a semiconductor device according to (1), wherein the first insulating film and the second insulating film are made of an inorganic insulating material. (6) The method for manufacturing a semiconductor device according to (1), wherein the metal film is made of a refractory metal or a refractory metal compound. (7) The method of manufacturing a semiconductor device according to (1), wherein the conductive film has a two-layer structure of a barrier metal film and a copper film. (8) A resist mask is used when forming the first opening in the metal film, and the resist mask is removed before forming the second opening. Manufacturing method of semiconductor device. (9) Using a resist mask when forming the second opening in the second insulating film, and etching a part of the first organic insulating film to form the third opening. The method of manufacturing a semiconductor device according to (1), wherein the resist mask is simultaneously etched. (10) A step of sequentially forming a first insulating film, a first organic insulating film, and a second insulating film on a semiconductor substrate, and partially etching the second insulating film to form a via pattern shape. Forming a first opening having the second opening, and etching the first organic insulating film through the first opening of the second insulating film to form the second opening having the via pattern shape. And forming a third opening having a wiring pattern shape by etching a region of the second insulating film including the first opening, and forming the third opening having the wiring pattern shape. Etching the underlying first insulating film through the second opening of the film to form a fourth opening in the first insulating film and applying the fourth opening as a via hole; , Through the third opening in the second insulating film The step of etching the first organic insulating film to form a fifth opening in the first organic insulating film, and applying the fifth opening and the third opening as wiring trenches; and the via hole. And a step of forming a via in the via hole and forming a wiring in the wiring groove by simultaneously embedding a conductor in the wiring groove, and a method of manufacturing a semiconductor device. (11) A step of forming a third insulating film below the first insulating film, and a sixth opening is formed by etching the third insulating film through the fourth opening to form the via. The method for manufacturing a semiconductor device according to (10), further including the step of forming a part of the hole. (12) The method further includes the step of forming a second organic insulating film between the first insulating film and the third insulating film, wherein the second organic insulating film has the first organic insulating film. At the same time when the fifth opening is formed in the film, a seventh opening is formed by etching through the fourth opening of the first insulating film, and the seventh opening is formed as the fourth opening and the fourth opening. (11) The method for manufacturing a semiconductor device according to (11), further comprising a step of applying the via hole together with a sixth opening. (13) The conductive film is also formed on the second insulating film, and the conductive film on the second insulating film is removed by a polishing method. Manufacturing method of semiconductor device. (14) The first insulating film and the second insulating film are made of an inorganic insulating material (1)
0) The method for manufacturing a semiconductor device described in 0). (15) The method of manufacturing a semiconductor device according to (10), wherein the conductive film has a two-layer structure of a barrier metal film and a copper film. (16) The first opening of the second insulating film is formed by etching the second insulating film using a resist as a mask, and the resist forms the second opening. Therefore, it is removed in parallel with the etching of the first organic insulating film (1)
0) The method for manufacturing a semiconductor device described in 0). (17) A step of sequentially forming a first insulating film and a second insulating film on a semiconductor substrate, and a first photoresist having a first window having a via pattern shape is formed on the second insulating film. Forming a first opening having the via pattern shape by etching the second insulating film using the first photoresist as a mask, and through the first opening Forming a second opening having the via pattern shape by etching the first insulating film, and forming a second photoresist having a wiring pattern on the second insulating film. Etching the second insulating film using the second photoresist as a mask to form a third opening having the wiring pattern; and the first insulating film through the third opening. By etching the upper,
Forming a fourth opening having the wiring pattern,
A conductive film is embedded in the second opening, the third opening, and the fourth opening to form a wiring in the third and fourth openings, and a via is formed in the second opening. And a step of forming a semiconductor device. (18) The method of manufacturing a semiconductor device according to (17), wherein after the second opening is formed, the first photoresist is removed by using a hydroxylamine-based stripping solution. (19) The method of manufacturing a semiconductor device according to (17), wherein after the fourth opening is formed, the second photoresist is removed using a hydroxylamine-based stripping solution. (20) The manufacturing of the semiconductor device according to (17), wherein the first insulating film is made of a hydrocarbon-based insulating material and the second insulating film is made of a silicon-containing insulating material. Method. (21) The method for manufacturing a semiconductor device according to (20), wherein the hydrocarbon insulating material contains an aromatic. (22) The silicon-containing insulating material is silicon oxide,
The method for manufacturing a semiconductor device according to (20), which is silicon nitride, silicon oxynitride, or silicon carbide. (23) The method of manufacturing a semiconductor device according to (20), wherein the first photoresist is etched at the same time when the first insulating film is etched to form the second opening. (24) The method of manufacturing a semiconductor device according to (20), wherein the second photoresist is etched at the same time when the first insulating film is etched to form the fourth opening.

[0075]

As described above, according to the present invention, in the multilayer damascene process by the dual damascene method using the inorganic material and the low dielectric organic material for the interlayer insulating film and copper for the wiring, the best inorganic After forming a via-hole-shaped opening in the insulating film, use the uppermost inorganic insulating film as a mask to form a via-hole-shaped opening in the organic insulating film below it.
Then, after forming the wiring-shaped opening in the uppermost inorganic insulating film, the uppermost inorganic insulating film was used as a mask to form the wiring-shaped opening in the organic insulating film thereunder, so that the opening of the uppermost inorganic insulating film was formed. The photoresist used for forming the film can be removed at the same time when the opening of the next organic insulating film is formed, and it is possible to prevent the opening of the organic insulating film from being adversely affected when removing the photoresist.

Further, according to the present invention, the shapes of the wiring opening formed in the uppermost inorganic insulating film and the via hole formed in the organic insulating film are sequentially transferred to the insulating film below them. The inorganic insulating film and the organic insulating film forming the interlayer insulating film can be etched under optimum conditions. Therefore, by using the present invention, it is possible to effectively reduce the inter-wiring capacitance, obtain a good via contact resistance, and improve the performance and reliability of the semiconductor device.

Further, according to the present invention, since the via and the wiring are formed in the organic insulating film by the dual damascene method, the wiring capacitance can be effectively reduced as compared with the multilayer wiring structure using silicon oxide or silicon nitride. In addition, the number of times of exchanging the etching gas for forming the via hole and the wiring groove in the insulating film is reduced, and the inexpensive multilayer wiring can be formed.

[Brief description of drawings]

FIG. 1A to FIG. 1D are cross-sectional views showing a process of forming a multilayer wiring structure by a first conventional dual damascene method.

2 (a) to 2 (c) are cross-sectional views showing a step of forming a multilayer wiring structure by a second conventional dual damascene method.

3 (a) to 3 (d) are cross-sectional views (No. 1) showing a step of forming a multilayer wiring structure by a dual damascene method according to the first embodiment of the present invention.

FIGS. 4A to 4C are cross-sectional views (No. 2) showing a step of forming a multilayer wiring structure by the dual damascene method according to the first embodiment of the present invention.

5A and 5B are cross-sectional views (3) showing a process of forming a multilayer wiring structure by the dual damascene method according to the first embodiment of the present invention.

6A to 6C are cross-sectional views (No. 4) showing a step of forming a multilayer wiring structure by the dual damascene method according to the first embodiment of the present invention.

7A and 7B are cross-sectional views (No. 5) showing a step of forming a multilayer wiring structure by the dual damascene method according to the first embodiment of the present invention.

8A and 8B are cross-sectional views (No. 6) showing a step of forming a multilayer wiring structure by the dual damascene method according to the first embodiment of the present invention.

9A and 9B are cross-sectional views (No. 1) showing a process of forming a multilayer wiring structure by a dual damascene method according to the second embodiment of the present invention.

FIGS. 10A and 10B are cross-sectional views (No. 2) showing a step of forming a multilayer wiring structure by the dual damascene method according to the second embodiment of the present invention.

11 (a) to 11 (c) are cross-sectional views (No. 3) showing a step of forming a multilayer wiring structure by the dual damascene method according to the second embodiment of the present invention.

FIG. 12 is a diagram showing a relationship between a diameter and a yield of contact vias formed according to the first embodiment and the second embodiment.

FIG. 13 is a diagram comparing the spacing and capacitance of the wirings formed according to the first embodiment and the second embodiment with the relationship with the related art.

FIG. 14 is a cross-sectional view showing a step of forming an opening to an organic insulating film in a dual damascene method according to the third embodiment of the present invention.

15A to 15C are cross-sectional views (No. 1) showing a step of forming a multilayer wiring structure by a dual damascene method according to the fourth embodiment of the present invention.

16A to 16C are cross-sectional views (No. 2) showing a step of forming a multilayer wiring structure by the dual damascene method according to the fourth embodiment of the present invention.

17 (a) and 17 (b) are cross-sectional views (3) showing a process of forming a multilayer wiring structure by a dual damascene method according to the fourth embodiment of the present invention.

18A and 18B are cross-sectional views (No. 4) showing a process of forming a multilayer wiring structure by the dual damascene method according to the fourth embodiment of the present invention.

19A and 19B are cross-sectional views (No. 5) showing a step of forming a multilayer wiring structure by the dual damascene method according to the fourth embodiment of the present invention.

FIGS. 20 (a) and 20 (b) are cross-sectional views (No. 6) showing a step of forming a multilayer wiring structure by the dual damascene method according to the fourth embodiment of the present invention.

21A and 21B are cross-sectional views (No. 7) showing a step of forming a multilayer wiring structure by the dual damascene method according to the fourth embodiment of the present invention.

[Explanation of symbols]

21 ... Silicon (semiconductor) substrate, 22 ... First SiO ₂ film,
23 ... First organic insulating film, 24 ... Second SiO ₂ film, 25 ...
Photoresist film, 26 ... First wiring groove, 27 ... First barrier metal film, 28 ... Cu film, 29 ... First wiring, 30
... silicon nitride, 31 ... third SiO ₂ film, 32 ... second organic insulating film, 33 ... fourth SiO ₂ film, 34 ... intermediate metal film, 3
5 ... Photoresist, 36 ... Photoresist, 37 ... Second wiring groove, 38 ... Contact via hole, 39 ... Ti
N film, 40 ... Copper film, 41 ... Copper film, 42 ... Second wiring, 4
3 ... Via, 44 ... Photoresist, 45 ... Photoresist, 50 ... Organic insulating film. 51 ... Silicon (semiconductor) substrate, 61 ... Silicon nitride film, 62 ... Organic insulating film, 63 ...
Silicon oxide film, 64 ... Photoresist, 65 ... Contact (via) hole, 66 ... Photoresist, 67 ...
Wiring groove, 68 ... TaN film, 69 ... Copper seed film, 70 ... Copper film, 71 ... Plug (via), 72 ... Second wiring.

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/768 H01L 21/28 H01L 21/3205

Claims (7)

(57) [Claims] 1. A step of sequentially forming a third insulating film, a first insulating film, a first organic insulating film, a second insulating film, and a metal film on a semiconductor substrate, and the metal film is partially formed. To form a first opening having a wiring pattern shape, and etching a portion of the second insulating film overlapping a part of the first opening to form a second opening having a via pattern shape. Forming an opening; and using the second insulating film as a mask, etching the first organic insulating film through the second opening to form a third opening having the via pattern shape. Forming a first organic insulating film, and etching the second insulating film through the first opening of the metal film to form a fourth opening having the wiring pattern shape in the second insulating film. At the same time as forming into A fifth opening having the via pattern shape is formed in the second insulating film by etching the first insulating film through the third opening of the edge film, and the fifth opening is formed as a via hole. And a step of forming a sixth opening having the wiring pattern shape by etching the first organic insulating film through the fourth opening of the second insulating film. And applying the sixth opening and the fourth opening as wiring trenches, and forming the seventh opening by etching the third insulating film through the sixth opening And a step of forming a second organic insulating film between the first insulating film and the third insulating film. The first organic insulating film is formed on the second organic insulating film. A sixth opening is formed in the machine insulating film, and at the same time, an eighth opening is formed by etching through the fifth opening of the first insulating film, and the eighth opening is the fifth opening. And a step of applying as a via hole together with the seventh opening, a conductor is simultaneously embedded in the via hole and the wiring groove to form a via in the via hole and a wiring in the wiring groove. And a step of removing the metal film, a method of manufacturing a semiconductor device. 2. A step of sequentially forming a third insulating film, a first insulating film, a first organic insulating film and a second insulating film on a semiconductor substrate, and the second insulating film is partially formed. Forming a first opening having a via pattern shape by etching, and etching the first organic insulating film through the first opening of the second insulating film to have the via pattern shape. Forming a second opening in the first organic insulating film; and etching a region of the second insulating film including the first opening to form a third opening having a wiring pattern shape. Together with, etching the first insulating film thereunder through the second opening of the first organic insulating film,
Forming a fourth opening in the first insulating film and making the fourth opening part of a via hole; and the first organic insulating film through the third opening in the second insulating film. Etching the film to form a fifth opening in the first organic insulating film, and applying the fifth opening and the third opening as wiring grooves; and the third opening through the fourth opening. A step of forming a sixth opening by etching the insulating film to form a part of the via hole, wherein the first insulating film and the third insulating film are formed. And a step of forming a second organic insulating film between, the second organic insulating film, at the same time as forming the fifth opening in the first organic insulating film, at the same time as the first The insulating film is etched through the fourth opening to form a seventh opening, and The seventh opening is applied as the via hole together with the fourth opening and the sixth opening, and a conductor is simultaneously embedded in the via hole and the wiring groove to form a via hole in the via hole. And a step of forming a wiring in the wiring groove, the method for manufacturing a semiconductor device. 3. A step of sequentially forming a first insulating film and a second insulating film on a semiconductor substrate, and a step of forming a first photoresist having a first window having a via pattern shape on the second insulating film. Forming a first opening having the via pattern shape by etching the second insulating film using the first photoresist as a mask; Forming a second opening having the via pattern shape by etching the first insulating film through the opening; and forming a second photoresist having a wiring pattern on the second insulating film. A step of forming a third opening having the wiring pattern by etching the second insulating film using the second photoresist as a mask, and the first opening through the third opening A step of forming a fourth opening having the wiring pattern by etching the upper part of the insulating film; and filling a conductive film in the second opening, the third opening and the fourth opening, Forming a wiring in the third and fourth openings and forming a via in the second opening, the method comprising: The method of manufacturing a semiconductor device, wherein the first photoresist is removed using a hydroxylamine-based stripping solution. 4. A step of sequentially forming a first insulating film and a second insulating film on a semiconductor substrate, and a step of forming a first photoresist having a first window having a via pattern shape on the second insulating film. Forming a first opening having the via pattern shape by etching the second insulating film using the first photoresist as a mask; Forming a second opening having the via pattern shape by etching the first insulating film through the opening; and forming a second photoresist having a wiring pattern on the second insulating film. A step of forming a third opening having the wiring pattern by etching the second insulating film using the second photoresist as a mask, and the first opening through the third opening A step of forming a fourth opening having the wiring pattern by etching the upper part of the insulating film; and filling a conductive film in the second opening, the third opening and the fourth opening, Forming a wiring in the third and fourth openings and forming a via in the second opening, the method comprising: The method for manufacturing a semiconductor device, wherein the second photoresist is removed using a hydroxylamine-based stripping solution. 5. A step of sequentially forming a first insulating film and a second insulating film on a semiconductor substrate, and a step of forming a first photoresist having a first window having a via pattern shape on the second insulating film. Forming a first opening having the via pattern shape by etching the second insulating film using the first photoresist as a mask; Forming a second opening having the via pattern shape by etching the first insulating film through the opening; and forming a second photoresist having a wiring pattern on the second insulating film. A step of forming a third opening having the wiring pattern by etching the second insulating film using the second photoresist as a mask, and the first opening through the third opening A step of forming a fourth opening having the wiring pattern by etching the upper part of the insulating film; and filling a conductive film in the second opening, the third opening and the fourth opening, Forming a wiring in the third and fourth openings and forming a via in the second opening, wherein the first insulating film is a hydrocarbon. And a second insulating film formed of a silicon-containing insulating material. 6. The manufacturing of a semiconductor device according to claim 5, wherein the first photoresist is etched at the same time when the first insulating film is etched to form the second opening. Method. 7. The semiconductor device manufacturing method according to claim 5, wherein the second photoresist is etched at the same time when the first insulating film is etched to form the fourth opening. Method.