JP3214475B2 - Method of forming dual damascene wiring - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a dual damascene wiring used for a multilayer wiring technique or the like.

[0002]

2. Description of the Related Art An embedded wiring (Damascene) technique is effective as a method for forming a multilayer wiring in a semiconductor integrated circuit device. Among them, a wiring groove where an upper layer wiring is formed,
After a via hole or a contact hole (hereinafter, referred to as a via hole including both) connecting the upper wiring and the lower wiring or the substrate is formed in an insulating film, a metal film is simultaneously buried in the wiring groove and the via hole to form a wiring. The dual damascene technology for simultaneously forming vias has an advantage that manufacturing costs can be significantly reduced due to simplification of a manufacturing process and rapid TAT (Turn-and-Around-Time).

FIG. 15 is a cross-sectional view showing a wiring forming method using the conventional dual damascene technique in the order of steps. First, as shown in FIG. 15A, a silicon oxide (SiO ₂ ) film 2 is formed as an interlayer insulating film on a silicon substrate 1, and a silicon nitride (SiN) film 3 is further formed thereon. Forming a resist film 4 on the nitride film 3;
This resist film 4 is patterned into a via hole pattern by photolithography. Thereafter, using the resist film 4 as a mask, the silicon nitride film 3 is plasma-etched to form a via hole pattern 5 in the silicon nitride film 3.

Thereafter, as shown in FIG. 15B, a silicon oxide film 6 is formed on the entire surface. Next, the surface of the silicon oxide film 6 is cleaned by CMP (Chemical Mechanical Polishing).
ng; chemical mechanical polishing).

Then, as shown in FIG. 15C, a resist film 7 is formed on the silicon oxide film 6, and the resist film 7 is patterned into a wiring groove pattern 9. Thereafter, by etching using the resist film 7 and the silicon nitride film 3 as a mask, a via hole is opened in the silicon oxide film 2 and a wiring groove is formed in the silicon oxide film 6.
In this case, etching is performed by an etching method having a high etching selectivity between the silicon oxide film and the silicon nitride film (etching speed of the silicon oxide film / etching speed of the silicon nitride film). The nitride film 3 remains as a mask.

After that, the resist film 7 is removed, and a conductive material is buried in the via hole and the wiring groove to form a via and a wiring.

In this conventional method for forming a dual damascene wiring, as shown in FIG. 15C, when a shift occurs between the via hole pattern 5 and the wiring groove pattern 9, the gap between the wiring and the via is formed. There is a disadvantage that the contact area is small and the contact resistance is high. Also, as the aspect ratio of the via hole increases, that is, as the ratio of the depth to the width of the via hole increases, the etching selectivity of the silicon oxide film 2 to the silicon nitride film 3 serving as a stopper needs to be extremely high. It is difficult to perform a proper etching condition in the process. Further, FIG.
As shown in (c), the upper edge of the via hole after etching is largely etched, so-called shoulder drop occurs.

FIG. 16 shows a conventional method of forming a dual damascene wiring which has solved the disadvantages of the prior art shown in FIG. 15 (JP-A-8-335634 and JP-A-10-223755). . FIG.
3A to 3D are cross-sectional views showing another conventional method of forming a dual damascene wiring in the order of steps. FIG.
As shown in FIG. 1A, a silicon oxide film 12 is formed on a silicon substrate 11, and the silicon oxide film 12 is etched by photolithography to form a via hole 13.

Next, as shown in FIG. 16B, an organic compound is applied to the entire surface to fill the via holes 13 with the organic compound film 14, and a resist film 15 is formed on the silicon oxide film 12 and the organic compound film 14. Then, the resist film 15 is patterned into a wiring groove pattern 16 by photolithography. This organic compound has an etching selectivity to a silicon oxide film as an interlayer insulating film of 1 /
2 or less.

Next, as shown in FIG. 16C, the wiring groove 16 is formed by plasma etching the organic compound film 14 and the silicon oxide film 12 using the wiring pattern of the resist film 15 as a mask. In this case, the organic compound film 14 embedded in the via hole 13
Since the silicon oxide film 12 has a higher etching selectivity than the silicon oxide film 12, the organic compound film 14 remains in the via hole 13 while the wiring groove 16 is being etched.

Thereafter, by removing the resist film 15 and the organic compound film 14, a via hole 13 is formed together with the wiring groove 16. By burying these wiring grooves 16 and via holes 13 with a conductive material, wirings and vias are formed.

In the conventional method configured as described above, as shown in FIG. 16C, even if a deviation occurs between the via hole and the wiring groove, as shown in FIG. The contact area between the via embedded in the wiring and the wiring embedded in the wiring groove 16 is not reduced. Therefore, the contact resistance between the two is sufficiently low. Further, in the prior art shown in FIG. 15, when the aspect ratio of the via hole increases, the etching selectivity of the silicon oxide film with respect to the silicon nitride film 3 needs to be extremely high. However, in the prior art shown in FIG. It is not necessary to take such etching conditions.

[0013]

However, the conventional method of forming a dual damascene has the following problems. That is, as shown in FIG. 16A, when the via hole 13 is formed by etching, due to the etching characteristics, the via hole 13 has a larger cross-sectional area at the upper opening and a smaller cross-sectional area at the bottom. For this reason,
The side surface of the via hole 13 is slightly inclined so that the upper side is warped backward.

As described above, since the side surface of the via hole 13 is inclined, when the wiring groove 16 is formed by etching in the step of FIG.
Since the etching selectivity of the organic compound film 14 is smaller than the etching selectivity of the silicon oxide film 12,
And an etching residue of the silicon oxide film 12 is generated immediately below the etching mask. For this reason, as shown in FIG. 16D, even after the organic compound film 14 is removed, a protrusion 17 made of a silicon oxide film remains at the upper end of the via hole 13. The projections 17 are mixed in the wiring, and cause poor conductivity of the wiring.

The present invention has been made in view of such a problem, and no foreign matter remains in a wiring due to an etching residue of an interlayer insulating film in an etching process, and a wiring failure does not occur. An object is to provide a method for forming a dual damascene wiring.

[0016]

According to a first aspect of the present invention, there is provided a method of forming a dual damascene wiring, comprising: forming an interlayer insulating film on a lower conductive layer; and forming a hole pattern opening on the interlayer insulating film. (1) forming a resist film;
Forming a hole by etching the interlayer insulating film using the first resist film as a mask, and forming a buried film by filling the hole with a material having a higher etching rate than the interlayer insulating film; Forming a second resist film having an opening of a wiring groove pattern on the buried film; and etching the buried film and the interlayer insulating film by using the second resist film as a mask to form a wiring groove in the interlayer insulating film. Forming a hole, and forming the hole.
In the etching step to leave a part of the interlayer insulating film.
Etching to stop the etching .

In the method for forming a dual damascene wiring according to the second invention of the present application, a step of forming a first interlayer insulating film on a lower conductive layer, and a first resist having a hole pattern opening on the first interlayer insulating film are provided. Forming a film;
Forming a hole by etching the first interlayer insulating film using the resist film as a mask, the said hole first
And forming a buried layer by embedding etching rate than first interlayer insulating film at a fast material, a second interlayer on the entire surface
Forming an insulating film; and forming a wiring on the second interlayer insulating film.
Forming a second resist film having an opening of the groove pattern, the second interlayer said second resist film as a mask
And having a step of forming a wiring groove of the insulating film by etching to Rukoto.

[0018] The present method of forming a third invention according dual damascene wiring includes the steps of: forming a first interlayer insulating film on the lower conductor, the second interlayer insulating film on the first interlayer insulating film
Forming a first resist film having an opening of a hole pattern on the second interlayer insulating film; and forming the first and second resist films using the first resist film as a mask .
Forming a hole by etching the second interlayer insulating film; filling the hole with a buried film;
Includes a step of forming a second resist film having an opening of the wiring trench pattern above and forming a wiring groove by etching the second interlayer insulating film the second resist film as a mask, the The second interlayer insulating film is embedded
The etching rate is faster than the film, and the buried film is
The etching rate is faster than that of the interlayer insulating film.
I do.

In the present gun onset Ming, after embedding the embedded film in the hole, performs the etching for forming wiring grooves, the embedded film in the case of the interlayer insulating film (third invention first
1) , and a material having an etching selectivity higher than that of the first interlayer insulating film is used, and the etching rate of the buried film is higher than that of the interlayer insulating film. The surface of the film is lower than the top edge of the hole. Therefore, in the step of etching the interlayer insulating film for forming the wiring groove, the buried film does not serve as an etching mask, so that the etching residue of the interlayer insulating film does not occur, and the conventional protrusion remains is avoided. Can be.

[0020]

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be specifically described below with reference to the accompanying drawings. 1A to 1C and 2A to 2C are cross-sectional views showing a method of forming a dual damascene wiring according to an embodiment of the present invention in the order of steps. As shown in FIG. 1A, on the conductor layer 21,
After an interlayer insulating film 22 such as a silicon oxide film is formed, a resist film 23 is applied on the interlayer insulating film 22, and then the resist film 23 is exposed and developed to form an opening pattern 31 for forming a via hole. The conductor layer 21 is a substrate on which a lower layer wiring of a multilayer wiring structure or a semiconductor element is formed. The interlayer insulating film 22 has a thickness sufficient to form a wiring groove and a via hole (hereinafter, also referred to as a via hole including a contact hole). The resist film 23 is a photosensitive organic film for forming a via hole. The conductor layer 2
When 1 is a lower layer wiring of a multilayer wiring, a hole formed in an interlayer insulating film thereabove is called a through hole, and when conductor layer 21 is a semiconductor substrate, it is formed in an interlayer insulating film thereabove. The hole is called a contact hole,
In the present invention, both are referred to as via holes.

Then, a via hole 32 is formed in the interlayer insulating film 22 by etching the interlayer insulating film 22 using the resist film 23 as a mask. At this time, the interlayer insulating film 22 slightly remains in the via hole 32.

Next, as shown in FIG. 1B, the resist film 23 is removed, a material different from the interlayer insulating film 22 is buried in the via hole 32, and a buried film 24 is formed. The buried film 24 is made of, for example, Si ₃ N ₄ , SiON (SixO
yNz), oxide film (SiO ₂ ), SiOF (SixOy)
Fz) or the like, or polysilicon, an organic oxide (coating film), an inorganic oxide (coating film), or the like. These materials have a higher etching rate than the material constituting the interlayer insulating film 22 such as silicon oxide, and the etching selectivity between the interlayer insulating film 22 and the buried film 24 is less than 1. Since ordinary inorganic materials have a higher etching rate than oxides, various materials can be used as the buried film 24. The buried film 24 can be formed by CVD (chemical vapor deposition), coating, or the like. For example, the buried film 24 is a CVD Si ₃ N ₄ film.

Next, a resist film 25 made of a photosensitive organic film is applied on the buried film 24,
5 is patterned by photolithography to form a wiring groove pattern 33. The etching selectivity between the interlayer insulating film (silicon oxide film) 22 and the resist film (photosensitive organic film) 25 is, for example, 5 or more.

Thereafter, as shown in FIG. 1C, the buried film 24 and the interlayer insulating film 22 are formed using the resist film 25 as a mask.
Is etched to form a wiring groove 34. In this case,
As described above, since the etching rate of the interlayer insulating film 22 is higher than the etching rate of the resist film 25 (the etching rate ratio is 5 or more), the interlayer insulating film 22 is etched into a wiring groove shape using the resist film 25 as a mask, Since the etching selectivity between the film 22 and the buried film 24 is less than 1, and the buried film 24 has a higher etching rate than the interlayer insulating film 22, the etching of the buried film 24 proceeds more than the interlayer insulating film 22. Therefore, as shown in FIG. 1C, the upper surface of the buried film 24 in the via hole 32 is located lower than the upper edge of the via hole 32 when the etching of the wiring groove 34 is completed. As an etching method, for example, plasma etching using a mixed gas of CHF ₃ gas, O ₂ gas and Ar gas can be used. In this case, the etching selectivity between the interlayer insulating film and the buried film is 1 or less.

Next, as shown in FIG.
Photosensitivity for forming wiring trenches by hardly removing the edge film 22
The resist film 25 and the buried film 24, which are organic films, are removed.
To remove the buried film 24, Cl_TwoGas and HBr gas
Plasma etching using a mixed gas of
In this case, etching of the buried film and the interlayer insulating film is performed.
The selection ratio is 10 or more. Also, for removing the buried film 24
Are wet etching, isotropic dry etching and
Any of anisotropic dry etching and the like may be used.
In this case, the process gas for isotropic dry etching
C_xF_yH_zGas, O_TwoGas, Cl_TwoGas, HBr gas, S
F₆Gas or the like can be used. In addition, anisotropic
Etching process gas is also C_xF_yH_zGas, O_TwoMoth
Su, Cl _TwoGas, HBr gas, SF₆Use gas, etc.
Can be.

At the same time as the removal of the buried film 24 or after the removal of the buried film 24, the interlayer insulating film 22 remaining at the bottom of the via hole 32 is removed. As a result, a via hole 32 and a wiring groove 34 are formed.

Thereafter, as shown in FIG. 2B, a wiring material 26 (conductive material) is embedded in the via holes 32 and the wiring grooves 34.

Next, as shown in FIG. 2C, the surface of the wiring material 26 is polished by CMP to expose the surface of the interlayer insulating film 22. As a result, a via 35 is formed in the via hole 32, and a wiring 36 is formed in the wiring groove 34.

In the method of the present embodiment configured as described above, the via hole 3 formed in the step shown in FIG.
1C, the buried film 24 is faster than the interlayer insulating film 22 in the step of forming the wiring groove 34 as shown in FIG. Since the buried film 24 is etched, the buried film 24 does not serve as a mask for preventing the etching when the interlayer insulating film 22 is etched. For this reason, the etching residue of the interlayer insulating film does not occur, and the protrusions do not mix in the wiring unlike the related art.

In this embodiment, as shown in FIG. 1A, in the etching step of forming the via hole 32, this etching is stopped halfway, and the interlayer insulating film 22 is slightly placed on the bottom of the via hole 32. Since a large part of the interlayer insulating film 22 and the buried film 24 remaining in the via hole 32 are etched, the processing time is shortened by using high-energy dry etching. When the thin interlayer insulating film 22 in the via hole 32 is removed in the step shown in FIG.
It is possible to prevent damage to the diffusion layer when the conductor layer 21 is a substrate.

Next, a method according to a second embodiment of the present invention will be described with reference to FIGS. First, FIG.
As shown in FIG. 1A, a first interlayer insulating film 22a made of an insulating material having an etching selectivity smaller than that of a buried material is formed on a silicon substrate 21.
A second interlayer insulating film 22b made of an insulating material having an etching selectivity higher than that of the buried material is formed on 2a. As described above, in this embodiment, the interlayer insulating film is formed by stacking different materials. Then, the second interlayer insulating film 22
b, a resist film 23 is applied, and is patterned into a via hole pattern 31. Next, the resist film 2
3 as a mask, the first and second interlayer insulating films 221 and 22
b is etched to form a via hole 32.

Next, as shown in FIG. 3B, after removing the resist film 23, a material different from the interlayer insulating film is buried in the via hole 32 to form a buried film 24. Thereafter, a resist film 25 is formed on the buried film 24, and a wiring groove pattern 33 is formed in the resist film 25.

Thereafter, as shown in FIG. 3C, the buried film 24 and the second interlayer insulating film 22b are etched using the resist film 25 as a mask. The etching conditions in this case are such that the etching selectivity of the second interlayer insulating film 22b is
And the etching selectivity of the first interlayer insulating film 22a is smaller than the etching selectivity of the buried film 24. Therefore, in this etching step, the buried film 2 on the second interlayer insulating film 22b is formed.
After the portion 4 is etched, the second interlayer insulating film 22b is formed.
In the part, the second interlayer insulating film 22b and the buried film 24 are removed by etching based on the wiring groove pattern 33 of the resist film 25. Thereafter, etching is performed on the first interlayer insulating film 22.
a, the buried film 24 has a higher etching selectivity in the first interlayer insulating film 22a, so that the first interlayer insulating film 22a
Is hardly etched, and the buried film 2 in the via hole 32 is not etched.
4 is preferentially etched. When the buried film 24 in the via hole 32 is slightly etched, the etching is stopped.

The subsequent steps are the same as in the first embodiment shown in FIGS. 2 (a) to 2 (c). That is, by removing the resist film 25 and the buried film 24, the wiring groove 34 and the via hole 32 are formed. Thereafter, a conductive material is buried in these wiring grooves 34 and via holes 32, and the surface of the conductive material is polished by CMP to form the same wiring and via holes as in FIG. 2C.

In this embodiment, a laminated film made of materials having different etching selectivity is used as the interlayer insulating film, and when the etching is transferred from the second interlayer insulating film to the first interlayer insulating film, the etching selective ratio is changed. By stopping the etching on the basis of the variation of the wiring groove, the wiring groove and the via hole can be clearly distinguished. Therefore, in the present embodiment, the depth of the wiring groove and the depth of the via hole can be controlled by the thicknesses of the first interlayer insulating film 22a and the second interlayer insulating film 22b. Compared to the case where the depths of the wiring grooves and the via holes are controlled by the etching time and the like, the depths of the wiring grooves and the like can be controlled with higher precision.

Next, FIGS. 4A to 4C and FIG.
A third embodiment of the present invention will be described with reference to (a) to (c). In this embodiment, as shown in FIG. 4A, a material different from the interlayer insulating film 22 is formed on the silicon substrate 21 as the etching stopper layer 27, and the interlayer insulating film and the resist are formed on the etching stopper layer 27. A film 23 is formed. Thereafter, a via hole pattern 31 is formed in the resist film 23, and the interlayer insulating film 22 is etched using the resist film 23 as a mask. In this case, the etching is stopped by the stopper layer 27 below the interlayer insulating film 22. Thereby, the via hole 32 is formed, and the surface of the conductor layer 21 is not damaged by the etching.

Next, as shown in FIG. 4B, a material different from the interlayer insulating film is buried in the via hole 32 to form a buried film 24, and then, as shown in FIG. Using the resist film 25 on which the pattern 33 is formed as a mask, the buried film 24 and the interlayer insulating film 22 are etched to a predetermined depth. Thereby, the wiring groove 34 is formed.

Next, as shown in FIG. 5A, the resist film 25 and the buried film 24 are removed and the buried film 24 is removed.
Simultaneously with or after the removal of the etching stopper layer 27 in the via hole 32 is removed.

Thereafter, as shown in FIG. 5B, the wiring material 26 is buried in the via hole 32 and the wiring groove 34, and the surface of the wiring material 26 is polished by CMP to form the wiring 36 and the via 35.

In this embodiment, since the etching stopper layer 27 is formed on the lowermost conductive layer 1, there is no possibility that the conductive layer 1 is damaged by etching. In this case, etching damage of elements formed on the substrate is prevented.

Next, a fourth embodiment of the present invention will be described with reference to FIGS. In this embodiment, as shown in FIG. 6A, as in the first embodiment shown in FIG. 1, the interlayer insulating film 22 is etched by using the resist film 23 to form the interlayer insulating film 22. A via hole 32 is formed.

Next, as shown in FIG. 6B, a material different from the interlayer insulating film is buried in the via hole 32 to form a buried film 24. When the buried film 24 is buried in the via hole 32, as shown in FIG.
In this embodiment, the buried film 24 is formed only in the via hole 32 by means of etch back, CMP, wet etching, or the like. All the upper embedded film 24 is removed.

Thereafter, the resist film 2 is formed on the interlayer insulating film 22.
5 is applied to the resist film 25 to form a wiring groove pattern 3
Form 3

Next, as shown in FIG. 6C, the interlayer insulating film 22 is etched using the resist film 25 as a mask to form a wiring groove 34. After the etching is performed to the depth of the wiring groove 34, the etching is stopped. Then, after removing the resist film 25 and the buried film 24, FIG.
Wirings and vias are formed in the same steps as in (a) to (c).

In this embodiment, after the buried film having a high etching selectivity on the interlayer insulating film is removed, the wiring groove is etched, so that the horizontal direction is formed between the resist film 25 and the interlayer insulating film 22. The etching does not proceed in the direction. For this reason, it is possible to form the wiring groove 34 that matches the shape defined by the wiring groove pattern 33 of the resist film 25 with high precision without causing corners at the upper edge of the wiring groove 34 due to etching. it can.

Next, FIGS. 7A to 7C and FIG.
A reference example of the present invention will be described with reference to (a) to (c). First, as shown in FIG. 7A, an interlayer insulating film 22 is formed on the conductor layer 1, and a resist film 25 is formed on the interlayer insulating film 22. A wiring groove pattern 33 is formed in the resist film 25. Thereafter, a part of the interlayer insulating film 22 in the thickness direction is etched using the resist film 25 as a mask, so that the wiring groove 34 is formed above the interlayer insulating film 22.
To form When the etching is performed for the depth of the wiring groove 34, the etching is stopped.

Next, as shown in FIG. 7B, the wiring groove 34 is buried with a burying material to form a buried film 24. This buried film 24 has an etching selectivity of the interlayer insulating film 2.
It is higher than 2.

After that, a resist film 23 is formed on the buried film 24. Next, a via hole pattern 31 is formed in the resist film 23. The resist film 23 has an etching selectivity much lower than that of the interlayer insulating film 22 and has a lower etching rate.

Thereafter, as shown in FIG. 7C, the buried film 24 is etched using the resist film 23 as a mask, and the interlayer insulating film 22 is further etched until the conductor layer 21 is exposed, thereby forming a via hole 32. To form The etching conditions in this case are such that the etching rate of the buried film 24 is the highest, then the etching rate of the interlayer insulating film 22 is the highest, and the etching rate of the resist film 23 is the lowest.

Next, as shown in FIG. 8A, the resist film 23 and the buried film 24 are removed, and a wiring groove 34 and a via hole 32 are formed.

After that, as shown in FIG. 8B, the wiring groove 34 and the via hole 32 are filled with the wiring material 26, and as shown in FIG.
The interlayer insulating film 22 is exposed by P polishing. This allows
The wiring 36 and the via 35 are formed.

[0053] In this reference example, on the upper edge of the via hole 32 in the interlayer insulating film 22 is higher embedded film 24 is etch selectivity is formed by etching the portion of the embedded film 24 horizontal Direction, and no protrusion remains on the upper edge of the via hole 32 .

Next, FIGS. 9A to 9C and FIG.
A second reference example of the present invention will be described with reference to (a) to (c). The second reference example is different from the reference example shown in FIGS. 7 and 8 only in that an etching stopper layer 27 is provided. In the second reference example, as shown in FIG. 9A, the etching stopper layer 27 is formed on the conductor layer 21.
Is formed, a wiring groove 34 is formed in the interlayer insulating film 22 using the resist film 25 as a mask, and the buried film 24 is buried in the wiring groove 34 as shown in FIG.
As shown in (c), the buried film 24 and the interlayer insulating film 22 are etched using the resist film 23 as a mask. This etching stops at the etching stopper layer 27.

Next, as shown in FIG. 10A, the etching stopper layer 27 remaining in the via hole 32 is removed by etching, and a wiring material 26 is buried as shown in FIG. 2), the wiring material 26 is polished by CMP to form the wiring 36 and the via hole 35.

[0056] In this second reference example, in addition to the same effects as the reference example shown in FIGS. 7 and 8, FIGS. 4 and 5
As in the embodiment shown in FIG. 7, when the conductor layer 21 is a substrate, it is possible to prevent the damage.

As an application of the reference example shown in FIGS. 7 and 8, as in the embodiment shown in FIGS. 1 and 2, in the step of forming a via hole by etching, the etching is stopped halfway and the embedded film is removed. The remaining portion of the interlayer insulating film may be removed simultaneously with the removal or after the removal of the buried film. Further, as in the embodiment shown in FIG. 3, a laminated film of a different material may be used as the interlayer insulating film. Further, similarly to the embodiment shown in FIG. 6, after the buried film is buried in the via hole, the buried film may be left only in the via hole, and the other portions may be entirely removed.

Next, FIGS. 11A to 11C and FIG.
A fifth embodiment of the present invention will be described with reference to (a) to (c). In this embodiment, first, FIG.
As shown in FIG. 1, a first interlayer insulating film 22 having a thickness enough to form a via hole on the conductor layer 21 is formed.
A resist film 23 is formed on the interlayer insulating film 22, and a via hole pattern 31 is formed in the resist film 23. Then, via hole 32 is formed by etching first interlayer insulating film 22 using resist film 23 as a mask.

Next, as shown in FIG. 11B, the via hole 32 is buried with a buried film 24, and a second interlayer insulating film having a thickness sufficient to form a wiring groove on the buried film 24. 28 are formed.

Thereafter, as shown in FIG.
A resist film 25 is formed on the interlayer insulating film 28, and a wiring groove pattern 33 is formed in the resist film 25. And
The second interlayer insulating film 28 is etched by the wiring groove pattern 33 to form a wiring groove 34. In this case, the etching conditions are such that the etching speed of the buried film 24 is higher than the etching speed of the first interlayer insulating film 22 and the second interlayer insulating film 28, and the etching speed of the interlayer insulating film 28 is higher than the etching speed of the resist film 25. Is also faster. This etching stops when the first interlayer insulating film 22 is exposed.

Thereafter, as shown in FIG.
The resist film 25 and the buried film 24 in the via hole 32 are removed so that the interlayer insulating film 22 and the second interlayer insulating film 28 are hardly removed.

Next, as shown in FIG. 12B, the wiring material 26 is buried in the wiring groove 34 and the via hole 32,
This is subjected to CMP polishing to form wirings 36 and vias 35 shown in FIG.

Also in this embodiment, as shown in FIG. 11C, since the buried film 24 has a higher etching rate than the first interlayer insulating film 22, the buried film 24 remaining in the via hole 32 is formed. Is lower than the first interlayer insulating film 22. Therefore, the upper edge of the buried film 24 does not serve as a mask when the first interlayer insulating film 22 is etched. Therefore, the first interlayer insulating film 22 is not left unetched.

Next, FIGS. 13A to 13C and FIG.
A sixth embodiment of the present invention will be described with reference to (a) to (c). This embodiment is different from the embodiments shown in FIGS. 11 and 12 in that the buried film 24 is left only in the via hole 32 and the other buried films 2 are formed as shown in FIG.
4 is to be removed.

For this reason, FIGS. 11C and 12A
To (c), FIG. 13 (c) and FIGS. 14 (a) to (c)
As is clear from the comparison with the first embodiment, in the present embodiment, between the first interlayer insulating film 22 and the second interlayer insulating film 28,
There is an advantage that the buried film 24 does not remain and the range of selection as the material of the buried film is wide.

As an application of the embodiment shown in FIGS. 11 and 12, similarly to the embodiment shown in FIGS. 4 and 5, an etching stopper layer may be provided between the conductor layer 21 and the first interlayer insulating film 22. good. Also, as shown in FIGS. When the via hole 32 is formed, the interlayer insulating film 22 may be left slightly, and the interlayer insulating film 22 remaining at the same time as the removal of the buried film 24 or after the removal of the buried film 24 may be removed.

[0067]

As described in detail above, according to the present invention,
In the etching step of forming wiring grooves and holes in the interlayer insulating film, no etching residue of the interlayer insulating film is generated, and therefore, the remaining protrusions of the interlayer insulating film are not mixed in the wiring, and the wiring quality is improved. Can be.

[Brief description of the drawings]

FIGS. 1A to 1C are sectional views showing a method of forming a dual damascene wiring according to a first embodiment of the present invention in the order of steps.

FIGS. 2 (a) to 2 (c) are views showing steps subsequent to FIG. 1 in the order of steps in the first embodiment.

FIGS. 3A to 3C are cross-sectional views illustrating a method of forming a dual damascene wiring according to a second embodiment of the present invention in the order of steps.

FIGS. 4A to 4C are cross-sectional views illustrating a method of forming a dual damascene wiring according to a third embodiment of the present invention in the order of steps.

FIGS. 5A to 5C are views showing the next step of FIG. 4 in the order of steps in the third embodiment.

FIGS. 6A to 6C are sectional views showing a method of forming a dual damascene wiring according to a fourth embodiment of the present invention in the order of steps.

FIGS. 7A to 7C are cross-sectional views illustrating a method of forming a dual damascene wiring according to a reference example of the present invention in the order of steps.

FIGS. 8 (a) to 8 (c) are the same in this reference example.
FIG. 8 is a diagram illustrating a step next to FIG. 7 in the order of steps.

FIGS. 9A to 9C are cross-sectional views illustrating a method of forming a dual damascene wiring according to a second reference example of the present invention in the order of steps.

FIGS. 10 (a) to (c) are views showing the steps next to FIG. 9 in the same order as in the second reference example.

FIGS. 11A to 11C are sectional views showing a method of forming a dual damascene wiring according to a fifth embodiment of the present invention in the order of steps.

12 (a) to 12 (c) are views showing steps subsequent to FIG. 11 in the same fifth embodiment in the order of steps.

13A to 13C are cross-sectional views illustrating a method of forming a dual damascene wiring according to a sixth embodiment of the present invention in the order of steps.

FIGS. 14 (a) to (c) are views showing the next step of FIG. 13 in the same order as in the sixth embodiment.

15A to 15C are cross-sectional views showing a conventional method of forming a dual damascene wiring in the order of steps.

16 (a) to (d) are cross-sectional views showing another conventional method of forming a dual damascene wiring in the order of steps.

[Explanation of symbols]

 1: silicon substrate 2: silicon oxide film 3: silicon nitride film 4: resist film 5: via hole pattern 11: silicon substrate 12: interlayer insulating film 13: via hole 14: buried film 15: resist film 16: wiring groove 17: protrusion Object 21: Conductive layer 22, 22a, 22b, 28: Interlayer insulating film 23, 25: Resist film 24: Embedded film 26: Wiring material 27: Etching stopper layer 31: Via hole pattern 32: Via hole 33: Wiring groove pattern 34: Wiring groove 35: Via 36: Wiring

──────────────────────────────────────────────────の Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/3205-21/3213 H01L 21/768

Claims (10)

(57) [Claims] A step of forming an interlayer insulating film on the lower conductor layer, a step of forming a first resist film having an opening of a hole pattern on the interlayer insulating film, and using the first resist film as a mask. Forming a hole by etching the interlayer insulating film, forming a buried film by filling the hole with a material having a higher etching rate than the interlayer insulating film, and forming a wiring groove pattern on the buried film. Forming a second resist film having an opening, and using the second resist film as a mask, etching the buried film and the interlayer insulating film to form a wiring groove in the interlayer insulating film ; Etching process for forming the hole
The etching is stopped by leaving a part of the interlayer insulating film.
A method of forming a dual damascene wiring, characterized in that the wiring is stopped . 2. A step of forming a first interlayer insulating film on the lower conductor layer, a step of forming a first resist film having an opening of a hole pattern on the first interlayer insulating film,
Forming a hole by etching the first interlayer insulating film using a resist film as a mask, and forming a buried film by filling the hole with a material having a higher etching rate than the first interlayer insulating film. Forming a second interlayer insulating film over the entire surface, forming a second resist film having an opening of a wiring groove pattern on the second interlayer insulating film, and forming the second resist film using the second resist film as a mask. Forming a wiring groove by etching an interlayer insulating film. 3. The method according to claim 1, further comprising a step of removing a buried film in the hole and a step of burying a conductive material in the wiring groove and the hole to simultaneously form a wiring and a contact or a via. 3. The method for forming a dual damascene wiring according to 1 or 2 . 4. An interlayer insulating film remaining in the hole,
4. The method according to claim 3 , wherein the removal is performed simultaneously with or after the removal of the buried film. 5. A first interlayer insulating film is formed on a lower conductor.
And a second interlayer insulating film on the first interlayer insulating film.
Forming a hole , and forming a hole pattern on the second interlayer insulating film.
Forming a first resist film having a turn opening
And the first and second resists using the first resist film as a mask.
Forming a hole by etching the second interlayer insulating film
Filling the hole with a buried film;
Forming a second resist film having a wiring groove pattern opening thereon
Forming, and using the second resist film as a mask,
Wiring grooves are formed by etching the second interlayer insulating film.
Forming the second interlayer insulating film with the embedded layer.
The etching rate is faster than the film, and the buried film is
The etching rate is faster than that of the interlayer insulating film.
Of forming dual damascene wiring. 6. A step of forming an etching stopper layer between the lower conductor layer and the interlayer insulating film, wherein the etching is stopped at the etching stopper layer in the hole etching step. Claim 1
Or the method for forming a dual damascene wiring according to 2 . 7. The method according to claim 1, further comprising a step of removing the buried film on the interlayer insulating film and leaving the buried film only in the hole as a step subsequent to the step of forming the buried film. The method for forming a dual damascene wiring according to claim 1 . 8. The dual damascene wiring according to claim 2 , further comprising a step of removing the buried film on the first interlayer insulating film as a step subsequent to the step of forming the buried film. Forming method. Wherein said lower conductor layer is the lower layer wiring, the hole forming method for a dual damascene wiring according to any one of claims 1乃<br/> optimum 8, which is a hole . 10. The semiconductor device according to claim 1, wherein said lower conductor is a semiconductor substrate, and said hole is a via hole.
9. The method for forming a dual damascene wiring according to any one of claims 1 to 8 .