JP3498862B2 - Receiving phasing circuit of ultrasonic equipment - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wave receiving and phasing circuit of an ultrasonic device, that is, a wave receiving and phasing circuit of an ultrasonic device for transmitting and receiving ultrasonic waves to obtain a tomographic image It is also referred to as a "phase circuit"), and particularly to a wave rectifying circuit improved by a variable aperture technology that changes the aperture size according to the focus depth.

[0002]

2. Description of the Related Art A conventional variable-aperture technology for a wave receiving and phasing circuit is described in various medical ultrasonic handbooks. For example, it is known that the azimuth resolution Δx at the focus of a rectangular oscillator having a diameter D is Δx = λF / D, where λ is the wavelength and F is the focus distance, and is inversely proportional to the size of the diameter. Therefore, as shown in FIG. 8, a method of obtaining a good beam by changing the aperture according to the focus distance (horizontal axis in the figure) is widely adopted. This method is, for example, as shown in FIG. 8B, n array elements (ch1 to ch
In n), for the short distance, ch4 to ch (n-3) are used to focus on the point of F1. Then, the aperture is increased in order and the focus position is shifted, so that FIG.
As described above, a good ultrasonic beam is obtained. Further, conventionally, regarding the received wave, since it is a phasing circuit using an analog delay line, the aperture has been controlled in an analog manner by a phasing output buffer circuit, a variable gain amplifier and the like. In addition, in a circuit configuration for digitizing and phasing a received signal, as a configuration including a multiplier, for example, Japanese Patent Laid-Open No. 2-2
The technology disclosed in Japanese Patent No. 6548 is known.

[0003]

In the above prior art, when the signal after the received analog signal is erased is digitized by the AD converter, even if the signal of the buffer circuit is set to 0, noise and offset of the circuit will be generated. Occurs,
There is a problem that this is included in the digital signal and converted. Further, the technique related to digital phasing disclosed in Japanese Patent Laid-Open No. 2-26548 describes only the phasing method and does not consider the concept of the variable aperture. The present invention has been made in view of the above circumstances, and an object of the present invention is to solve the above-mentioned problems in the related art and to reduce noise in a variable aperture in digital phasing. It is to provide a phasing circuit.

[0004]

The above object of the present invention is to make the multiplication data of the digital multiplier zero after digitally converting the received signals from the arrayed ultrasonic transducers, and reset the latch. To control the write / read of the memory, control the sample clock of the AD converter, etc. to zero the received signal of the unused channel and then add it to the output signals of other channels. Is achieved by a wave phasing circuit of an ultrasonic device.

[0005]

In the wave receiving and phasing circuit according to the present invention, after the ultrasonic wave receiving signal is digitally converted, (1) the multiplication data of the channels located in the unused caliber is set to zero, or (2) ) By setting the latch output to zero, it is possible to output a 0 level signal without noise. The output of the memory is set to 0 by (3) controlling the write / read clock to the memory or (4) controlling the sample clock of the AD converter.
Therefore, it is possible to output a 0 level signal without noise.

[0006]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 shows a wave receiving and phasing circuit according to a first embodiment of the present invention. As shown in FIG. 1A, the received signal received by the transducers arranged in strips is quantized by the sampling means 1 and written in the memory 2. When the sampling means 1 is an analog-digital converter, the received signals of the respective channels are digitized by the sampling clocks S1 to Sn and written in the memory by the write pulses W1-Wn. Next, the data written in the memory 2 is read by the read pulses R1 to Rn at the timing or address designation for correcting the time difference of each channel, and the delay amount less than the sampling interval is corrected by the delay processing circuit 3, and each channel is read. The ultrasonic beams are formed by matching the phases of and adding by the adder 4.

After that, it is processed by the signal processing circuit 5 and displayed as an ultrasonic image. In order to form a good ultrasonic beam, the weighting factors WE1-W are assigned to each channel.
Multiplying En is done. This is performed in order to reduce side lobes that occur because the shape of the aperture formed by the transducer array is rectangular. In this embodiment, as described above, the operation of changing the size of the aperture according to the focus distance is performed by using the multiplication data. That is, as shown in FIG. 1B, ch3-ch (n-2) is used for the focus distance F1, ch2-ch (n-1) is used for F2, and all channels are used for F3. For simplification, if a triangle weight is given, as shown in FIG. 1C, ch1 gives a weighting coefficient of 0 in F1 and F2, and a coefficient of a in F3. ch2 gives a weight of 0 for F1, a for F2, and b for F3. The same applies hereinafter.

By this processing, in the wave-reception phasing circuit according to this embodiment, in F1, it is equivalent to ch1, 2, (n-1), and n being substantially not connected, and the aperture can be reduced. is there. Others are the same. Next, a wave receiving and phasing circuit according to a second embodiment of the present invention will be described with reference to FIG. The present embodiment is one example of controlling the aperture in the delay processing circuit 3 of the embodiment shown in FIG. In this embodiment, 90
This is an example of a delay method that samples once and performs complex processing. In the case of a complex signal, as shown in FIG.
The phase rotation can be realized by multiplying the real part signal and the imaginary part signal by the value of and adding them by the crossing as shown in the figure. Note that FIG. 2 shows the basic configuration of one channel, and the phase rotation amount can be set for each channel. Also in the present embodiment, the aperture can be controlled by setting the multiplication data to 0 as in the first embodiment.

FIG. 2B shows an example of the sequence. If ch1 is used from F3, F1, F2
Then, the value of φ1 is usually cos (θ) = if sin (θ) = 0
Although 1 or -1, both sin (θ) and cos (θ) are 0.
By this processing, in F1 and F2, it becomes equivalent to that ch1 is not substantially connected, and the aperture can be reduced. Others are the same. Next, a wave receiving and phasing circuit according to a third embodiment of the present invention will be described with reference to FIG. This embodiment is shown in FIG.
This is a second example of controlling the aperture in the delay processing circuit 3 of the embodiment shown in FIG. In the present embodiment, the roughly quantized sample data is obtained by interpolating a desired point using a sampling function.

In this method, delayed data is generated by multiplying each sampled data of several consecutive points by a coefficient and adding the coefficient. The present embodiment is an example in which interpolation is performed using data of four points. Also in this embodiment, the multiplication data is set to 0 as in the other embodiments described above.
The diameter can be controlled by setting. Figure 3 (b)
Shows an example of the sequence. Similarly to the above, if ch1 is used from F3, the coefficients a, b, c, and d are set to 0 in F1 and F2, and interpolation data a1-3, b1-3, and c1-3 are calculated from F3. , D1-3 are given. By this processing, in F1 and F2, it is equivalent to that ch1 is not substantially connected, and the aperture can be reduced. Others are the same.

Next, a wave receiving and phasing circuit according to a fourth embodiment of the present invention will be described with reference to FIG. In the present embodiment, the received signal is multiplied by the reference wave to shift the frequency. This embodiment is an example of analog frequency shift. In general, AD
The above operation is performed in order to keep the frequency of the converter low. It should be noted that, after digitization, digital frequency shift may be performed, and either case can be dealt with. Also in this embodiment, as in the other embodiments described above, the aperture can be controlled by setting the multiplication data to 0. FIG. 4B shows an example of the sequence.
If ch1 is used from F4, F1, F2, F
In 3, the amplitude of the reference wave is set to 0 or is not input.
The amplitude is set to 1 from F4.

The phase of the reference wave at this time may be the same in all channels, or, if a delay shorter than the sampling time is made by the phase difference of the reference wave, it is given by the phase difference realizing the delay. The amplitude weight shown in the first embodiment can be realized by the amplitude of the reference wave. By this processing, in F1, F2, and F3, it becomes equivalent to that ch1 is not substantially connected, and the aperture can be reduced. Others are the same. Next, a wave receiving and phasing circuit according to a fifth embodiment of the present invention will be described with reference to FIG. This embodiment is shown in FIG.
This is an example in which the aperture is controlled in the adder 4 of the example shown in FIG.

In digital addition, a latch circuit is inserted to synchronize data. Therefore, even if the delayed data is input to the adder 4 by using this latch circuit having a reset function, the input data of the adder 4 can be held at 0 by keeping the latch in the reset state. In this embodiment, the diameter is controlled by this operation. FIG. 5B shows an example of the sequence.
If ch1 is used from F3, by setting the latch of ch1 to reset state in F1, F2 and operating from F3, it becomes equivalent to ch1 not being connected in F1 and F2, and the aperture is It can be made smaller. Others are the same.

It should be noted that although the description has been given here using the latch of the adder input, the same configuration and operation are possible if the latch is in the signal path. In each of the above embodiments, A
The sample clock of the D converter, the writing to the memory, and the reading from the memory can control the aperture even if control is performed using the entire aperture without considering the aperture change. Further, it goes without saying that even in the example in which the processing of the real part signal is described, it can be applied to the complex processing including the imaginary part. Next, a sixth embodiment of the present invention will be described with reference to FIG. As a delay method using a memory, there are a FIFO method and a method of designating an address. FI
When FO is used, a write pulse is not given to each channel until the required data is first fetched,
After more than the maximum delay time when forming the beam,
Give a read pulse.

In FIG. 6A, the horizontal axis represents the sampling time t, the vertical axis represents each channel, and a, b, c, ... Represent the received signals from the focus point. . This means adding data of the same alphabet for each channel.
FIG. 6B shows the contents of the memory 2 of each channel. W1 of ch1 is applied from t = 5. Therefore, all a's are written at address 1 of the memory of each channel. Here, the maximum delay (in this case, tdmax =
4) After that, that is, by giving a read pulse to each channel from t = 6 and reading them all at once, the phases of all the channels can be aligned. Here, ch1 is t =
Assuming that it is used from 7, the write pulse of ch1 is given from t = 7, and the read pulse is given from t = 8.

Address 1 of the memory of ch1 in FIG. 6 (a)
At, the value c of t = 7 is written. In ch5,
Since it is read from t = 6, when ch1 reads address 1 at t = 8, ch5 outputs the value c of address 3. At t = 6 and 7, since the values of FIG. 6B are output except for ch1, only the data of the unused diameter ch1 can be set to 0 until the start of use, and the variable diameter can be realized. Next, the case of using a memory such as a RAM that can specify an address will be described. In the present embodiment, writing is started from address 0 all channels at once, and after reading a maximum delay or more, the start address is set to all channels all at once according to the delay time, and reading is performed. The phase of the channels is adjusted.

In this case, as shown in FIG. 7, the sampling order matches the memory address. In the figure, x indicates that unused data is written. Similar to the above-mentioned embodiments, the same alphabet in each channel is the data to be added. Read out
By setting the address to 5 for ch1 and to 4 for ch2 and starting reading all channels simultaneously from t = 6, delay of all channels can be realized. Here, when performing variable aperture, for example, ch1 is t
Assuming that the data is used from = 7, the data of the unused aperture can be set to 0 by setting the address to 7 and giving the read pulse from t = 8. A variable aperture can be realized by this operation.

It is needless to say that the above embodiment shows an example of the present invention, and the present invention should not be limited to this. For example, the configuration shown in FIG. 7 can also be realized by not applying the sampling clock of the AD converter as in the above.

[0019]

As described above in detail, according to the present invention, it is possible to realize a wave receiving and phasing circuit capable of reducing noise in a variable aperture in digital phasing. Is. More specifically, after the ultrasonic wave reception signal is digitally converted, the multiplication data of the channel located in the unused aperture is set to 0, the latch output is set to 0, or the writing / writing to the memory is performed.
The output of the memory is set to 0 by controlling the read clock or the sample clock of the AD converter.
Therefore, it is possible to output a 0 level signal without noise.

[Brief description of drawings]

FIG. 1 is a diagram illustrating a configuration example including a weight multiplication circuit according to a first embodiment.

FIG. 2 is a diagram showing a configuration example of performing phase rotation using a complex signal according to a second embodiment.

FIG. 3 is a diagram showing a configuration example of multiplying and interpolating a coefficient according to a third embodiment.

FIG. 4 is a diagram illustrating a configuration example for performing frequency shift according to a fourth embodiment.

FIG. 5 is a diagram showing a configuration example having a latch according to a fifth embodiment.

FIG. 6 is a diagram showing a configuration example realized by a FIFO according to a sixth embodiment.

FIG. 7 is a diagram showing a configuration example realized by a RAM according to a seventh embodiment.

FIG. 8 is a diagram showing a conventional example.

[Explanation of symbols] 1 AD converter 2 memory 3 Delay processing circuit 4 adder 5 Signal processing circuit 6 oscillators

Continuation of the front page (56) Reference JP-A-57-134146 (JP, A) JP-A-60-106441 (JP, A) JP-A-61-262657 (JP, A) JP-A-63-216547 (JP , A) JP 63-222748 (JP, A) JP 64-68240 (JP, A) JP 2-26548 (JP, A) JP 3-103787 (JP, A) JP 5-15533 (JP, A) JP-A-5-184568 (JP, A) Actual development Sho 58-69276 (JP, U) (58) Fields investigated (Int.Cl. ⁷ , DB name) A61B 8/00

Claims (5)

(57) [Claims] 1. A means for controlling the phase of an array of ultrasonic transducers to transmit and receive an ultrasonic beam and converting a received signal from each of the ultrasonic transducers into a digital signal to give a delay. And a means for shifting the frequency by multiplying the received signal by a reference wave to shift the frequency, and in the wave receiving and phasing circuit of an ultrasonic device for obtaining a tomographic image of a subject, the amplitude of the reference wave of each channel is adjusted to Depending on the size, the amplitude of the reference wave of the channel not used for the caliber is set to zero, and the received signal of the channel not used for the caliber is not connected so that the channel not used for the caliber is not substantially connected in the wave phasing circuit. Is set to zero and is added to the output signals of the other channels used for the aperture to change the size of the aperture used according to the focus depth. 2. A means for controlling the phase of arrayed ultrasonic transducers to transmit and receive ultrasonic beams, sampling the received signals from each of the ultrasonic transducers, converting them into digital signals and giving a delay. And an interpolation calculation unit that obtains a delay amount smaller than the sampling interval of the received signal by interpolation by interpolation calculation, and in each of the reception phaser circuit of the ultrasonic device that obtains a tomographic image of the subject, each channel By changing the multiplication coefficient of the interpolation calculation means in accordance with the focus depth,
The multiplication coefficient of the interpolation calculation means of the channel not used for the aperture is set to zero, so that the channels not used for the aperture are not substantially connected in the wave receiving and phasing circuit, the reception signal of the channel not used for the aperture is set to zero, By adding with the output signals of other channels used for the caliber,
A receiving and phasing circuit for an ultrasonic device, characterized in that a size of an aperture used is changed according to a focus depth. 3. The phase of ultrasonic transducers arranged is controlled to transmit and receive ultrasonic beams, and the received signals from each of the ultrasonic transducers are subjected to complex sampling to be converted into digital signals for delay. In the wave receiving and phasing circuit of the ultrasonic device, which has a means for giving and a phase matching means for performing phase matching by multiplying the phase rotation data, the phase matching means of each channel By changing the amplitude of the phase rotation data according to the focus depth, the amplitude of the phase rotation data of the phase matching means of the channel not used for the aperture is set to zero, and the channel not used for the aperture is substantially connected in the wave rectifying circuit. Therefore, the received signals of the channels not used for the aperture are set to zero and added to the output signals of the other channels used for the aperture, depending on the focus depth. Reception phasing circuit of the ultrasonic apparatus characterized by changing the size of the aperture to use. 4. The phase of the arrayed ultrasonic transducers is controlled to transmit and receive ultrasonic beams, the received signals from each of the ultrasonic transducers are converted into digital signals, and the signals are written into and read from a memory. By means of providing a delay by
In the wave phasing circuit of the ultrasonic device that obtains a tomographic image of the subject, by not applying the write pulse or the read pulse of each of the memories, the wave reception signal of the channel not used for the aperture is set to zero and used for the aperture. A receiving and phasing circuit of an ultrasonic device, characterized in that the size of the aperture to be used is changed according to the focus depth by adding the output signals of other channels. 5. controlling the phase of the arrayed ultrasonic transducer of the ultrasonic beam transmitted and received waves, the the received signal from each of the ultrasonic transducers and converted into a digital signal by the AD converter delay In the wave receiving and phasing circuit of the ultrasonic device, which has a means for giving a tomographic image of the subject, the sample clock of the AD converter is controlled, and the sampling clock of each of the AD converters is not given An ultrasonic device characterized in that the size of the aperture to be used is changed according to the focus depth by making the received signal of the unused channel zero and adding it to the output signals of the other channels used for the aperture. Receiving wave phasing circuit.