JP2002336249A - Ultrasonic reception beam-shaping device using delay element with multistage structure - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a beam-shaping device with a multistage structure capable of reducing size of a delay memory. SOLUTION: This device includes plural E-FIFOs 14a1-14d4, G-FIFOs 20a-20d, M-FIFOs 28a and 28b, and L-FIFO 32, applying multistage delay for shaping N reception beams to M-channel data samples supplied from M transducers, adding up the delayed data samples to generate N middle outputs; and adders 24a, 24b, 24c and 24d adding up the middle outputs to output N pieces of reception beam data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ultrasonic imaging apparatus using a digital beam focusing technique,
The present invention relates to a receiving beam forming apparatus having a multi-stage delay element and processing a plurality of scanning lines or beams.

[0002]

2. Description of the Related Art As is well known, an ultrasound imaging system using an array of transducers includes a number of transducers in a phased, convex or linear array. Such a system comprises a plurality of channels each having a transmitter and a receiver connected to a corresponding transducer. The transmitter transmits an ultrasonic pulse to a target such as a human body. In order to focus the ultrasound energy so transmitted on a particular portion of the target, a sequential time delay is applied to the pulses. The amount of time delay for each pulse is determined so that each transmission pulse reaches the target point at the same time. These pulses pass through different materials / mediums and are focused on the target, and the pulses reflected from the material / media
It passes through the medium again and returns to the transducer row.

Since the distances from the target to the respective array elements are different from each other, the ultrasonic energy reflected from the target reaches the respective array elements at different times. The receive beamformer amplifies the signal received from each array element, time-delays the amplified signal, and sums all the delayed signals. In this case, the delay value for each delay element is determined such that the receive scan line is focused at a predetermined point. Also, the delay value for each delay element changes constantly so that the focus point advances in the radial direction.

An ultrasound image is formed by scanning a desired area in the body with a transmission scan line and processing signals / data reflected from the scan line. In this case, it is important to increase the frame rate in order to obtain a high-quality video. The frame rate is determined by the number of scanning lines used for imaging, the frequency of ultrasonic waves, and the depth of a region where an image is to be formed. A method for improving the frame rate is a multi-beam focusing technique in which ultrasonic pulses are transmitted to form a large number of scan lines or beams simultaneously.

In a multiple beam forming apparatus, different delay amounts are applied to each channel and each beam.
There is the disadvantage of increasing the complexity of the system compared to the case of a single beam. In particular, the capacity of a memory element used as a delay element is greatly increased. The required capacity of the memory element in the conventional beam forming apparatus increases in proportion to the number of channels, the maximum delay, and the number of beams formed after one transmission. For example, for a system with 64 channels, quad beams, a maximum delay of 1000 system clock periods, and each data is represented by 10 bits, a considerable memory space corresponding to 64 × 4 × 1000 × 10 Is required.

[0006]

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a beam forming apparatus having a novel structure capable of reducing the size of a delay memory.

Another object of the present invention is to provide an ultrasonic imaging apparatus of a multi-focusing system for focusing a plurality of reception scanning lines from a reflection signal of an ultrasonic signal which forms one transmission scanning line, and comprising a plurality of reception scanning lines. It is an object of the present invention to provide a beam forming apparatus for generating time-multiplexed data for a line.

[0008]

According to a preferred embodiment of the present invention, there is provided an ultrasonic receive beamforming apparatus for processing signals received from an array of ultrasonic transducers, comprising: And M is a positive integer less than the number of transducers, each adding a delay to shape the N receive beams for the M channel data samples provided by the M transducers, and A plurality of beamforming means for summing the delayed data samples to generate N intermediate outputs, and summing the intermediate outputs from the plurality of beamforming means to represent the N received beams. Summing means for outputting data, wherein the plurality of beamforming means adds a first delay to the data samples of the M channel, and Generating another and each receive beam-delayed data, first adding the channel-by-channel delay element number previously determined, for at least two channels of said delayed data from the channel by a delay element
An ultrasonic receiving beam forming apparatus, comprising: an adder; and a multi-channel delay element that adds a second delay to an output from the first adder.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a schematic block diagram of a four-channel beamforming apparatus according to a preferred embodiment of the present invention, which simultaneously processes data samples received from a four-channel ultrasonic transducer array.

The beamforming apparatus shown in FIG. 1 applies a coarse time delay to each channel data sample in four different stages, filters and time-multiplexes each time-delayed channel data, and time-multiplexes each of the multiplexed data. The channel data is multiplied by an apodization factor obtained from a predetermined apodization curve, and the resultant data is summed to generate an intermediate output. Summing the intermediate outputs from multiple beamformers produces a time-multiplexed final output representing up to four focused beams, with each time gap in the time-multiplexed output data corresponding to each received beam. I do. In an ultrasonic imaging apparatus that generates one reception scan line or beam by combining data from 64 channels, 16 beam forming apparatuses as shown in FIG. 1 are required.

Although the beamforming device can simultaneously provide intermediate outputs for shaping up to four receive beams, the number of beams formed at one time can vary, for example, depending on the center frequency of the ultrasound signal. .

The time delays generated by the beamformer include coarse delays and fine delays. The coarse delay is a delay corresponding to an integral multiple of the system clock cycle, and as shown in FIG. 1, the E_FIFOs 14a1 to 14d4, G_F
IFOs 20a to 20d, M_FIFOs 28a and 28
b, and a first-in first-out (FIFO) register divided into four stages of L_FIFO 32. Each register or delay element performs data delay by controlling the time during which read data is output. The fine delay smaller than the system clock period is implemented in each channel by finite impulse response (FIR) filter and multiplexer (MUX) blocks 18a to 18d as shown in FIG. In each channel, the apodization for adjusting the size of the data sample is performed by multipliers 24a to 24a.
d and the apodization generators 22a to 22d. The summation is performed by four adders 26a, 26b, 30 and 34 in three different stages.

Referring to FIG. 1, data from each transducer element (not shown) or each channel is input to analog-to-digital (A / D) converters 10a to 10d and sampled. Each A / D converter 10a to 10d
Are supplied to the corresponding input buffers, i.e., I_FIFOs 12a to 12d, and time-delayed. That is, the coarse delay for the first channel input is provided by a series of FIFOs 14a, 20a, 28a and 32, and the coarse delay for the second channel input is a series of F
FIFOs 14b, 20b, 28a and 32, and the coarse delay for the third channel input is a series of FIFOs.
O14c, 20c, 28b and 32, and the coarse delay for the fourth channel input is a series of FIFOs 14
d, 20d, 28b and 32. Also,
The fine delay for each channel input is performed by the corresponding FIR filter & MUX 18a-18d.

In each channel, each I_FIFO1
2a to 12d are E_FIFOs having four E_FIFOs
14a1 to 14a4, 14b1 to 14b4, 14c1
14c4, 14d1 to 14d4 are respectively connected in parallel. For example, sample data from the first channel is E_
The four E_FIFOs 0 to 3 in the FIFO 14a1 are simultaneously recorded in the entirety. These four E_FIFO0
3 respectively performs a time delay corresponding to each reception beam and generates each output delayed at a different time. Four E_
The delay output from FIFO0 to FIFO3 is a multiplexer (FIG. 3)
) And filtered by an FIR filter, thereby performing a fine delay on the sample data. Hereinafter, time multiplexing and filtering will be described in more detail with reference to FIGS.

In each channel, the filtered and time-multiplexed data is passed through a second stage G_FIFO 20
a to 20d. These G_FIFOs 20a
20d performs a second coarse time delay. After that, each G_
The output data from the FIFOs 20a to 20d are supplied to corresponding multipliers 24a to 24d and an apodization generator 22.
apodized by a to 22d. Specifically, each of the multipliers 24a to 24d has a corresponding G_F
The outputs from the IFOs 20a to 20d are multiplied by the corresponding apodization coefficients obtained from predetermined apodization curves in the apodization generators 22a to 22d. Here, each of the apodization generators 22a to 22d may include a memory (not shown) for storing the apodization curve.

Two adjacent channels (multiplier 24a)
And 24b and the outputs from multipliers 24c and 24d) are added in adders 26a and 26b, respectively. The added data is stored in the M_FIFOs 28a and 28b, respectively. These M_FIFOs 28a and 28b perform a third coarse time delay on the input data. Then, M_
The time-delayed data from the FIFOs 28 a and 28 b are added together in the adder 30 and stored in the L_FIFO 32. The L_FIFO 32 performs a fourth coarse time delay on the input data from the adder 30.

The reasons for applying the coarse time delay in four different stages are as follows. The difference in delay applied to data samples from multiple channels to shape multiple beams may vary with distance between channels and / or between beams. Specifically, the difference in delay between two adjacent channels and / or between beams is smaller than the difference between non-adjacent channels. Therefore, E_F for performing the first coarse delay
IFOs 14a1-14d4 handle the maximum delay difference between the four beams in each corresponding channel. Each of the G_FIFOs 20a to 20d performing the second coarse delay processes a maximum delay difference between two adjacent channels not processed in the first stage. M_FIFO 28 for performing third coarse delay
a and 28b each handle the delay difference between four adjacent channels that were not processed in the first and second stages.
The L_FIFO 32 that performs the fourth coarse delay processes a delay difference between channels processed by another beam forming apparatus.

As described above, since the delay sample data from the two channels is added by the adders 26a and 26b, two M_FIFOs 28a are provided in the third stage.
And 28b only are required. Similarly, since the delay sample data from the four channels is added by the adder 30, only one L_FIFO 32 is required in the fourth stage. Therefore, by arranging the delay elements and the adders in a hierarchical structure as shown in FIG. 1, the size of the memory required to obtain the focusing delay can be greatly reduced.

In one embodiment of the present invention, E_FIF
The maximum time delays applied by O, G_FIFO, M_FIFO and L_FIFO are 64, 256, and 25, respectively.
6 and 1024 clock periods. That is, L_FIF
By setting the time delay due to O to be generally larger than the time delay due to other FIFOs, the size of the memory can be reduced as much as possible.

As shown in FIG. 1, the summation process is performed in three different stages. Adder 26 in first stage
a sums the delayed sample data output from the upper two channels (ie, channel 0 and channel 1),
The adder 26b in the first stage sums the delayed sample data output from the lower two channels (that is, channel 2 and channel 3). The adder 30 in the second stage sums the delayed outputs from the adders 26a and 26b. The adder 34 in the third stage includes a number of beam forming devices.
The intermediate outputs from (only one is shown in FIG. 1) are summed to produce a final result representing up to four receive beams.

FIG. 2 shows E_F according to a preferred embodiment of the present invention.
5 is a diagram for explaining an operation of the IFO. In FIG. 2, _{D i} is a data supplied from each channel is written into each one by 1 E_FIFO0~E_FIFO3. As shown in FIG. 2, the write pointer (Wr_Ptr) indicating the data write bit position is set to all E_FIFOs.
It is located at the same place above, and moves one bit at a time for each data write. Thus, sample data from the four channels is written at the same time. However, the time to be input to the FIR filter & MUX registers subsequent stages D _i written in each E_FIFO is read (described later with reference to FIG. 3) each beam (or, the E
_FIFO). As shown in FIG. 2, the read pointer (Rd_Ptr) indicating the data read position can specify a different position.

In FIG. 2, in the case of E_FIFO0,
The data is read out 5 clock cycles after being written, and in the case of E_FIFO2, it is read out 3 clock cycles and different delays are applied to the two beams. As described above, the amount of delay applied to each channel and each beam is adjusted by the difference in position between the write pointer and the read pointer. The location of these pointers is shown in FIG.
Adjusted by the FDCU 16 inside. Specifically, the amount of delay is adjusted by moving the read pointer one memory location per clock cycle based on the delay curve.

FIG. 3 is a diagram showing the FIR & MUX 18 in FIG. 1 in detail. As shown in FIG. 3, the shift register unit 110 includes four sets of 16-tap registers. Each set of registers stores 16 consecutive data read from the corresponding E_FIFO. In one embodiment of the present invention, each data from the E_FIFO includes 10 bits, and each register can store 10 bits.

These 16 consecutive data are represented by Cij
Is filtered by the 16-tap filter indicated by. The coefficients of each filter are 8: 1 MUX 120, 12
2, 124, a predetermined set of eight coefficients (C
i0 to Ci7). In one embodiment of the present invention, the filter coefficient Cij is predetermined by a separate filter coefficient bank (not shown), and the FIR & MUX unit 18
Supplied to The coefficient selection signal is 8: 1 MUX120
To 124 are used to control to select any one of the eight filter coefficient sets. This coefficient selection signal is determined by the fine delay amount applied in the FIR & MUX unit 18.

The filtering of 16 consecutive data is performed by setting one of the 16 tap registers of the four sets in the shift register unit 110 to 4: 1 MUX1.
12, 114, and 116 are selected and performed in a time-multiplexed manner. The beam selection signal is 4: 1 MUX 112, 11
4, 116, and indicates which of the four beams will be processed. Thereafter, the filter coefficients selected by the 8: 1 MUX are 4: 1 MUX 112,
Multiplied by 16 data selected by 114 and 116. Filtering is E_FIFO0, E_FIF
This is performed on data sequentially supplied from O1, E_FIFO2, and E_FIFO3. That is, the filtering is sequentially repeated for each beam.

The shift enable signal in FIG.
When data from the FIFO is input to the 16-tap register, it functions to control the shift of data in the register at a specific clock cycle. In the clock cycle in which the read pointer moves in FIG. 2, the shift enable signal controls each register so that data is shifted in the register. If the read pointer remains for adjustment of the delay value, the shift enable signal is disabled so that data is not shifted in the register. By synchronizing the movement of the read pointer and the movement of the data in the shift register in this manner, the same data is prevented from being redundantly written to the register. This is because if the same data is repeatedly written into the register, an error may occur when obtaining the interpolation data from the corresponding data.

FIG. 4 is a drawing for explaining the function of the FIR filter in FIG. The fine delay is implemented using an interpolation filter. Appropriate selection of FIR filter coefficients
By doing so, a fine delay having a value smaller than the system clock period can be applied to the delay sample data. By applying a fine delay smaller than the system clock period to data samples in this manner, a delay error can be eliminated.

The input waveform shown in FIG. 4 represents data input from the E_FIFO to the register set. FIR in FIG.
The filter is an interpolation filter for finding an intermediate value between sample data in the input waveform. FIG. 4 illustrates the function for a 4-tap interpolation filter for convenience.

Although the preferred embodiments of the present invention have been described above, those skilled in the art will be able to make various modifications without departing from the scope of the present invention.

[0031]

Thus, according to the present invention, a multistage delay element is used, and a part of the delay elements is shared by a plurality of channels, thereby realizing a memory required for realizing the delay element. The size can be reduced. further,
Processing multiple beams in a time multiplexed manner can further reduce overall hardware complexity.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of a 4-channel beamforming apparatus according to a preferred embodiment of the present invention.

FIG. 2 is a diagram illustrating an operation of an E_FIFO according to a preferred embodiment of the present invention;

FIG. 3 is a diagram showing FIR & MUX in FIG. 1 in detail.

FIG. 4 is a diagram for explaining a function of an FIR filter in FIG. 3;

[Explanation of symbols]

 14a1 to 14d4 First-stage delay element 20a to 20d Second-stage delay element 28a, 28b Third-stage delay element 32 Fourth-stage delay element 18a, 18b, 18c, 18d FIR & MUX 26a, 26b, 30, 34 Addition vessel

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Bemho South Korea Seoul Tokbyulsi Songpak Zamsil 6-dong Zangmi apartment 19-dong 808-ho F-term (reference) 2G047 BA03 CA01 DB02 EA14 GB02 GF17 GF20 GF22 GG09 GG17 GG34 4C301 AA02 BB23 EE15 GB02 HH33 HH37 HH38 HH39 HH43 JB02 JB29 JB35 5J083 AA02 AB17 AC28 AC31 AD13 AE10 BA01 BC02 BE56 BE57

Claims (6)

[Claims] An ultrasonic receive beamforming apparatus for processing signals received from an array of ultrasonic transducers, wherein each of N and M is a positive integer less than the number of transducers and is supplied from M transducers. A plurality of beams that add a delay to shape the N receive beams for the M channel data samples to be generated and sum the delayed data samples for the M channel to generate N intermediate outputs. Shaping means, and summing means for summing the intermediate outputs from the plurality of beam shaping means and outputting data representing the N received beams, wherein the plurality of beam shaping means comprises A predetermined number of channels for adding a first delay to the data samples to generate delay data for each channel and each receive beam. A delay element for each channel; a first adder for adding the delay data from the delay element for each channel to at least two channels; and a multi-channel for adding a second delay to an output from the first adder. An ultrasonic receiving beam forming apparatus, comprising: a delay element. 2. Each of said beam forming means supplies said N intermediate outputs for said N received beams in a time multiplexed manner, and said summing means time multiplexes data representing said N received beams. 2. The ultrasonic receiving beam forming apparatus according to claim 1, wherein the output is performed by a conversion method. 3. The delay element for each channel includes a coarse delay element for adding a delay corresponding to an integral multiple of a system clock cycle, and a fine delay element for adding a delay smaller than the system clock cycle. Item 2. An ultrasonic receiving beam forming apparatus according to Item 1. 4. The apparatus according to claim 3, wherein said fine delay element comprises a plurality of interpolation filters, each of said interpolation filters using a set of data samples from a channel to determine interpolated data between corresponding data samples. An ultrasonic receiving beam forming apparatus as described in the above. 5. The fine delay element comprises: M sets of shift registers, each set having L shift registers storing L consecutive data samples from each channel; and M sets of the M sets. Based on the M: 1 multiplexing means for selecting one of them and supplying the L data stored in the selected set, and the delay value added by the fine delay element, each set is Selecting means for selecting any one of a plurality of predetermined filter coefficient sets having L filter coefficients; and selecting the L data samples supplied from the M: 1 multiplexing means. 4. An ultrasonic receiving beam forming apparatus according to claim 3, further comprising means for multiplying said L filter coefficients from said means and summing up the L multiplication results. 6. A coarse delay element comprising: N first-in first-out storage means for each of N channels each storing a data sample to be used in shaping each beam; and data of the N first-in first-out storage means in each channel. Means for controlling the write pointers, and means for independently controlling the data read pointers of the N first-in, first-out storage means for each channel, wherein the data stored in each of the first-in, first-out storage means is determined by a coarse delay amount. 4. The ultrasonic receiving beam forming apparatus according to claim 3, wherein the reading is performed at the determined time.