JP3476212B2 - Liquid crystal display - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device in which a liquid crystal layer is held between a pair of substrates, and more particularly, a switch element for selectively applying a drive voltage to each display pixel is provided. The present invention relates to a liquid crystal display device.

[0002]

2. Description of the Related Art A liquid crystal display device in which a plurality of display pixels are arranged in a matrix and a switch element for selectively applying a video signal voltage to each display pixel is provided is lightweight, has low power consumption, and A good display image without crosstalk can be obtained.

In recent years, attention has been paid to a liquid crystal display device in which a drive circuit is integrally formed on the same substrate in order to eliminate the inconvenience of connection between the liquid crystal panel and the drive circuit due to the finer pitch of each display pixel. Are gathering.

A major technical problem for a liquid crystal display device is how to secure a high aperture ratio in response to such a fine pitch of each display pixel. A liquid crystal display device capable of securing a high aperture ratio even with such a fine pitch is, for example, “SID 90 DIGEST P.315-P.318;
New Technologies for Compact TFT LCDs with High-Ap
erture Ratio ”.

A brief description will be given below with reference to FIG. 5 showing an equivalent circuit diagram and FIG. 6 showing a schematic front view. This liquid crystal display device (901) comprises a liquid crystal layer (803) held between a matrix array substrate (not shown) integrally formed with a drive circuit section and a counter substrate (not shown). There is.

The matrix array substrate comprises a plurality of scanning lines (713a), (71) on an insulating substrate (not shown) as shown in FIG.
3b) and a plurality of signal lines (711) are arranged in a matrix, and pixel electrodes are formed at the respective intersections through thin film transistors (hereinafter abbreviated as TFT) (721a) and (721b) as switch elements. (751a) and (751b) are placed.

This liquid crystal display device (901) has two scanning lines (7
13a) and (713b) are closely arranged as one set. Also,
A storage capacitor line (821) common to the pixel electrodes (751a) and (751b) adjacent to each other is provided along the signal line (711) without passing through the scanning lines (713a) and (713b).

By adopting such a structure, firstly, the number of auxiliary capacitance lines (821) can be reduced to about half that of the conventional one, and secondly, the scanning lines (713a), (713b) of one unit closely arranged. ) Connected to 1 unit TFT (721a), (721b) and signal line (711)
The contact hole (73
0) The number can be reduced to about half.

[0009]

By the way, a dot-sequential drive, that is, a liquid crystal display device (901) for sequentially applying a video signal to each signal line (711) or for each block composed of a plurality of signal lines (711). In order to hold the video signal applied to each signal line (711) for a predetermined period such as one horizontal scanning period, it is necessary to form a signal potential holding capacitor (Cv) connected to each signal line (711). There is.

Conventional liquid crystal display device (901) as described above
In, the pixel potential holding capacitance (Cv) formed inside the display area is the intersection of the signal line (711) and the scanning lines (713a) and (713b), the signal line (711) and the auxiliary dose line (Cv). 821) Only a small intersection with it. Therefore, in such a liquid crystal display device (901), it is necessary to form a sufficient signal potential holding capacitance (Cv) around the display area.

However, in order to form a sufficient signal potential holding capacitor (Cv) around the display area, a large electrode area for the signal potential holding capacitor is required, which leads to an increase in size of the device.

[0012] Such a thing becomes more remarkable as the definition of the liquid crystal display device (901) becomes higher. That is, although the distance between the signal lines (711) becomes narrower as the pixel pitch becomes smaller, the required signal potential holding capacitance (Cv) is about the same as the conventional one. Therefore, each electrode for holding the signal potential is inevitably formed in the direction along the signal line (711), which further increases the size of the device.

When the pair of electrode substrates is sealed with a sealant around the display area of the liquid crystal display device (901), a glass fiber or the like contained in the sealant is used to store the signal potential holding capacitor. The electrodes may be destroyed.

The present invention has been made in view of the above technical problems, and an object of the present invention is to provide a liquid crystal display device having a sufficient signal potential holding capacitance without impairing the aperture ratio of the display region. I am trying.

[0015]

A liquid crystal display device according to claim 1, wherein a plurality of thin film transistors having a source region and a drain region, and an active region sandwiched between the source region and the drain region, and a signal are provided. A plurality of signal lines for supplying a video signal from a line driving circuit to the drain regions of the thin film transistors, and a pair of pixel electrodes arranged on both sides of the signal lines and connected to the source regions of the thin film transistors. And an auxiliary capacitance line arranged between the pair of pixel electrodes, and a signal holding insulating film laminated between the auxiliary capacitance line and the signal line.

According to a second aspect of the present invention, in the liquid crystal display device according to the first aspect, the thin film transistor includes a source extension region electrically connected to the source region, and at least a part of the source extension region. A first pixel capacitance insulating film is disposed on the surface, and the source extension region is covered with the auxiliary capacitance line through the first pixel capacitance insulating film.

According to a third aspect of the present invention, in the liquid crystal display device according to the second aspect, the source extension region includes an upper region and a side region, and between the upper region and the auxiliary capacitance line, and It is characterized in that a pixel potential holding capacitance is formed between the side region and the auxiliary capacitance line via the first pixel capacitance insulating film.

According to a fourth aspect of the present invention, in the liquid crystal display device according to the first aspect, a second pixel holding insulating film is disposed on at least a part of the surface of the auxiliary capacitance line,
It is characterized in that a region overlapping with the pixel electrode via the second pixel holding insulating film is provided.

According to a fifth aspect of the present invention, in the liquid crystal display device according to the first aspect, each of the thin film transistors is a gate insulating film disposed on the active region,
It is characterized in that it includes a gate electrode connected to a scanning line substantially orthogonal to the signal line through the gate insulating film, and the auxiliary capacitance line extends in a direction substantially parallel to the scanning line.

According to a sixth aspect of the present invention, in the liquid crystal display device according to the first aspect, each of the thin film transistors has a gate insulating film disposed on the active region,
The gate electrode includes a gate electrode connected to a scanning line that is substantially orthogonal to the signal line through the gate insulating film, and two scanning lines are arranged in close proximity to each other and are adjacent to each other through one scanning line. It is characterized in that each of the pixel electrodes is arranged.

According to a seventh aspect of the present invention, in the liquid crystal display device according to the sixth aspect, the drains of the pair of thin film transistors are connected to the pixel electrodes adjacent to each other through one set of the scanning lines. The region is commonly connected to the signal line via a connecting portion.

Further, a liquid crystal display device according to claim 8 is a plurality of thin film transistors having a source region and a drain region, and an active region sandwiched between the source region and the drain region, and a signal line. A plurality of signal lines for supplying the video signal from the driving circuit to the drain region of each of the thin film transistors, and a pair of pixel electrodes arranged on both sides of the signal line so as to be connected to the source regions of the respective thin film transistors. A source extension region extending from the source region between the pair of pixel electrodes, a pixel capacitance insulating film disposed on a surface of the source extension region, and the source extension region via the pixel capacitance insulating film. It is characterized in that it is provided with an auxiliary capacitance line for covering and a signal holding insulating film laminated between the auxiliary capacitance line and the signal line.

[0023]

As described above, according to the liquid crystal display device of the present invention, between the pair of pixel electrodes arranged on both sides of the signal line,
Since the signal line and the auxiliary capacitance line are arranged via the first signal holding insulating film, a sufficiently large signal holding capacitance (Cv) can be formed inside the display region.

By appropriately selecting the signal line width or the film thickness or material of the first signal holding insulating film, it is not necessary to form the signal potential holding capacitor (Cv) outside the display area, and It is also possible to form with only the signal potential holding capacitance (Cv).

As a result, the problem of destruction of the signal potential holding capacity (Cv) by the sealant or the problem of increasing the size of the device can be solved at once. Moreover, as described above, since the signal potential holding capacitance (Cv) is formed by making good use of the region between the pair of pixel electrodes that does not contribute to the display, the aperture ratio is not significantly reduced as compared with the conventional case.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A liquid crystal display device (5) used in a projection type high-definition TV for dot-sequential driving according to an embodiment of the present invention
Taking 01) as an example, a detailed description will be given with reference to the drawings. This liquid crystal display device (501) includes an alignment film (27) made of polyimide between a pair of electrode substrates (101), (301) as shown in FIGS.
A liquid crystal layer (401) is held via 1) and (331).

As shown in FIG. 1, the first electrode substrate (101) includes a display area (281), a signal line driving circuit (291) formed around the display area (281), and a scanning line driving circuit. (293),
A counter electrode drive circuit (295). Although not shown, the signal line drive circuit (291) described above is composed of a shift register and a sample hold circuit for sampling and holding a video signal input based on the output of the shift register. Reference numeral (293) is composed of a shift register that sequentially transfers the scanning signal.

In the display area (281), the signal line drive circuit (29
1) and a plurality of signal lines Xi (i = 1,2, ..., m) (111) which are connected substantially parallel to each other and are spaced apart by a predetermined distance, and which are connected to the scanning line driving circuit (293) 2 A plurality of scanning lines Yj (j = 1, 2, ..., N) (113), which are arranged close to each other as one set and are arranged substantially orthogonal to the signal line (111) and substantially parallel to each other, are arranged. .

The TF arranged at the intersection of the scanning line (113a) of one set of scanning lines (113) and the signal line (111).
The first pixel electrode (151a) made of ITO (Indium-Tin-Oxide) is connected to the other scanning line (113b) and the signal line through the T (121a).
The second pixel electrode (151b) made of ITO is arranged via the TFT (121b) arranged at the intersection with (111).

Further, between the first and second pixel electrodes (151a) and (151b) adjacent to each other along the signal line (111) without interposing a pair of scanning lines (113a) and (113b), 1, 2 pixel electrodes (151
In order to form a pixel potential holding capacitor (Cs) electrically connected in parallel to a) and (151b), the auxiliary capacitance line (211), which is connected to a predetermined potential and is integrally formed, is connected to the scanning line (113). ) Is arranged substantially parallel to.

As shown in FIG. 3, the second electrode substrate (301) is made of a metal such as chromium (Cr) extending on the transparent quartz substrate (303) substantially parallel to the scanning lines (113a) and (113b). A striped light-shielding layer (311) is formed so as to shield the scanning lines (113a), (113b) and the TFTs (121a), (121b) from each other. The second electrode substrate (301) is provided with a counter electrode (321) made of ITO and an alignment film (331) arranged thereon.

The first electrode substrate (101) and the second electrode substrate (301) are controlled at a predetermined interval via a spacer (not shown), and the display area (281) and the driving circuit (301) are controlled. 291), (2
The liquid crystal layer (401) is held by a sealant (not shown) provided between the liquid crystal layers (93) and (295).

Next, FIG. 2 showing a schematic front view of the first electrode substrate (101) of the liquid crystal display device (501), cut along the line AA 'and the line BB' in FIG. The liquid crystal display device 501 will be described in more detail with reference to the schematic sectional view and the schematic sectional view taken along the line CC ′. (TFT part) First, the TFT of this liquid crystal display device (501)
The parts (121a) and (121b) will be described in detail.

First electrode substrate of this liquid crystal display device (501)
(101) is on a transparent quartz substrate (103) as shown in FIG.
Island-shaped polycrystalline silicon film with a thickness of 1300 angstroms
It is equipped with (120).

Each polycrystalline silicon film (120) has a first pixel electrode (151) adjacent to it via a pair of scanning lines (113a), (113b).
a) and a pair of TFTs (121a) and (121b) connected to the second pixel electrode (151b), respectively. Therefore, as shown in FIG. 3, source regions (123a) and (123b) and drains Area (125a),
(125b), source regions (123a), (123b) and drain region (12
5a) and (125b) are sandwiched between the active regions (127a) and (127b), and the drain regions (125a) and (125b) are connected to each other by a drain connection region (129).

The active region (1) of this polycrystalline silicon film (120)
27a) and (127b) on the polycrystalline silicon film (120), respectively.
The gate insulating films (141a) and (141b) having a thickness of 1000 angstroms are formed by thermal oxidation. The gate electrodes (115a) and (115b) extended from the scanning lines (113a) and (113b) are arranged on the gate insulating film (141). The gate electrodes (115a) and (115b) are made of polysilicon (p-Si) having a thickness of 1500 angstroms doped with impurities and WSi having a thickness of 2500 angstroms, similarly to the scanning lines (113a) and (113b). _It consists of a two-layer structure with _X.

A first interlayer insulating film (161) and a signal line (111) are sequentially arranged on this. The drain connection region (129) of the polycrystalline silicon film (120) and the signal line (111) are connected via the contact hole (130).

A second interlayer insulating film (171) is arranged on the signal line (111), and pixel electrodes (151a) and (151b) made of ITO are arranged on the second interlayer insulating film (171). Then, the pixel electrodes (151a) and (151b) and the source regions (123a) and (123b) of the polycrystalline silicon film (120) are connected to the contact holes (1
60) electrically connected via.

As described above, in the present embodiment, a pair of scanning lines (113a) and (113b) are connected to the adjacent first and second pixel electrodes (151a) and (151b), respectively. Set of TFTs
(121a) and (121b) are formed of a common polycrystalline silicon film (120), and a set of TFTs (121a) and (121b)
Are connected to the signal line (111) through a common contact hole (130) via the drain connection region (129).

With such a structure, the TFTs (121a) and (121b) formed in the display area (281) and the signal line are formed.
Contact hole (1) for electrical connection with (111)
The number of 30) can be reduced to half of the number of TFTs (121a) and (121b), and thus the aperture ratio can be improved.

Further, in this embodiment, as shown in FIG. 2, the active regions (127a), (127b) of the polycrystalline silicon film (120).
The signal line (111) wider than that of the first is the first interlayer insulating film (161).
It is arranged on the active regions (127a) and (127b) so as to shield the active regions (127a) and (127b) from light through.

Therefore, the liquid crystal layer (401) and the second electrode substrate (3
(01) The TFT (121a), (121b) is provided with a light-shielding layer or the like which prevents the reflected light at the interface with (01) from being applied to the TFT (121a), (121b).
Since it is not necessary to separately provide it above, light leakage of the TFTs (121a) and (121b) can be prevented, and a good display image can be obtained. (Pixel potential holding capacitor section) The above-mentioned polycrystalline silicon film (12
(0) is extended so as to surround the pixel electrodes (151a) and (151b) connected to the source regions (123a) and (123b) in opposite directions from the source regions (123a) and (123b). Source extension regions (131a) and (131b) are provided.

Gate insulating layers are provided in the upper regions (135a) and (135b) of the source extension regions (131a) and (131b) and the side regions (137a) and (137b) of the polycrystalline silicon film (120). Membrane (1
Similar to 41a) and (141b), first pixel capacitance insulating films (143a) and (143b) formed by thermally oxidizing the polycrystalline silicon film (120) are arranged.

The auxiliary capacitance line (211) and the first pixel electrode (151a) adjacent to each other in the signal line (111) direction are provided without interposing a pair of scanning lines (113a) and (113b). 2 pixel electrodes (1
51b) and the source extension regions (131a), (131b) via the first pixel capacitance insulating films (143a), (143b).
It is arranged so as to cover b) by extending in a stripe shape in a direction substantially parallel to the scanning line (113).

Further, the auxiliary capacitance line (211) and the first pixel electrode (151a) which are adjacently arranged in the signal line (111) direction without interposing a pair of scanning lines (113a) and (113b). Second pixel electrode
Source extension regions (131a), (13a)
It has an extension region (213) covering 1b).

The auxiliary capacitance line (211) is a scanning line.
It is made of the same material as (113) and the gate electrodes (115a) and (115b), and is connected to a predetermined potential. In addition, the auxiliary capacitance line (2
11) is a second electrode formed in the same manner as each pixel electrode (151a), (151b) and the above-mentioned first and second interlayer insulating films (161), (171).
It has overlapping regions (221a) and (221b) which partially overlap with each other through the third pixel capacitance insulating films (165) and (175).

By constructing the auxiliary capacitance lines (211) in this way, the number of auxiliary capacitance lines (211) can be reduced to about half the number of scanning lines (113), thereby improving the aperture ratio. Can be made.

The pixel electrodes (151a) and (151b) have upper regions (135a) and (135b) above the source extension regions (131a) and (131b), respectively.
In addition to the first pixel potential holding capacitance (Cst) formed by using the auxiliary capacitance line (211) as the other electrode and the auxiliary capacitance line (211), side regions (137a) of the source extension regions (131a) and (131b) , (137b)
A second pixel potential holding capacitor (Css) formed by using as an electrode and the auxiliary capacitance line (211) as the other electrode is electrically connected in parallel. Further, the pixel electrodes (151a) and (151b) are used as one electrode, and the overlapping regions (221a) and (22) of the auxiliary capacitance line (211) are used.
A third pixel potential holding capacitor (Csp) formed by using 1b) as the other electrode is electrically connected in parallel to each pixel electrode (151a), (151b).

Therefore, the pixel potential holding capacitance (Cs) is sufficiently larger than the area shielded by the auxiliary capacitance line (211).
Can be electrically formed in parallel with each pixel electrode (151a), (151b), and thereby, the adjacent pixel electrodes (151a), (151b) can be formed.
The effect of b) can be prevented.

By the way, as described above, when the source extension regions (131a) and (131b) are integrally formed with the source regions (123a) and (123b) by the polycrystalline silicon film (120), the source extension regions are formed. (131a) and (131b) are also source regions (123a) and (123b)
Similarly to the above, it is necessary to reduce the resistance by implanting impurities. However, since the auxiliary capacitance line (211) is arranged on the source extension regions (131a) and (131b), the source region (123
Similar to a), (123b) or drain regions (125a), (125b), it is difficult to reduce the resistance. Therefore, in this embodiment, after the polycrystalline silicon film (120) is formed, impurities are first implanted to form the source extension regions (131a), (131a).
b) is formed. And the gate insulating film (141a), (141b)
And the first pixel capacitance insulating films (143a), (143b) are formed by thermal oxidation of the polycrystalline silicon film (120) as described above, and then the gate electrodes (115a), (115b) and the auxiliary capacitance lines (211) are formed. )
The gate electrodes (115a), (115b) and the auxiliary capacitance line.
Impurities are implanted again using (211) as a mask, and the source region
(123a), (123b), drain regions (125a), (125b), and source regions (123a), (123b) and drain regions (125a), (12
Active regions (127a) and (127b) sandwiched between 5b) were formed.

When the source extension regions (131a) and (131b) are formed, the impurity implantation amount is 1 × 10 ¹⁷ to 5 × 10 5.
¹⁸ / cm ³ is preferable. The first pixel capacitance insulating film (143
If the doping amount is too large when forming a) and (143b), the film thickness of the active regions (127a) and (127b) of the TFT (121a) and (121b)
It becomes thicker than the film thickness of the upper gate insulating films (141a) and (141b), and it is impossible to obtain a necessary pixel potential holding capacitance (Cs). If the doping amount is too small, it becomes difficult to secure the desired pixel potential holding capacity (Cs).

Therefore, the gate insulating films (141a), (141b) and the first pixel capacitor insulating films (143a), (143b) are simultaneously formed by the CVD method or the like instead of the above-mentioned thermal oxidation. Pixel potential holding capacitor (Cs)
It suffices to inject a sufficient amount of impurities into the portion where the film is to be formed to reduce the resistance, variation in characteristics between elements can be suppressed, and the manufacturing yield can be improved.

As in this embodiment, the source extension region (1
The provision of the auxiliary capacitance line (211) having a sufficient width so as to cover 31a) and (131b) also contributes to the speed reduction of the voltage supply to the auxiliary capacitance line (211). That is, increasing the pixel potential holding capacity (Cs) means increasing the wiring capacity of the auxiliary capacity line (211). Therefore, in order to increase the pixel potential holding capacity (Cs), the auxiliary capacity line
It is necessary to reduce the sheet resistance and wiring resistance in (211). This is especially important when a large number of pixel electrodes (151) are required as in the case of high definition.

Therefore, in this embodiment, polycrystalline silicon doped with phosphorus (P) ions and WSi _x 2 are used.
The resistance of the wiring is also reduced by using the layered auxiliary capacitance line (211).

In this embodiment, for the above reason,
The auxiliary capacitance line (151) is connected to the gate electrodes (115a), (115b), the scanning line
Similar to (113a) and (113b), 1500 angstrom thick polysilicon (p-Si) doped with impurities and 2500
Although it has a two-layer structure with WSi _X having an angstrom thickness, molybdenum (Mo), molybdenum tantalum (Mo
-Ta), tungsten (W), aluminum (Al)
It may be formed of a light-shielding metal such as.

Further, in this embodiment, the auxiliary capacitance line (2
The reason (11) has a two-layer structure of polycrystalline silicon and WSi _x is also for securing the light shielding property. Auxiliary capacitance line (211)
This is because it is not necessary to separately provide a light-shielding layer in the region where the auxiliary capacitance line (211) is arranged by forming the material with a light-shielding material. Therefore, in this embodiment, a pair of scanning lines (113) in which the auxiliary capacitance line (211) is not provided is used.
A light-shielding layer (311) is provided so as to shield only a), (113b) and TFTs (121a), (121b).

Thereby, the degree of freedom of the accuracy of the light shielding layer (311) with respect to the first electrode substrate (101) and the positioning accuracy of the light shielding layer (311) with respect to the first electrode substrate (111) are sufficiently increased. It is also possible to improve productivity.

In this embodiment, each source extension region (131
a) and (131b) are respectively the first pixel capacitance insulating film (143)
Is covered by the auxiliary capacitance line (211). Therefore, the source extension regions (131a), (131b) are connected to the source regions (123a), (123b) by the pixel electrodes (151a), (151b).
b) In addition to the neighboring pixel electrodes (151a) and (151b), even if the overlapping regions (133a) and (133b) partially overlap, the influence of the potential of the neighboring pixel electrodes (151a) and (151b) Can be prevented. Therefore, the degree of freedom of the positional accuracy required for the pixel electrodes (151a) and (151b) can be increased. (Signal Potential Holding Capacitor Section) Next, the signal potential holding capacitor (Cv), which is a characteristic part of this embodiment, will be described with reference to the drawings.

According to this liquid crystal display device (501), as described above, between the pair of first pixel electrodes (151a) arranged adjacent to both sides of the signal line (111) and between the pair of second pixel electrodes. (1
An auxiliary capacitance line (211) having extension regions (213a) and (213b) extended to each of 51b) is arranged. Then, as shown in FIGS. 3 and 4, the auxiliary capacitance line (211) and the signal line (111)
A first signal holding insulating film (163), which is an extension of the first interlayer insulating film (161), is laminated between and.

A conventional liquid crystal display device (901) shown in FIG.
In, the signal potential holding capacitance (Cv) formed in the display area is the width of the signal line (711) and the scanning lines (713a) and (713b), and the width of the signal line (711) and the auxiliary capacitance line (821) ( It is necessary to form a sufficiently large signal potential holding capacitor (Cv) outside the display region because it is between L).

On the other hand, the liquid crystal display device of this embodiment
According to (501), a large signal potential holding capacitance (Cv) with the auxiliary capacitance line (211) including the extension regions (213a) and (213b) as one electrode and the signal line (111) as the other electrode is provided. Each display area (2
81) Can be formed inside.

This signal potential holding capacitance (Cv) is shown in FIGS.
As shown in FIG. 11, the auxiliary capacitance line (211) including extension regions (213a) and (213b) extended between the pair of first pixel electrodes (151a) and between the pair of second pixel electrodes (151b), respectively. ) Is the signal line
Since the region (231) overlapping with (111) is formed sufficiently wide, it can be made large enough to eliminate the need to dispose the signal potential holding capacitor (Cv) in the signal line drive circuit section (291).

Moreover, this signal potential holding capacitance (Cv) is
Since it is formed between the pair of first pixel electrodes (151a) and between the pair of second pixel electrodes (151b), the aperture ratio is not impaired.

As a result, the size of the device can be reduced without impairing the aperture ratio of the display area (281) and without the need to separately form a signal potential holding capacitor (Cv) outside the display area (281). You can

Such a thing works more effectively, especially as the pitch of the pixel electrodes 151 becomes smaller. That is, when the signal potential holding capacitance (Cv) is to be formed outside the display region (281), the pitch of the pixel electrodes (151) becomes small even though the area required to secure the desired capacitance is the same. As the space between each signal line (111) becomes narrower,
Long signal potential holding capacitor (Cv) along each signal line (111)
This is because it has to be formed.

Further, according to this embodiment, since the signal potential holding capacitance (Cv) is formed inside the display region (281), the signal potential holding capacitor (Cv) is provided between the signal line drive circuit (291) and the display region (281). Even if the sealant is arranged, the signal potential holding capacitor portion is not damaged by the filler contained in the sealant, thereby ensuring a high manufacturing yield.

Further, as shown in FIG. 4, the signal line (111) and the pair of first and second pixel electrodes (151a) and (151b) adjacent to each other on both sides of the signal line (111) are disposed below the signal line (111). An extension region (213) of the auxiliary capacitance line (211) is arranged via the first interlayer insulating film (161) and the second interlayer insulating film (171).

Therefore, the signal line (111) and each pixel electrode (151
Even if a) and (151b) are arranged close to each other, they also act as a shield layer so as to suppress the horizontal electric field generated between the signal line (111) and the pixel electrodes (151a) and (151b). ing. This makes it possible to reduce the reverse tilt length of the liquid crystal and the coupling capacitance due to the lateral electric field, and it is possible to secure a good display image. By reducing the lateral electric field in this manner, the pixel electrodes (151a) and (151b) can be arranged sufficiently close to the signal line (111), so that a good display image can be secured as compared with the conventional one. While the liquid crystal display (5
The aperture ratio of 01) can also be improved.

Further, although the TFT (121) of the double gate structure is used in this embodiment, a single gate structure may be used. In the case of the single gate structure, the pixel potential holding capacitance (Cs) can be secured. It goes without saying that the shielding effect is improved and the shielding effect is improved.

In this embodiment, as shown in FIGS. 3 and 4, the signal line (111) is on the first interlayer insulating film (161) and the pixel electrodes (151a) and (151b) are on the second interlayer insulating film (161). Layers were separated on the inter-layer insulation film (171), but this is the signal line (111) and each pixel electrode.
It is needless to say that this is for the purpose of preventing the occurrence of a short circuit defect between (151a) and (151b) and may be formed on the same layer.

As described in detail above, according to the liquid crystal display device (501) of this embodiment, the signal line (111) and the auxiliary capacitance line (211) are included.
A signal potential holding capacitor (Cv) is formed with the overlapping region (231) with the signal. In this way, by forming the signal potential holding capacitor (Cv) in the display area (281) well without reducing the aperture ratio, conventionally, between the display area (281) and the signal line driver circuit (291). The signal potential holding capacitance (C
v) can be formed inside the display area (281), so that the signal potential holding capacitance (Cv) is provided on the signal line driver circuit (291) side.
Therefore, the area of the peripheral circuit portion can be reduced.

Further, according to this embodiment, the source extension regions (131a) and (131b) are the first pixel capacitance insulating films (143a) and (14a).
It is covered by the auxiliary capacitance line (281) via 3b). Therefore, the first pixel potential holding capacitance (formed by using the upper regions (135a), (135b) of the source extension regions (131a), (131b) as one electrode and the auxiliary capacitance line (211) as the other electrode ( Cst) and the side wall regions (137a) and (137b) of the source extension regions (131a) and (131b) as one electrode, the auxiliary capacitance line (211)
A second pixel potential holding capacitor (Css) formed with the other electrode as the other electrode is electrically connected in parallel. Therefore, a sufficiently large pixel potential holding capacitance (Cs) can be obtained without lowering the aperture ratio.

By thus securing a high aperture ratio and a large pixel potential holding capacitance (Cs), undesired potential fluctuations of the pixel electrodes (151a), (151b) can be suppressed,
A good display image can be obtained.

Further, the characteristic feature of this embodiment is that
The source extension regions (131a) and (131b) are covered with the auxiliary capacitance line (211) through the first pixel capacitance insulating film (143), respectively, and the source extension regions (131) are thereby covered.
Even if (131a) and (131b) form an overlapping region that overlaps with an adjacent pixel electrode that is not electrically connected, the adjacent pixel electrode (151
It is possible to prevent the influence of the potentials of a) and (151b), and it is possible to obtain an excellent display image that is not influenced by the adjacent pixel electrodes (151a) and (151b).

According to the above-described liquid crystal display device (501) of the present embodiment, a high aperture ratio of 40% is ensured and the display area (281) is formed despite the fine pixel pitch of 40 μm square. It was possible to form a sufficient signal potential holding capacitance (Cv) of about 7 pF when the interlayer insulating film thickness was 1 μm and the number of pixels in the vertical direction was 1035.

The overall capacitance value of the pixel potential holding capacitance (Cs) is approximately the same as that of the conventional example shown in FIG. It was possible to secure double the pixel potential holding capacity (Cs).

In the present embodiment, the case where the light shielding layer (311) is formed on the counter electrode (211) side is shown.
In consideration of alignment between the pixel electrodes (151a) and (151b) and the pixel electrodes (151a) and (151b), another insulating film may be formed above or below the TFTs (121a) and (121b).

The writing time to the signal line (111) is determined by the product of the signal potential holding capacitance (Cv) and the on resistance of the analog switch in the signal voltage drive circuit (291). The larger the potential holding capacitance (Cv), the better. The value of the signal potential holding capacitance (Cv) needs to be determined in consideration of the leak characteristic due to the off resistance of the analog switch and the write characteristic. For this reason,
When the light shielding layer is formed on the TFTs (121a) and (121b) via the insulating film, the light shielding layer and the signal line (111) are formed by forming the light shielding layer in a substantially stripe shape along the scanning line (113). There is no undesired formation of capacitance due to), and it becomes easy to set the writing time to the signal line (111).

When the light shielding layer is formed on the TFTs (121a), (121b), the signal line (111) and the pixel electrodes (151a), (151
b) is not formed in the same layer, but is not shown
(111), insulating film, light shielding layer, insulating film, pixel electrode (151a), (151
In the laminated structure of b), the light shielding layer acts as a shield layer between the signal line (111) and the pixel electrodes (151a) and (151b),
It is possible to more completely reduce the coupling capacitance between the signal line (111) and the pixel electrodes (151a) and (151b).

[0080]

As described above in detail, according to the liquid crystal display device of the present invention, a part or all of the signal potential holding capacitor can be formed inside the display region without lowering the aperture ratio. In particular, the area outside the display area can be made small and miniaturization can be achieved.

[Brief description of drawings]

FIG. 1 is an equivalent circuit diagram of a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a schematic front view of the liquid crystal display device in FIG.

FIG. 3 is a schematic cross-sectional view taken along the line AA ′ and the line BB ′ of the liquid crystal display device in FIG. 2 from the front of the drawing.

4 is a sectional view taken along line CC ′ of the liquid crystal display device in FIG.
It is a schematic sectional drawing cut | disconnected along the line.

FIG. 5 is a diagram showing an equivalent circuit diagram of a conventional liquid crystal display device.

FIG. 6 is a schematic front view of a conventional liquid crystal display device.

[Explanation of symbols]

(111)… Signal line (113) ... scan line (121)… TFT (131)… Source extension area (141)… Gate insulating film (143) ... First insulating film for pixel capacitance (151)… Pixel electrode (161) ... First interlayer insulating film (163) ... First signal holding insulating film (165)… Second insulating film for pixel capacitance (171)… Second interlayer insulating film (175)… Second signal-holding insulating film (211)… Auxiliary capacitance line (301)… Second electrode substrate (313)… Shading layer

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G02F 1/1368 G02F 1/1343

Claims (7)

(57) [Claims] 1. A plurality of thin film transistors having a source region and a drain region, and an active region sandwiched between the source region and the drain region, and a video signal from a signal line driving circuit for each of the thin film transistors. A plurality of signal lines supplied to the drain region, a pair of pixel electrodes connected to the source regions of the thin film transistors on both sides of the signal line, and extending from the source region between the pair of pixel electrodes. Source territory
A source extension region electrically connected to the region, an auxiliary capacitance line disposed between the pair of pixel electrodes, and a first extension on at least a part of the surface of the source extension region.
A liquid crystal display, characterized in that the auxiliary capacitance line is provided via an insulating film for pixel capacitance, and a first signal holding insulating film laminated between the auxiliary capacitance line and the signal line. apparatus. 2. The liquid crystal display device according to claim 1 , wherein
The source extension region includes an upper region and a side region, and the first pixel capacitance insulating film is interposed between the upper region and the auxiliary capacitance line and between the side region and the auxiliary capacitance line. A liquid crystal display device, wherein a pixel storage capacitor is formed. 3. The liquid crystal display device according to claim 1,
A second pixel holding insulating film is disposed on at least a part of the surface of the auxiliary capacitance line, and a region overlapping with the pixel electrode via the second pixel holding insulating film is provided. Liquid crystal display device. 4. The liquid crystal display device according to claim 1,
Each of the thin film transistors includes a gate insulating film arranged on the active region, a gate electrode connected to a scanning line substantially orthogonal to the signal line through the gate insulating film, and the auxiliary capacitance line is A liquid crystal display device, wherein the liquid crystal display device extends in a direction substantially parallel to a scanning line. 5. The liquid crystal display device according to claim 1, wherein
Each of the thin film transistors includes a gate insulating film disposed on the active region, and a gate electrode connected to a scanning line substantially orthogonal to the signal line through the gate insulating film, and two scanning lines are provided. Are placed close to each other,
A liquid crystal display device, wherein each of the pixel electrodes adjacent to each other through one set of the scanning lines is arranged. 6. The liquid crystal display device according to claim 5 ,
A liquid crystal characterized in that the drain regions of the pair of thin film transistors connected to each of the pixel electrodes adjacent to each other via a set of the scanning lines are commonly connected to the signal lines via a connecting portion. Display device. 7. The liquid crystal display device according to claim 1,
Characterized in that the active region is polycrystalline silicon
Liquid crystal display device.