JPH05127195A - Liquid crystal display device - Google Patents
Liquid crystal display deviceInfo
- Publication number
- JPH05127195A JPH05127195A JP29262091A JP29262091A JPH05127195A JP H05127195 A JPH05127195 A JP H05127195A JP 29262091 A JP29262091 A JP 29262091A JP 29262091 A JP29262091 A JP 29262091A JP H05127195 A JPH05127195 A JP H05127195A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- signal line
- liquid crystal
- pixel
- pixel electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136218—Shield electrodes
Landscapes
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、アクティブマトリック
ス型の液晶表示装置に係わり、特にアレイ基板側にシー
ルド電極を形成した液晶表示装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type liquid crystal display device, and more particularly to a liquid crystal display device having a shield electrode formed on the array substrate side.
【０００２】[0002]
【従来の技術】近年、薄型軽量の表示装置として、液晶
ディスプレイの開発が活発に行われている。なかでも、
高画質，高精細を実現する方式として、薄膜トランジス
タアレイを用いたアクティブマトリックス方式の液晶デ
ィスプレイが注目されている。現在、例えばラップトッ
プ型コンピュータ用の液晶ディスプレイとしては、対角
１０インチサイズで画素数が縦 500×横2000程度のもの
が主流であるが、より高画質，高精細のディスプレイを
目指して、またファインピッチの高精細型プロジェクシ
ョンの開発等が行われている。2. Description of the Related Art In recent years, a liquid crystal display has been actively developed as a thin and lightweight display device. Above all,
As a method of realizing high image quality and high definition, an active matrix type liquid crystal display using a thin film transistor array is drawing attention. Currently, for example, as a liquid crystal display for a laptop computer, a mainstream is a diagonal 10 inch size with a pixel number of 500 × 2000, but aiming at a display with higher image quality and higher definition, Development of fine-pitch, high-definition projections is underway.
【０００３】薄膜トランジスタアレイを用いたアクティ
ブマトリックス方式の液晶ディスプレイの１画素構成を
図５（ａ）に、その等価回路を図５（ｂ）に示す。図中
１はスイッチング素子としての薄膜トランジスタ（ＴＦ
Ｔ）、２は走査線、３は信号線、４は画素電極である。
この装置では、走査線２が選択された時間だけＴＦＴ１
がＯＮとなり信号線３の電圧によって、画素電極４と対
向電極（図示せず）に挟まれた液晶で形成されるコンデ
ンサ（ＣLC）と、アレイ基板上に作り込まれた補助容量
（Ｃｓ）が充電される。走査線２の非選択時は、ＴＦＴ
１はＯＦＦとなり、画素電極４は信号線３から切り離さ
れ、画素電位が保持される。このようにして、画素電極
と対向電極との間に信号に対応した電界が生じ、液晶分
子が電界の向きに配向し、液晶を通過する光をコントロ
ールする。アクティブマトリックス方式の液晶ディスプ
レイの動作原理は、以上のようなものである。FIG. 5 (a) shows a one-pixel configuration of an active matrix type liquid crystal display using a thin film transistor array, and its equivalent circuit is shown in FIG. 5 (b). In the figure, 1 is a thin film transistor (TF) as a switching element.
T), 2 is a scanning line, 3 is a signal line, and 4 is a pixel electrode.
In this device, the TFT1 is operated only when the scanning line 2 is selected.
Is turned on and the voltage of the signal line 3 causes the capacitor (C LC ) formed of liquid crystal sandwiched between the pixel electrode 4 and the counter electrode (not shown), and the auxiliary capacitance (Cs) formed on the array substrate. Is charged. When scanning line 2 is not selected, TFT
1 is turned off, the pixel electrode 4 is separated from the signal line 3, and the pixel potential is held. In this way, an electric field corresponding to a signal is generated between the pixel electrode and the counter electrode, the liquid crystal molecules are oriented in the direction of the electric field, and light passing through the liquid crystal is controlled. The operating principle of the active matrix type liquid crystal display is as described above.
【０００４】ところで、薄膜トランジスタアレイにおい
ては、寄生容量として、画素電極−走査線間の静電容量
（Ｃgs），画素電極−信号線間の静電容量（Ｃds）が存
在する。従って画素電極は、信号線，走査線と静電容量
結合しており、信号線，走査線の電位変動が画素電位に
影響を与える。走査線の電位変動が問題となるのは画素
につながる走査線のパルスが立ち下がった時で、この時
に走査線パルスの立ち下がりに応じて突き抜け電圧（Δ
Ｖｐ）と呼ばれる電位変動が起こる。 ΔＶｐ＝｛Ｃgs／（ＣLC＋Ｃｓ＋Ｃgs＋Ｃds）｝×ΔＶg … (1)By the way, in the thin film transistor array, there are the electrostatic capacitance (Cgs) between the pixel electrode and the scanning line and the electrostatic capacitance (Cds) between the pixel electrode and the signal line as the parasitic capacitance. Therefore, the pixel electrode is capacitively coupled with the signal line and the scanning line, and the potential fluctuation of the signal line and the scanning line affects the pixel potential. The potential fluctuation of the scanning line becomes a problem when the pulse of the scanning line connected to the pixel falls, and at this time, the punch-through voltage (Δ
A potential fluctuation called Vp) occurs. ΔVp = {Cgs / (C LC + Cs + Cgs + Cds)} × ΔVg (1)
【０００５】この突き抜け電圧（ΔＶｐ）のため、画素
電位は信号線の電位で書き込むことができない。そこ
で、対向電極の電位をΔＶｐ分だけ変化させて突き抜け
電圧を補償したり、蓄積容量（Ｃｓ）を増やしてΔＶｐ
を小さくしている。しかし、ＣLCは一定ではなく液晶に
かかる電圧によって変化し、また製造上の問題で画面内
のＣgs，Ｃｓ，ＣLCを常に一定にすることはできない。
このため、ΔＶｐは画面内で一定でなくなり、対向電極
の電位を調整するだけでは完全に補償することができな
い。その結果、画面上でフリッカや焼き付きが問題とな
る。Due to this punch-through voltage (ΔVp), the pixel potential cannot be written with the potential of the signal line. Therefore, the potential of the counter electrode is changed by ΔVp to compensate the penetration voltage, or the storage capacitance (Cs) is increased to obtain ΔVp.
Is small. However, C LC is not constant and varies depending on the voltage applied to the liquid crystal, and Cgs, Cs, C LC in the screen cannot always be constant due to manufacturing problems.
Therefore, ΔVp is not constant within the screen, and cannot be completely compensated by only adjusting the potential of the counter electrode. As a result, flicker and image sticking become problems on the screen.
【０００６】一方、信号線の電位変動は常に起こるた
め、画素電位変化の様子は一様ではない。また、信号線
の駆動方法によっても変化の様子が違うが、一例として
フレーム反転での変化の様子を説明する。フレーム反転
では全ての信号線電位を同一極性とし、１フレーム毎に
信号線の極性を反転するため、この極性を反転したとき
が最も信号線の電位変動が大きい。このときの画素電位
の変動（ΔＶｐｓ）は、画素電極と静電容量を持つ左右
の信号線の電位変化をΔＶsig １，ΔＶsig ２として、
またそれぞれの静電容量をＣds１，Ｃds２とすると、 ΔＶｐｓ＝（Ｃds１×ΔＶsig １＋Ｃds２×ΔＶsig ２） ／（ＣLC＋Ｃｓ＋Ｃgs＋Ｃds１＋Ｃds２） … (2)On the other hand, since the potential of the signal line always fluctuates, the variation of the pixel potential is not uniform. Further, although the manner of change differs depending on the method of driving the signal line, the manner of change due to frame inversion will be described as an example. In frame inversion, all signal line potentials are set to have the same polarity, and the polarity of the signal line is inverted every frame. Therefore, when this polarity is inverted, the potential variation of the signal line is the largest. The fluctuation (ΔVps) of the pixel potential at this time is expressed as ΔVsig 1 and ΔVsig 2 which are the potential changes of the left and right signal lines having the pixel electrode and the capacitance.
Further, when each of the capacitance and Cds1, Cds2, ΔVps = (Cds1 × ΔVsig 1 + Cds2 × ΔVsig 2) / (C LC + Cs + Cgs + Cds1 + Cds2) ... (2)
【０００７】となる。この電位変動ΔＶｐｓが１フレー
ム毎に、言い換えれば画面の一番下の画素列を書き込む
毎に起こる。このため、画素毎に見ると書き込みが行わ
れてΔＶｐｓが起こるまでの時間が画面の上下で異なる
ため、それが輝度の変化として現われる。また、Ｃds
１，Ｃds２が大きくなると信号線の電位変動が画素電位
変動につながりクロストークとなる。[0007] This potential fluctuation ΔVps occurs every frame, that is, every time the bottom pixel row of the screen is written. Therefore, when viewed for each pixel, the time until writing and ΔVps occurs at the top and bottom of the screen is different, which appears as a change in brightness. Also, Cds
When 1 and Cds2 become large, the potential variation of the signal line leads to the pixel potential variation and crosstalk occurs.
【０００８】これらの寄生容量をアレイ基板で見てみる
と、まず、Ｃgsは主にＴＦＴのチャネル部分と走査線電
極とソース電極（画素電極）の重なり部分で形成され
る。また、Ｃdsは主に画素電極と信号線が接する部分で
形成される。前述のようにディスプレイの高精細化が進
み、１つの画素のサイズが小さくなってくると、各電極
間を大きく離すことはディスプレイの開口率を大きく低
下させることとなる。従って、各電極間をできるだけ近
付けることが望ましい。このように電極間距離を近付け
ると、Ｃds，Ｃgsが更に大きくなり、これらの寄生容量
が画質を劣化させる大きな要因となってくる。Looking at these parasitic capacitances on the array substrate, first, Cgs is mainly formed in the overlapping portion of the channel portion of the TFT, the scanning line electrode and the source electrode (pixel electrode). Further, Cds is mainly formed in a portion where the pixel electrode and the signal line are in contact with each other. As the definition of the display becomes higher and the size of one pixel becomes smaller as described above, widening the distance between the electrodes greatly reduces the aperture ratio of the display. Therefore, it is desirable to bring the respective electrodes as close as possible. When the distance between the electrodes is reduced in this way, Cds and Cgs are further increased, and the parasitic capacitances thereof are a major factor that deteriorates the image quality.
【０００９】さて、今までは、アレイ基板の寄生容量に
よる従来の諸問題について述べてきたが、液晶ディスプ
レイを光透過型デバイスとして使う場合、光による悪影
響への対策を講じなければならない。液晶物質に電圧が
掛かっていないときに表示が白或いは透明のとき、ノー
マリーホワイトモードと呼ぶが、このとき画素電極と信
号線電極の間から光が漏れ、コントラストが低下してし
まう。これを防ぐために従来から、対向基板に遮光性導
電膜でブラックマトリックスを形成している。しかし、
対向基板に形成するという理由で、その位置ずれを考慮
してブラックマトリックスを少し大きめに形成しなけれ
ばならないので、開口率を犠牲にしている。The conventional problems due to the parasitic capacitance of the array substrate have been described above. However, when the liquid crystal display is used as a light transmissive device, it is necessary to take measures against the adverse effect of light. When the display is white or transparent when no voltage is applied to the liquid crystal substance, it is called a normally white mode. At this time, light leaks from between the pixel electrode and the signal line electrode, and the contrast deteriorates. In order to prevent this, a black matrix is conventionally formed of a light-shielding conductive film on the counter substrate. But,
The aperture ratio is sacrificed because the black matrix must be formed a little larger in consideration of the positional deviation because it is formed on the counter substrate.
【００１０】また、一旦液晶を通過した光が対向電極側
のガラス基板やブラックマトリックス、或いはその後の
レンズ系などに反射して前記の薄膜トランジスタのバッ
クチャネルに入射すると、薄膜トランジスタのＯＦＦ時
のリーク電流となり、コントラスト低下などの画質劣化
につながるという問題がある。Further, when the light that has once passed through the liquid crystal is reflected by the glass substrate on the counter electrode side, the black matrix, or the lens system thereafter, and enters the back channel of the thin film transistor, a leak current is generated when the thin film transistor is turned off. However, there is a problem that it leads to deterioration of image quality such as reduction of contrast.
【００１１】その他の問題としては、液晶のエッジリバ
ースと呼ばれる問題がある。液晶ディスプレイは、基本
的には画素電極と対向電極との間に電界を掛け、その方
向に液晶物質が配向し光の透過，遮断を制御するもので
ある、しかし、画素電極の直ぐ横に信号線が存在するの
で、この信号線と画素電極の間にいわば横方向の電界が
掛り、液晶の配向状態を乱してしまう。これが、エッジ
リバースであり、コントラスト低下などの画質劣化につ
ながる。液晶ディスプレイの高精細化が進むに伴い信号
線と画素電極との間隔が益々狭くなり、この問題が深刻
化している。As another problem, there is a problem called liquid crystal edge reverse. The liquid crystal display basically applies an electric field between the pixel electrode and the counter electrode, and the liquid crystal substance is oriented in that direction to control the transmission and blocking of light. However, the signal is provided just beside the pixel electrode. Since there is a line, a so-called horizontal electric field is applied between the signal line and the pixel electrode, disturbing the alignment state of the liquid crystal. This is edge reverse, which leads to deterioration of image quality such as reduction in contrast. The gap between the signal line and the pixel electrode becomes narrower as the definition of the liquid crystal display becomes higher, and this problem becomes more serious.
【００１２】また、信号線と画素電極の隙間付近にある
液晶は、信号線と画素電極の電位が異なる場合、その配
向が信号線，画素の両方の電界の影響を受けている状態
である。いわば、液晶配向の遷移状態にあるといえる。
従来は、この遷移状態の液晶を通過する光は、画素電極
の電位で制御されず、コントラスト低下などの画質劣化
につながるので、対向基板に付けたブラックマトリック
スで覆い隠すといった措置を取っている。これは、開口
率を低くしている原因の一つとなる。Further, the liquid crystal in the vicinity of the gap between the signal line and the pixel electrode is in a state where its orientation is affected by the electric fields of both the signal line and the pixel when the potentials of the signal line and the pixel electrode are different. In a sense, it can be said that the liquid crystal alignment is in a transition state.
Conventionally, the light passing through the liquid crystal in this transition state is not controlled by the potential of the pixel electrode and leads to image deterioration such as contrast deterioration. Therefore, measures are taken to cover it with a black matrix attached to the counter substrate. This is one of the reasons for the low aperture ratio.
【００１３】[0013]
【発明が解決しようとする課題】このように従来、突き
抜け電圧を低く抑えるためには、(1) 式から分かるよう
に蓄積容量（Ｃｓ）を大きくしなければならないが、そ
のための電極を形成するとことは開口率を招く。また、
ＣdsやＣgs等の寄生容量は画質を劣化させる要因とな
り、特にＣdsが大きくなると信号線と画素電極とのクロ
ストークが顕著に現れる。これらの寄生容量を小さくす
るために電極間距離を大きく離すと、開口率の低下につ
ながる。また、高精細化が進むとエッジリバースによる
画質劣化も無視できないものとなる。As described above, in order to suppress the punch-through voltage to a low level, the storage capacitance (Cs) must be increased as is apparent from the equation (1). That leads to an aperture ratio. Also,
Parasitic capacitances such as Cds and Cgs cause deterioration of image quality, and especially when Cds becomes large, crosstalk between the signal line and the pixel electrode becomes remarkable. If the distance between the electrodes is increased to reduce these parasitic capacitances, the aperture ratio is reduced. Further, as the definition becomes higher, the image quality deterioration due to the edge reverse cannot be ignored.
【００１４】本発明は、上記事情を考慮してなされたも
ので、その目的とするところは、電極間距離を大きく離
すことなく、画素電極とこれに隣接する信号線や走査線
等の電極との間の寄生容量を低減することができ、クロ
ストークの低減，Ｃｓの増大及びエッジリバースの抑制
等により、表示画質の向上をはかり得る液晶表示装置を
提供することにある。The present invention has been made in consideration of the above circumstances, and an object thereof is to provide a pixel electrode and an electrode such as a signal line or a scanning line adjacent to the pixel electrode without a large distance between the electrodes. It is an object of the present invention to provide a liquid crystal display device capable of reducing the parasitic capacitance between them, and improving the display image quality by reducing crosstalk, increasing Cs and suppressing edge reverse.
【００１５】[0015]
【課題を解決するための手段】本発明の骨子は、画素電
極の存在する層と信号線の存在する層との間に、新たに
シールド電極を設置して、画素電極に関する寄生容量の
低減をはかることにある。The essence of the present invention is to newly install a shield electrode between a layer in which a pixel electrode exists and a layer in which a signal line exists to reduce the parasitic capacitance related to the pixel electrode. There is a question.
【００１６】即ち本発明は、行方向又は列方向に複数本
配列された信号線と、これらの信号線と直交する方向に
複数本配列された走査線と、信号線及び走査線で囲まれ
た領域にそれぞれ配置された画素電極と、画素電極と信
号線との間に接続された薄膜トランジスタとを具備した
液晶表示装置において、信号線が存在する層と画素電極
が存在する層との間に、該信号線及び画素電極とそれぞ
れ絶縁層を介してシールド電極を形成するようにしたも
のである。That is, according to the present invention, a plurality of signal lines arranged in a row direction or a column direction, a plurality of scanning lines arranged in a direction orthogonal to these signal lines, and a signal line and a scanning line are surrounded. In a liquid crystal display device including a pixel electrode arranged in each region and a thin film transistor connected between the pixel electrode and a signal line, between a layer in which the signal line is present and a layer in which the pixel electrode is present, A shield electrode is formed via the insulating layer with the signal line and the pixel electrode, respectively.
【００１７】[0017]
【作用】画素電極と信号線や走査線等の電極との間の静
電容量は、２つの電極の形状と周囲の誘電率，電極形状
に大きく左右される。２つの電極（例えば、画素電極と
信号線電極）間に定電位のシールド電極が存在する場
合、画素電極から信号線電極に向かう電気力線がシール
ド電極の静電シールド効果により減少する。この電気力
線の減少は、２つの電極間の静電容量の減少を意味す
る。従って本発明によれば、シールド電極を画素電極と
信号線との間に形成することによって、画素電極とこれ
に隣接する信号線との間の静電容量を減少させることが
できる。このため、従来技術に比べて画素電極に関する
寄生容量を低減し、より高画質な、高精細な液晶ディス
プレイの形成が可能となる。The capacitance between the pixel electrode and the electrode such as the signal line or the scanning line is greatly influenced by the shapes of the two electrodes, the surrounding permittivity, and the electrode shape. When a constant potential shield electrode is present between two electrodes (for example, a pixel electrode and a signal line electrode), the lines of electric force from the pixel electrode to the signal line electrode are reduced by the electrostatic shield effect of the shield electrode. This decrease in the lines of electric force means a decrease in the capacitance between the two electrodes. Therefore, according to the present invention, by forming the shield electrode between the pixel electrode and the signal line, it is possible to reduce the electrostatic capacitance between the pixel electrode and the signal line adjacent thereto. Therefore, it is possible to reduce the parasitic capacitance related to the pixel electrode as compared with the conventional technique, and to form a high-definition and high-definition liquid crystal display.
【００１８】本発明では、信号線と画素電極の間の層
に、絶縁膜で絶縁を保ちながら、シールド電極を形成し
一定電位に保つことにより、信号線電極の電位変動の影
響を画素電極に伝えないようにし、クロストークをなく
すことができる。さらに、このシールド電極は、液晶に
掛ってしまう横方向の電界の最大値を抑え、前述のエッ
ジリバースの影響を低くし、コントラスト等の表示特性
を向上させることができる。そのうえ、このシールド電
極と画素電極との間に静電容量を持つことから、これを
前述の蓄積容量（Ｃｓ）として使うことができるので、
開口率を低めたり製作工程数を増やしたりせずにすむ。According to the present invention, a shield electrode is formed in the layer between the signal line and the pixel electrode while maintaining insulation with an insulating film to maintain a constant potential, so that the pixel electrode is affected by the potential fluctuation of the signal line electrode. You can turn it off and eliminate crosstalk. Further, this shield electrode can suppress the maximum value of the electric field in the lateral direction applied to the liquid crystal, reduce the influence of the edge reverse described above, and improve the display characteristics such as contrast. Moreover, since there is an electrostatic capacitance between the shield electrode and the pixel electrode, this can be used as the above-mentioned storage capacitance (Cs).
Do not reduce the aperture ratio or increase the number of manufacturing processes.
【００１９】また、シールド電極をＴａで形成し、その
表面を陽極酸化すれば、表面に誘電率の高い絶縁膜を被
覆した電極となり、前述の蓄積容量（Ｃｓ）をより大き
くすることができ、前述の突き抜け電圧や信号線・画素
のクロストークをさらに低減させることができる。If the shield electrode is made of Ta and its surface is anodized, it becomes an electrode whose surface is covered with an insulating film having a high dielectric constant, and the aforementioned storage capacitance (Cs) can be further increased. It is possible to further reduce the above-mentioned punch-through voltage and signal line / pixel crosstalk.
【００２０】また、シールド電極を遮光性導電膜で形成
することにより、ブラックマトリックスとしての働きも
兼ねさせ、なおかつ、薄膜トランジスタのバックチャネ
ルを光から守るチャネル遮光膜の働きもさせることがで
きる。逆に、シールド電極を透明導電膜で形成すれば、
開口率を低下させずに大きな静電容量を持った蓄積容量
（Ｃｓ）を形成でき、前述の突き抜け電圧（ΔＶｐ）を
低く抑えることができる。Further, by forming the shield electrode with a light-shielding conductive film, it can also serve as a black matrix and also serve as a channel light-shielding film that protects the back channel of the thin film transistor from light. On the contrary, if the shield electrode is made of a transparent conductive film,
A storage capacitor (Cs) having a large electrostatic capacity can be formed without lowering the aperture ratio, and the punch-through voltage (ΔVp) can be suppressed to a low level.
【００２１】また、シールド電極の電位を適当に調整す
ることにより、信号線と画素電極の隙間付近の液晶の配
向状態をコントロールし、ブラックマトリックス（シー
ルド電極自身）で覆い隠さなければならない面積を減ら
して、開口率を上げることも可能である。Further, by appropriately adjusting the potential of the shield electrode, the alignment state of the liquid crystal in the vicinity of the gap between the signal line and the pixel electrode is controlled, and the area that must be covered by the black matrix (shield electrode itself) is reduced. It is also possible to increase the aperture ratio.
【００２２】[0022]
【実施例】以下、本発明の詳細を図示の実施例によって
説明する。The details of the present invention will be described below with reference to the illustrated embodiments.
【００２３】図１は本発明の第１の実施例に係わる液晶
ディスプレイの１画素構成を示すもので、（ａ）は平面
図、（ｂ）は（ａ）の矢視Ａ−Ａ′断面図である。図中
１１はスイッチング素子としての薄膜トランジスタ（Ｔ
ＦＴ）、１２は走査線（ゲート線）、１３は信号線、１
４は画素電極、１５はシールド電極、２０はガラス基
板、２１，２２，２３は絶縁膜を示している。1A and 1B show a one-pixel configuration of a liquid crystal display according to a first embodiment of the present invention. FIG. 1A is a plan view and FIG. 1B is a sectional view taken along the line AA 'in FIG. Is. In the figure, 11 is a thin film transistor (T
FT), 12 is a scanning line (gate line), 13 is a signal line, 1
Reference numeral 4 is a pixel electrode, 15 is a shield electrode, 20 is a glass substrate, 21, 22, and 23 are insulating films.
【００２４】基本的な構成は従来装置と同様であるが、
本実施例ではシールド電極１５を新たに設けたことを特
徴としている。即ち、シールド電極１５は、信号線１３
が存在する層と画素電極１４が存在する層との間に配置
され、信号線１３を覆うように且つ画素電極１４と一部
重なるように形成されている。また、シールド電極１５
と信号線１３及び画素電極１４との間には、絶縁膜２
２，２３がそれぞれ配設されている。次に、上記装置の
製造方法について説明する。The basic structure is the same as that of the conventional device,
This embodiment is characterized in that the shield electrode 15 is newly provided. That is, the shield electrode 15 is connected to the signal line 13
Is disposed between the layer in which the pixel electrode 14 exists and the layer in which the pixel electrode 14 exists, and is formed so as to cover the signal line 13 and partially overlap the pixel electrode 14. In addition, the shield electrode 15
The insulating film 2 is provided between the signal line 13 and the signal line 13 and the pixel electrode 14.
2 and 23 are arranged respectively. Next, a method for manufacturing the above device will be described.
【００２５】まず、ガラス基板２０上にＭｏ−Ｔａ合金
を２５０ｎｍ堆積し、これをパターニングして、走査線
１２を形成する。続いて、これらの上にゲート絶縁膜２
１としてＳｉＯｘ，ＳｉＮｘをそれぞれ３００ｎｍ，５
０ｎｍ堆積し、連続して活性層のａ−Ｓｉ，チャネル保
護膜としてＳｉＮｘを、それぞれ５０ｎｍ，２００nm堆
積する。First, a Mo-Ta alloy is deposited to a thickness of 250 nm on the glass substrate 20, and this is patterned to form the scanning line 12. Then, the gate insulating film 2 is formed on these.
SiOx and SiNx as 300 nm and 5 respectively
0 nm is deposited, and a-Si of the active layer and SiNx as a channel protective film are successively deposited to 50 nm and 200 nm, respectively.
【００２６】次いで、チャネル保護膜のＳｉＮｘを島状
にエッチング形成したのち、オーミックコンタクト層と
してのｎ+ ａ−Ｓｉ層を５０ｎｍ堆積する。この後、ｎ
+ ａ−Ｓｉ，ａ−Ｓｉを島状にエッチングし、走査線１
２の取り出し部分のゲート絶縁膜２１を除去する。Next, SiNx of the channel protective film is etched to form an island, and then n + as an ohmic contact layer is formed. Deposit 50 nm of a-Si layer. After this, n
+ a-Si and a-Si are etched into islands, and scanning line 1
The gate insulating film 21 at the extraction portion 2 is removed.
【００２７】次いで、Ｃｒ，Ａｌをそれぞれ５０ｎｍ，
３００ｎｍ堆積し、これをパターニングして信号線１３
（ドレイン電極），ソース電極を形成する。そして、信
号線１３をマスクにしてＴＦＴ１１のソース−ドレイン
電極間のｎ+ ａ−Ｓｉ層をチャネル保護膜とは選択的に
エッチング除去する。その後、全面にＳｉＮｘ膜２２を
３５０ｎｍ堆積してから、前記シールド電極１５とし
て、遮光性導電膜のＣｒを１００ｎｍ堆積させる。な
お、シールド電極１５としては、必ずしも遮光性導電膜
に限らず、透明導電膜のＩＴＯを１００ｎｍ堆積させて
もよい。さらに、遮光性導電膜としてのＴａを６００ｎ
ｍ堆積させて、その表面を３００ｎｍだけ陽極酸化して
もよい。Next, Cr and Al are added to 50 nm,
The signal line 13 is formed by depositing 300 nm and patterning it.
(Drain electrode) and source electrode are formed. Then, using the signal line 13 as a mask, n + between the source and drain electrodes of the TFT 11 is increased. The a-Si layer is selectively removed by etching from the channel protective film. After that, a SiNx film 22 is deposited to a thickness of 350 nm on the entire surface, and then Cr of a light-shielding conductive film is deposited to a thickness of 100 nm as the shield electrode 15. The shield electrode 15 is not limited to the light-shielding conductive film, and ITO of a transparent conductive film may be deposited to a thickness of 100 nm. Further, Ta as the light-shielding conductive film is 600 n
m, and the surface may be anodized by 300 nm.
【００２８】次いで、全面にＳｉＮｘ膜２３を２００ｎ
ｍ堆積し、前記走査線１２の端部パッド部上と、前記ソ
ース電極上、及び前記シールド電極１５の端部パッド上
のＳｉＮｘをエッチング除去する。但し、シールド電極
１５をＴａ及びその陽極酸化膜で形成した場合は、この
ＳｉＮｘ膜を堆積しない。しかるのちに、画素電極１４
としてのＩＴＯを１００ｎｍ堆積し、エッチングにより
そのパターンを形成する。このようにして、ＴＦＴアレ
イが形成される。そして、このＴＦＴアレイ基板と対向
電極基板との間に液晶を挿入し、封止することにより、
液晶ディスプレイが形成される。Next, the SiNx film 23 is formed on the entire surface by 200 n.
Then, SiNx on the end pad portion of the scanning line 12, on the source electrode, and on the end pad of the shield electrode 15 is removed by etching. However, when the shield electrode 15 is formed of Ta and its anodic oxide film, this SiNx film is not deposited. After that, the pixel electrode 14
Is deposited to a thickness of 100 nm, and the pattern is formed by etching. In this way, the TFT array is formed. Then, by inserting a liquid crystal between the TFT array substrate and the counter electrode substrate and sealing it,
A liquid crystal display is formed.
【００２９】このような構成であれば、画素電極１４か
ら信号線１３に向かう電気力線がシールド電極１５の静
電シールド効果により減少する。このため、画素電極−
信号線間の静電容量が低減し、寄生容量に起因する画質
の劣化を未然に防止することができる。つまり、表示画
質の向上をはかることができる。なお、本発明者らの実
験によれば、突き抜け電圧，フレーム反転による画素電
位変動を検出して従来装置と比較することによって、シ
ールド電極１５の形成により画素電極−信号線の間の寄
生容量が減少することが確認された。With this structure, the lines of electric force from the pixel electrode 14 to the signal line 13 are reduced by the electrostatic shield effect of the shield electrode 15. Therefore, the pixel electrode
The electrostatic capacitance between the signal lines is reduced, and deterioration of image quality due to parasitic capacitance can be prevented in advance. That is, it is possible to improve the display image quality. According to the experiments conducted by the present inventors, the penetration capacitance and the pixel potential variation due to the frame inversion are detected and compared with the conventional device, whereby the formation of the shield electrode 15 reduces the parasitic capacitance between the pixel electrode and the signal line. It was confirmed to decrease.
【００３０】また、本実施例では、シールド電極１５を
一定電位に保つことにより、信号線１３の電位変動の影
響を画素電極１４に伝えないようにし、クロストークを
なくすことができる。さらに、シールド電極１５は液晶
に掛ってしまう横方向の電界の最大値を抑え、前述のエ
ッジリバースの影響を少なくするので、コントラスト等
の表示特性を向上させることができる。しかも、シール
ド電極１５は画素電極１４との間に静電容量を持つこと
から、これを蓄積容量（Ｃｓ）として使うことができ
る。Further, in the present embodiment, by keeping the shield electrode 15 at a constant potential, it is possible to prevent the influence of the potential fluctuation of the signal line 13 from being transmitted to the pixel electrode 14 and eliminate crosstalk. Further, since the shield electrode 15 suppresses the maximum value of the electric field in the lateral direction applied to the liquid crystal and reduces the influence of the above-mentioned edge reverse, it is possible to improve display characteristics such as contrast. Moreover, since the shield electrode 15 has an electrostatic capacitance between the shield electrode 15 and the pixel electrode 14, this can be used as the storage capacitance (Cs).
【００３１】また、シールド電極１５を遮光性導電膜で
形成しているので、これをブラックマトリックスとして
利用することができ、さらにＴＦＴ１１のバックチャネ
ルを光から守るチャネル遮光膜として利用することもで
きる。さらに、シールド電極１５の電位を適当に調整す
ることによって、信号線１３と画素電極１４の隙間付近
の液晶の配向状態をコントロールし、ブラックマトリッ
クス（シールド電極自身）で覆い隠さなければならない
面積を減らして、開口率を上げることも可能である。Further, since the shield electrode 15 is formed of a light-shielding conductive film, it can be used as a black matrix, and can further be used as a channel light-shielding film that protects the back channel of the TFT 11 from light. Further, by appropriately adjusting the potential of the shield electrode 15, the alignment state of the liquid crystal near the gap between the signal line 13 and the pixel electrode 14 is controlled, and the area that must be covered with the black matrix (shield electrode itself) is reduced. It is also possible to increase the aperture ratio.
【００３２】また、シールド電極をＴａで形成し、その
表面を陽極酸化すれば、表面に誘電率の高い絶縁膜を被
覆した電極となり、前述の蓄積容量（Ｃｓ）をより大き
くすることができ、突き抜け電圧や信号線，画素のクロ
ストークをさらに低減させることができる。If the shield electrode is made of Ta and its surface is anodized, it becomes an electrode whose surface is covered with an insulating film having a high dielectric constant, and the aforementioned storage capacitance (Cs) can be further increased. Penetration voltage, signal lines, and pixel crosstalk can be further reduced.
【００３３】図２は、本発明の第２の実施例の要部構成
を示す図であり、（ａ）は平面図、（ｂ）は（ａ）の矢
視Ｂ−Ｂ′断面図である。なお、図１と同一部分には同
一符号を付して、その詳しい説明は省略する。2A and 2B are views showing the configuration of the main part of the second embodiment of the present invention, wherein FIG. 2A is a plan view and FIG. 2B is a sectional view taken along the line BB 'of FIG. .. The same parts as those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted.
【００３４】この実施例が、先に説明した第１の実施例
と異なる点は、遮光性導電膜のシールド電極２５をマス
クにし、アレイ基板の裏側から光を当てて画素電極１４
をセルフアラインで形成したことにある。The difference between this embodiment and the first embodiment described above is that the shield electrode 25 of the light-shielding conductive film is used as a mask and light is applied from the back side of the array substrate to the pixel electrode 14.
Is formed by self-alignment.
【００３５】この実施例では、シールド電極２５と画素
電極１４との間の静電容量を蓄積容量とするときに、パ
ターン合わせずれによる蓄積容量の設計値からのずれを
なくすことができる。また、この場合、画素電極１４と
シールド電極２５がオーバラップしないので、絶縁膜の
ピンホールによる層間ショートの恐れはない。In this embodiment, when the electrostatic capacitance between the shield electrode 25 and the pixel electrode 14 is used as the storage capacitance, it is possible to eliminate the deviation from the design value of the storage capacitance due to the pattern misalignment. Further, in this case, since the pixel electrode 14 and the shield electrode 25 do not overlap with each other, there is no fear of interlayer short circuit due to the pinhole of the insulating film.
【００３６】ここで、今後の投射型液晶テレビ、ビュー
ファインダー等の高精細化への動向を考えると、画素サ
イズはできるだけ小さい方が望ましい。現状では、小型
のものでも１００μｍ×１００μｍ程度である。将来的
にはより一層の小型化が望まれるが、技術的に難しい問
題を抱えている。例えば、画素サイズ４０μｍ×４０μ
ｍとして、従来のようにゲート線と同じ層に適切な大き
さの蓄積容量電極を設けると、開口率は殆ど０％であ
り、また、狭い面積で容量を稼ぐために蓄積容量の絶縁
膜を誘電率の高いものにしたとしても、高々開口率を２
０％にできる程度であった。Here, considering the trend toward higher definition of projection type liquid crystal televisions, viewfinders and the like in the future, it is desirable that the pixel size is as small as possible. At present, even a small size is about 100 μm × 100 μm. Although further miniaturization is desired in the future, there are technically difficult problems. For example, pixel size 40 μm × 40 μ
As m, if a storage capacitor electrode of an appropriate size is provided in the same layer as the gate line as in the conventional case, the aperture ratio is almost 0%, and an insulating film of the storage capacitor is formed in order to obtain a capacitance in a small area. Even if the dielectric constant is high, the aperture ratio is at most 2
It was about 0%.
【００３７】これに対し、第１及び第２の実施例のよう
な構造を採用することにより、画素サイズが４０μｍ×
４０μｍであるにも拘らず、開口率５２％を達成するこ
とができた。On the other hand, by adopting the structures of the first and second embodiments, the pixel size is 40 μm ×
Despite being 40 μm, an aperture ratio of 52% could be achieved.
【００３８】図３は、本発明の第３の実施例の要部構成
を示す図であり、（ａ）は平面図、（ｂ）は（ａ）の矢
視Ｃ−Ｃ′断面図である。なお、図１と同一部分には同
一符号を付して、その詳しい説明は省略する。3A and 3B are views showing the configuration of the essential parts of a third embodiment of the present invention, wherein FIG. 3A is a plan view and FIG. 3B is a sectional view taken along the line CC 'of FIG. .. The same parts as those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted.
【００３９】この実施例では、シールド電極３５を透明
導電膜にし、画素電極１４下のほぼ全面にも形成してい
る。ここで、シールド電極３５が透明であることからＴ
ＦＴ部分上にはシールド電極３５を形成していないが、
ＴＦＴ部分の遮光には別に遮光膜を設ける、又は対向基
板側に遮光膜を設けるようにすればよい。これによっ
て、蓄積容量（Ｃｓ）を十分に大きくすることができ、
突き抜け電圧（ΔＶｐ）の変動量を０．１Ｖ以下に低減
することができた。また、図３のような画素形状を取
り、ノーマリーブラックモードにすれば、画素サイズが
４０μｍ×４０μｍであるにも拘らず、開口率５７％を
達成することができた。In this embodiment, the shield electrode 35 is made of a transparent conductive film and is formed almost all over the pixel electrode 14. Here, since the shield electrode 35 is transparent, T
Although the shield electrode 35 is not formed on the FT portion,
A light shielding film may be separately provided for shielding the TFT portion, or a light shielding film may be provided on the counter substrate side. As a result, the storage capacity (Cs) can be increased sufficiently,
It was possible to reduce the variation amount of the punch-through voltage (ΔVp) to 0.1 V or less. Further, when the pixel shape as shown in FIG. 3 is taken and the normally black mode is set, an aperture ratio of 57% can be achieved despite the pixel size being 40 μm × 40 μm.
【００４０】また、シールド電極３５を透明導電膜で作
っていれば、走査線１２と信号線１３をマスクにして、
アレイ基板の裏側から光を当てる所謂セルフアライン法
で画素電極１４を形成することもできる。この方法によ
り、マスクの合わせずれを考慮せずに済むようになり、
走査線１２及び信号線１３を光漏れを防ぐブラックマト
リックスとして利用することができる。これにより、前
述の画素サイズが４０μｍ×４０μｍの場合で、開口率
７０％を達成することができた。また、ノーマリーホワ
イトモードを使えるので、コントラストを高くすること
ができるようになった。If the shield electrode 35 is made of a transparent conductive film, the scanning line 12 and the signal line 13 are used as a mask,
The pixel electrode 14 can also be formed by a so-called self-alignment method in which light is applied from the back side of the array substrate. By this method, it becomes unnecessary to consider the misalignment of the mask,
The scanning lines 12 and the signal lines 13 can be used as a black matrix that prevents light leakage. As a result, an aperture ratio of 70% could be achieved when the pixel size was 40 μm × 40 μm. Also, since the normally white mode can be used, the contrast can be increased.
【００４１】図４は、本発明の第４の実施例の要部構成
を示す図であり、（ａ）は平面図、（ｂ）は（ａ）の矢
視Ｄ−Ｄ′断面図である。なお、図１と同一部分には同
一符号を付して、その詳しい説明は省略する。4A and 4B are views showing the structure of the main part of a fourth embodiment of the present invention, FIG. 4A is a plan view, and FIG. 4B is a sectional view taken along the line DD 'of FIG. .. The same parts as those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted.
【００４２】この実施例は、基本的には第１の実施例と
同様であるが、ＴＦＴのバックチャネル上部だけシール
ド電極１５を除去している。なお、図中１６はａ−Ｓｉ
等の活性層、１７はＳｉＮｘ等のチャネル保護膜、１８
は対向電極、３０は対向基板を示している。This embodiment is basically the same as the first embodiment, but the shield electrode 15 is removed only above the back channel of the TFT. In the figure, 16 is a-Si
And the like, 17 is an active layer, 17 is a channel protective film such as SiNx, and 18
Is a counter electrode, and 30 is a counter substrate.
【００４３】ここで、シールド電極１５の電位である
が、例えば対向電極と同電位にしておくと、結果的に開
口率を最大にできる。但しこの場合、ＴＦＴのバックチ
ャネル側に正電位の電極が存在するので、ＴＦＴのリー
ク電流が懸念される。従って本実施例のようにバックチ
ャネル上部だけシールド電極１５を抜いておく。もし、
ＴＦＴのバックチャネルを遮光しなければならない場合
は、対向基板側にブラックマトリックスを取り付ければ
よい。Here, although the potential of the shield electrode 15 is the same as that of the counter electrode, the aperture ratio can be maximized as a result. However, in this case, since there is a positive potential electrode on the back channel side of the TFT, there is a concern about leakage current of the TFT. Therefore, as in this embodiment, the shield electrode 15 is removed only in the upper portion of the back channel. if,
When it is necessary to shield the back channel of the TFT from light, a black matrix may be attached to the counter substrate side.
【００４４】なお、本発明は上述した各実施例に限定さ
れるものではない。ＴＦＴアレイのパターン，層構造や
材料等は、実施例で用いたものに限定されるものではな
く、仕様に応じて適宜変更可能である。また、シールド
電極はゲート絶縁膜中にあってもよく、材料はＣｒでも
よい。その他、本発明の要旨を逸脱しない範囲で、種々
変形して実施することができる。The present invention is not limited to the above embodiments. The pattern, layer structure, material, etc. of the TFT array are not limited to those used in the embodiments, and can be changed appropriately according to the specifications. The shield electrode may be in the gate insulating film, and the material may be Cr. In addition, various modifications can be made without departing from the scope of the present invention.
【００４５】[0045]
【発明の効果】以上詳述したように本発明によれば、信
号線が形成された層と画素電極が形成された層との間に
シールド電極を配設し、且つこのシールド電極を遮光性
導電膜で形成することにより、次のような効果を期待で
きる。 (1) 信号線と画素とのクロストークをなくすことができ
る。 (2) シールド電極をブラックマトリックスとしても利用
できるので、光漏れによるコントラスト低下を防ぐこと
ができる。 (3) 対向電極に反射して、薄膜トランジスタのチャネル
に入射する光を遮断するチャネル遮光膜としての働きも
ある。As described above in detail, according to the present invention, the shield electrode is provided between the layer in which the signal line is formed and the layer in which the pixel electrode is formed, and the shield electrode is shielded from light. By forming the conductive film, the following effects can be expected. (1) Crosstalk between the signal line and the pixel can be eliminated. (2) Since the shield electrode can also be used as a black matrix, it is possible to prevent a decrease in contrast due to light leakage. (3) It also functions as a channel light-shielding film that blocks light that is reflected by the counter electrode and enters the channel of the thin film transistor.
【００４６】(4) エッジリバースを低減させて、コント
ラストを向上させることができる。 (5) 開口率を犠牲にせずに、なおかつ、製作工程数を増
やすことなく、蓄積容量を形成できる。(4) The edge reverse can be reduced to improve the contrast. (5) The storage capacitor can be formed without sacrificing the aperture ratio and without increasing the number of manufacturing steps.
【００４７】(6) このシールド電極の電位を最適化すれ
ば、ブラックマトリックス（シールド電極自身が兼ねて
いる）で覆い隠すべき面積を減らせるので、開口率を上
げることができる。(6) By optimizing the potential of the shield electrode, the area to be covered by the black matrix (which the shield electrode itself also serves) can be reduced, so that the aperture ratio can be increased.
【００４８】また、シールド電極を、透明導電膜で形成
する場合には、上記の(2)(3)の効果はないが、上記の
(5)の効果の蓄積容量を大きくすることができるので、
前述の突き抜け電圧をさらに小さく抑えることができ
る。When the shield electrode is formed of a transparent conductive film, the effects of (2) and (3) above are not obtained, but
Since the storage capacity of the effect of (5) can be increased,
The punch-through voltage described above can be further reduced.
【図１】第１の実施例に係わる液晶ディスプレイの１画
素構成を示す図、FIG. 1 is a diagram showing a one-pixel configuration of a liquid crystal display according to a first embodiment,
【図２】第２の実施例に係わる液晶ディスプレイの１画
素構成を示す図、FIG. 2 is a diagram showing a one-pixel configuration of a liquid crystal display according to a second embodiment,
【図３】第３の実施例に係わる液晶ディスプレイの１画
素構成を示す図、FIG. 3 is a diagram showing a one-pixel configuration of a liquid crystal display according to a third embodiment,
【図４】第４の実施例に係わる液晶ディスプレイの１画
素構成を示す図、FIG. 4 is a diagram showing a one-pixel configuration of a liquid crystal display according to a fourth embodiment,
【図５】従来の液晶ディスプレイの１画素構成を示す
図。FIG. 5 is a diagram showing a one-pixel configuration of a conventional liquid crystal display.
１１…薄膜トランジスタ（ＴＦＴ）、 １２…走査線（ゲート線）、 １３…信号線、 １４…画素電極、 １５，２５，３５…シールド電極、 ２０…ガラス基板、 ２１，２２，２２…絶縁層。 11 ... Thin film transistor (TFT), 12 ... Scan line (gate line), 13 ... Signal line, 14 ... Pixel electrode, 15, 25, 35 ... Shield electrode, 20 ... Glass substrate, 21, 22, 22 ... Insulating layer.
Claims (1)
線と、これらの信号線と直交する方向に複数本配列され
た走査線と、前記信号線及び走査線で囲まれた領域にそ
れぞれ配置された画素電極と、前記画素電極と信号線と
の間に接続された薄膜トランジスタとを具備した液晶表
示装置において、 前記信号線が存在する層と前記画素電極が存在する層と
の間に、該信号線及び画素電極とそれぞれ絶縁層を介し
てシールド電極を形成してなることを特徴とする液晶表
示装置。1. A plurality of signal lines arranged in a row direction or a column direction, a plurality of scanning lines arranged in a direction orthogonal to the signal lines, and a region surrounded by the signal lines and the scanning lines. In a liquid crystal display device comprising pixel electrodes respectively arranged and a thin film transistor connected between the pixel electrode and a signal line, between a layer in which the signal line is present and a layer in which the pixel electrode is present. A liquid crystal display device comprising a shield electrode formed between the signal line and the pixel electrode via an insulating layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29262091A JPH05127195A (en) | 1991-11-08 | 1991-11-08 | Liquid crystal display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29262091A JPH05127195A (en) | 1991-11-08 | 1991-11-08 | Liquid crystal display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05127195A true JPH05127195A (en) | 1993-05-25 |
Family
ID=17784160
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29262091A Pending JPH05127195A (en) | 1991-11-08 | 1991-11-08 | Liquid crystal display device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05127195A (en) |
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-
1991
- 1991-11-08 JP JP29262091A patent/JPH05127195A/en active Pending
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