JP3450132B2 - Cache control circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache control circuit, and more particularly to a cache control system for a fault tolerant computer.

[0002]

2. Description of the Related Art Conventionally, in this type of cache control system, a fault-tolerant computer having a duplicated memory has an object to efficiently reflect the cache contents in the duplicated memory without impairing the fault tolerance. It is used.

That is, in a fault-tolerant computer, when the cache in the processor element is updated, each time the update is performed, a sequential write process for reflecting the updated content in one memory element is performed by a write-through method, and the other memory element is executed. On the other hand, during the checkpoint processing, the batch write-out processing is performed in which all the updated contents of the cache are collectively written.

Regarding the cache update processing in the above fault tolerant computer, Japanese Patent Laid-Open No. 7-
This is described in detail in Japanese Patent No. 271624.

[0005]

In the above-mentioned conventional cache control method, only the memory element is made redundant, and the case where the processor element is made redundant is not taken into consideration. When the processor element is made redundant, the failure of the processor element itself can be covered by the alternative processor element, so that the above checkpoint processing itself is unnecessary and a more efficient system can be constructed. Further, even if one processor element fails, there is no need to recover from the memory.

However, when the processor elements are made redundant, an error occurs only in one redundant processor element. Therefore, the operation of correcting the error and writing the corrected data in the cache causes the error. It is only the processor element that occurred. When the correction data is written in the cache of the processor element in which the error has occurred, the cache cannot be accessed from the processor while the correction data writing operation is performed.

Therefore, for example, when a read from the processor to the cache occurs while the processor element in which the error has occurred is writing the correction data,
Read data is immediately returned from the cache to the processor in a processor element in which no error has occurred, but read data can be returned to the processor in the processor element in which an error has occurred until the writing of the correction data to the cache is completed. Can not.

As described above, if an error is corrected and correction data is written in the cache, the redundant processor elements that must operate in synchronization will be out of synchronization. Therefore, when the processor elements are also made redundant, even if a correctable error is detected in the cache, there arises a problem that the error-corrected data cannot be written in the cache. In the prior art, this problem does not occur because the processor elements are not redundant.

Therefore, an object of the present invention is to solve the above-mentioned problems, and even if an error occurs in a cache in a redundant processor element, an uncorrectable error does not occur without shifting the synchronization of the redundant processor element. It is to provide a cache control circuit that can prevent the development of the cache control circuit.

[0010]

SUMMARY OF THE INVENTION A cache control circuit according to the present invention comprises a cache memory for storing a part of the contents of a storage device, and the cache in which the stored contents do not match the contents of the storage device due to writing of data. A cache control circuit of an information processing system, comprising: first and second processor elements, which are provided with write-back means for writing back stored contents of a memory to the storage device, and which operate in synchronization with each other. Error detection / correction means for detecting an error in read data and correcting the detected error, and the write-back in response to an error notification output from the error detection / correction means and the error detection / correction means of another processor element. A finger for instructing the means to write back the contents stored in the cache memory to the storage device. And means possess in the first and second processor elements each, said write back means, not one
The stored contents of the cache memory that has become a match are stored in the memory.
It is detected by the error detection and correction means when writing back to the device.
Write to the storage device after correcting the correctable error
It is characterized in that it is configured to return.

Another cache control circuit according to the present invention is
A cache control circuit of an information processing system, comprising a first and a second processor element having a cache memory for storing a part of the contents of a storage device and operating in synchronization with each other, wherein the cache control circuit stores data read from the cache memory. and error detection and correction means for performing detecting and correcting the detected correctable errors errors, an address holding means for holding a read address of said cache, the error when the error is detected by the error detection and correction means Correction data holding means for holding the corrected data,
Said correction data holding means with an error notification and the address held in the address holding unit when an error notification one is inputted from said error detecting and correcting means of another processor element from said error detecting and correcting means of its own processor element and means for instructing writing the data held in the cache memory to the first and second processor elements each, wherein the first and second
The error detection and correction of one of the processor elements
When an uncorrectable error is detected by the corrective means, the first
And disconnecting one of the second processor element
Of the first and second processor elements
On the other hand, the process is continued .

As described above, according to the cache control method of the present invention, when an error occurs in the cache of the redundant processor element, the error on the cache is eliminated without shifting the synchronization of the redundant processor element. Remove.

More specifically, an error detection / correction circuit having a function of detecting an error in read data from the cache and correcting an error in data having an error, and all error detection / correction of redundant processor elements And an interrupt generation circuit that generates an interrupt for notifying the software that an error has been detected for the software to flush the cache in accordance with the error notification received from the circuit.

According to another method, an error detection / correction circuit having a function of detecting an error in read data from the cache and correcting an error in data having an error, and an address holding means for holding a read address of the cache. , Correction data holding means for holding read data from the cache in which the error is corrected when the error is detected by the error detection / correction circuit, and error notification from the error detection / correction circuit of the own processor element, or any one of
It has a correction data writing means for issuing an instruction to write the data held by the correction data holding means to the cache at the address held by the address holding means in response to an error notification from one or more other processor elements.

Data causing an error on the cache without shifting the synchronization of the redundant processor elements by flushing the cache by software by the interrupt generation circuit or writing correction data to the cache by the correction data writing means. Can be removed.

This is different from the usual system, in general, even when a correctable error occurs in the cache, a processor element which has been separated from the service due to the problem of synchronization of the processor element made redundant as a fault tolerant system. It has the effect of enabling continuous operation and improving reliability performance.

At present, the cache has a large capacity, and accordingly, there is a high probability that a soft error, which is not a hardware failure due to radiation or the like, will occur in the cache. A soft error can be restored to its original state by correcting the error.

In a fault-tolerant computer in which reliability is particularly important, it is possible to improve reliability significantly by recovering this cache soft error and continuing to operate in a redundant configuration.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the first embodiment of the present invention. In the figure, since the processor elements 1 and 2 are duplicated, they have exactly the same components. That is, the processor elements 1 and 2 have the MPUs 11 and 21 and the cache 1
2, 22, error detection / correction circuits 13 and 23, and interrupt generation circuits 14 and 24.

The MPUs 11 and 21 are microprocessors that perform arithmetic processing in the processor elements 1 and 2, respectively. The caches 12 and 22 are cache memories of the MPUs 11 and 21, respectively. Error detection / correction circuit 13, 23
Is cache 1 according to the instruction of each MPU 11, 21.
It is a circuit that performs error detection and error correction of the data read from Nos. 2 and 22.

The error detection / correction circuit 13 includes a cache 12
When an error is detected in the read data from, the interrupt generation circuit 14 in the own processor element 1 and the interrupt generation circuit 24 in the other processor element 2 are notified at the same time that the error is detected through the error notification line 110. Notice. Similarly, the error detection / correction circuit 23 simultaneously notifies the interrupt generation circuits 14 and 24 via the error notification line 120 that an error has been detected.

When the interrupt generation circuits 14 and 24 are notified by the error detection / correction circuit 13 or the error detection / correction circuit 23 that an error has been detected, the interrupt generation circuits 14 and 24 cause the software to recognize that an error has occurred in the MPUs 11 and 21. To generate an interrupt.

The operation of the first embodiment of the present invention will be described with reference to FIG. Since the processor elements 1 and 2 are duplicated and their constituent elements perform exactly the same operation, the operation of the constituent elements of the processor element 1 will be basically described. Each element of the processor element 2 corresponds to a component element of the processor element 1 having the same name.

In the processor element 1, the MPU 11 performs arithmetic processing. By the load / store in this arithmetic processing, data is read from a main memory (not shown) or written in the main memory. A cache 12 is provided to perform this access at high speed. Upon receiving a read request from the MPU 11, the cache 12 sends read data to the error detection / correction circuit 13.

The error detection / correction circuit 13 has a cache 12
Check if there is an error in the data from.
When an error is detected, the error detection / correction circuit 13 notifies the interrupt generation circuit 14 in the own processor element 1 and the interrupt generation circuit 24 in the other processor element 2 simultaneously through the error notification line 110. Notice.

If the detected error is a correctable error, the error detection / correction circuit 13 replies the corrected data to the MPU 11. If it is an uncorrectable error, the processor element 1 becomes a failure and is disconnected from the service, and the other duplicated processor element 2 continues to operate.

In the interrupt generation circuit 14, the error notification line 11
0 to the error detection / correction circuit 13 to the cache 2a
Is notified that there was an error in the read data of
Alternatively, when the error detection / correction circuit 23 notifies that there is an error in the read data of the cache 22 through the error notification line 120, an interrupt for notifying the software that there is an error is executed to the MPU 11.

Therefore, the processor elements 1 and 2 are
Even if an error is detected in one of the two, this interrupt is sent to the MPU 11 by the interrupt generation circuit 14.
The interrupt generation circuit 24 simultaneously executes the MPU 21.

At this point, the erroneous data remains stored in the cache of the processor element in which the error was detected. Therefore, the software that receives the interrupt performs a full cache flush before proceeding to an uncorrectable error.

Here, flushing the cache means that a write is executed from the processor to the cache, and when the data in the main memory and the data in the cache do not match, at least the data in the cache do not match. This is a series of operations in which all the stored data is written back to the main memory to match the data in the main memory with the data in the cache, and all the data in the cache at the time of flushing is invalidated. However, in the present invention, when the cache is flushed, all the data to be written back from the cache to the main memory is sent to the main memory through the error detection / correction circuits 13 and 23. Even if a correctable error is detected in step 1, all the data in the cache that is inconsistent with the error corrected is written back to the main memory.

FIG. 3 is a block diagram showing the configuration of the second embodiment of the present invention. In the figure, the processor elements 3 and 4 are duplicated similarly to the configuration of the first embodiment of the present invention, and therefore have exactly the same components. That is, the processor elements 3 and 4 are MPU3.
1, 41, caches 32 and 42, error detection / correction circuits 33 and 43, address holding means 34 and 44, correction data holding means 35 and 45, and correction data writing means 36 and 46. .

The MPUs 31 and 41 are microprocessors that perform arithmetic processing in the processor elements 3 and 4, respectively. The caches 32 and 42 are cache memories of the MPUs 31 and 41, respectively. Error detection / correction circuits 33 and 43
Is cache 3 according to the instructions of MPUs 31 and 41.
It is a circuit that performs error detection and error correction of data read from Nos. 2 and 42.

The address holding means 34, 44 are MPU 3
The read addresses from the caches 1, 41 to the caches 32, 42 are held. The correction data holding means 35 and 45 hold the read data returned from the error detection and correction circuits 33 and 43 to the MPUs 31 and 41.

When the correction data writing means 36 is informed by the error detection / correction circuit 33 that an error has been detected through the error notification line 130, the fact that an error has been detected by the processor element 3 itself is indicated by the other processor element 4 The correction data writing means 46 is notified.

The correction data writing means 36 is notified by the error detection / correction circuit 33 that an error has been detected, or
Alternatively, when the correction data writing means 46 of the other processor element 4 notifies that an error has been detected in the processor element 4, the address holding means 34
And the write to the cache 32 is executed according to the address and data held in the correction data holding means 35. The correction data writing means 46 has the same function as the correction data writing means 36.

The operation of the second embodiment of the present invention will be described with reference to FIG. Since the processor elements 3 and 4 are duplicated and their constituent elements perform exactly the same operation, the operation of the constituent elements of the processor element 3 will be basically described. Each element of the processor element 4 corresponds to the constituent element of the processor element 3 having the same name.

The processor element 3 causes the MPU 31 to perform arithmetic processing. By loading / storing in the arithmetic processing, data is read from a main memory (not shown) or written in the main memory. A cache 32 is provided to perform this access at high speed. Cash 32
When the MPU 31 issues a read request, sends the read data to the error detection / correction circuit 33.

The error detection / correction circuit 33 uses the cache 32.
Check if there is an error in the data from.
When an error is detected, the error detection / correction circuit 33 notifies the correction data writing means 36 via the error notification line 130 that the error has been detected.

If the detected error is a correctable error, the error detection / correction circuit 33 replies the corrected data to the MPU 31. In the case of an uncorrectable error, the processor element 3 becomes a failure and is disconnected from the service, and the other duplicated processor element 4 continues to operate.

The address holding means 34 holds the read address from the MPU 31 to the cache 32. At this time, the address holding means 34 is stored in the correction data holding means 35.
The data of the address held at is read from the cache 32, and even if the read data has an error, the data whose error is corrected by the error detection / correction circuit 33 is held.

When the correction data writing means 36 is notified by the error detection / correction circuit 33 that an error has been detected through the error notification line 130, the correction data writing means 46 of the other processor element 4 is notified of an error in its own processor element 3. Report that it was detected. Since the correction data writing unit 46 has the same function, the correction data writing unit 36 can recognize the error from the correction data writing unit 46 even when an error is detected in the processor element 4. When the correction data writing means 36 receives an error detection notification from the error detection / correction circuit 33 or the correction data writing means 46, the correction data writing means 36 writes to the cache 32 according to the address of the address holding means 34 and the data of the correction data holding means 35.

At this time, even if an error has occurred in the processor element 4, since the processor element is duplicated, the addresses held in the address holding means 34 and 44 are always the same, and the corrected data holding means is the same. The data held in 35 and 45 and the data in which an error is detected are always the same data since the error is corrected. Therefore, there is no problem in using the address and data held in the own processor element 3.

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 2 is a block diagram showing the configuration of the error detection / correction circuit 13 of FIG. In the figure, the error detection / correction circuit 13 includes an error detection circuit 13a, a syndrome generation circuit 13b, a syndrome decoder 13c, an error correction circuit 13d, and an uncorrectable error detection circuit 13e.
It consists of and. The error detection / correction circuit 23 has the same configuration as the error detection / correction circuit 13 described above.

An example of the first embodiment of the present invention will be described with reference to FIGS. 1 and 2. MP
The U11 and 21 and the caches 12 and 22 are as described in the operation of the above-described first embodiment of the present invention. The error detection / correction circuits 13 and 23 perform ECC for error detection and correction.
An example using the (error check & collection) code is shown in FIG. Normally, a code that can correct a 1-bit error and detect a 2-bit error is used as the ECC code.

In the error detection circuits 13a and 23a (the error detection circuit 23a is not shown), all data bits and all E bits are
Whether or not there is a correctable error is detected by taking the exclusive OR of the CC codes. Error detection circuit 13
The results of a and 23a are output to the error notification line 110 or the error notification line 120 and notified to the interrupt generation circuits 14 and 24.

The syndrome generation circuits 13b and 23b (the syndrome generation circuit 23b is not shown) generate a syndrome according to a predetermined syndrome generation pattern. The syndrome without error is
It is usually all “0”.

The generated syndrome is decoded by the syndrome decoders 13c and 23c (the syndrome decoder 23c is not shown), and the same number of bits as the read data in which only the bit corresponding to the error data is "1". The decoding result of is obtained. Similar to the syndrome, this decoding result is all "0" when there is no error.

The error correction circuit 13 which takes the exclusive OR of the decoding results of the syndrome decoders 13c and 23c and each bit of the read data from the caches 12 and 22.
A correctable 1-bit error is corrected by d and 23d (error correction circuit 23d is not shown).

Uncorrectable error detection circuits 13e, 23e
(Uncorrectable error detection circuit 23e is not shown) detects whether the error is an uncorrectable error of 2 bits or more. Although no error is detected in the error detection circuits 13a and 23a, the syndrome generation circuit 13b,
If the result of 23b is not all "0", or if the results of the syndrome generation circuits 13b and 23b are undefined patterns, it is determined as an uncorrectable error.

Since recovery is impossible when an uncorrectable error is detected, the processor element in which the uncorrectable error is detected is disconnected from the service, and the fault tolerant system is duplicated. The processor element continues processing.

The error correction by the error detection / correction circuits 13 and 23 described above is not necessary unless the data read from the caches 12 and 22 has an error. However,
Depending on the system, it may take several clock cycles to correct the error shown in FIG. 2. In that case, the timing of reply to the MPU 11, 21 differs depending on whether the error is corrected or not.

If the reply timings of the MPUs 11 and 21 are different, there is a problem that the processor element 1 and the processor element 2 are out of synchronization. In order to prevent this, the error detection / correction circuits 13 and 23 always operate to correct the error. That is, the output results of the error correction circuits 13d and 23d are always returned to the MPUs 11 and 21.

When an error is detected in the read data from the caches 12 and 22 by the error detection and correction circuits 13 and 23, in a general system, the error-corrected data is rewritten in the caches 12 and 22. ,
The errors existing in the caches 12 and 22 are corrected. However, in the case where the processor elements 1 and 2 are duplicated, if only one processor element in which an error occurs rewrites the error correction data to the cache, the duplication synchronization is lost. The problem occurs.

Here, the interrupt generation circuits 14 and 24 OR the error notification signals of the error notification lines 110 and 120,
An interrupt is generated in MPU11,21. This interrupt is received by the operating system and, upon recognizing that an error has been detected in the read data from the cache, instructs the caches 12, 22 to be flushed. Instead of rewriting the error-corrected data in the cache, the caches 12 and 22 are flushed at the same time, so that the data including the error is eliminated from the cache without shifting the synchronization of the processor elements 1 and 2.

FIG. 4 is a block diagram showing the structure of the correction data writing means 36 shown in FIG. In the figure, the correction data writing means 36 indicates an error F / F (flip-flop) 3
6a, address register 36b, and data register 3
6c and an OR circuit 36d. The correction data writing means 46 has the same configuration as the above-mentioned correction data writing means 36.

An example of the second embodiment of the present invention will be described with reference to FIGS. 3 and 4. In the first embodiment of the present invention, the data in which an error has occurred is flushed from the cache by flushing the cache by software, whereas in the second embodiment of the present invention, an error occurs when the cache is read. By storing the corrected data and address and simultaneously writing the correction data to the cache in both of the duplicated processor elements, an error on the cache occurs without shifting the synchronization of the duplicated processor elements. Has the function of correcting data.

MPU 31, 41 and cache 32, 4
2 is as described in the operation of the second embodiment of the present invention described above. The error detection / correction circuits 33 and 43 have the same configuration as the error detection / correction circuits 13 and 23 of the first embodiment of the present invention, and are as described in the first embodiment of the present invention. When a correctable error is detected by the error detection circuits of the error detection / correction circuits 33 and 43, the error notification line 13
The corrected data writing means 36 and 46 are notified that an error has been detected through 0 and 140.

When an error is detected in the read data from the caches 32, 42 by the error detection / correction circuits 33, 43, in a general system, the error-corrected data is rewritten in the caches to rewrite them in the caches. Correcting any existing errors.

However, the processor element 3,
In the case where 4 is duplicated, the error correction data is rewritten to the cache only in one of the processor elements in which the error has occurred.
There is a problem that the duplexing synchronization is out of sync. Therefore, not only one processor element but also the cache of both processor elements are rewritten at the same time to correct the data existing in the cache without shifting the duplication synchronization. 3 is shown.

The address holding means 34 and 44 are the MPU 3
The addresses when the caches 32 and 42 are read from the caches 1 and 41 are held. The correction data holding means 35 and 45 hold the data after the errors that can be corrected by the error detection and correction circuits 33 and 43 are corrected.

The detailed structure of the correction data writing means 36 and 46 is as shown in FIG. Correction data writing means 3
In 6, the address held in the address holding means 34 is stored in the address register 36b, and the data held in the corrected data holding means 35 is stored in the data register 36c.
Hold on. The error notification from the error detection / correction circuit 33 through the error notification line 130 is stored in the error F / F 36a.

The correction data writing means 46 of the other processor element 4 is notified that an error has been detected in the read data of the cache 32 of its own processor stored in the error F / F 36a.

The OR circuit 36d ORs the error notification signal of its own processor element stored in the error F / F 36a and the error notification signal from the other processor element 4 to generate an enable signal for writing to the cache 32. . The address to the cache 32 for this write enable signal is the address register 3
6b is the address stored, and the data is the data stored in the data register 36c.

By ORing the error notification of the own processor element 3 and the other processor element 4 by the OR circuit 36d, even if the error occurs in one of the processor elements, both processor elements 3 and 4 simultaneously cache it. A write instruction is given to 32 and 42.

Since the addresses held in the address holding registers 34 and 44 and the data held in the correction data holding means 35 and 45 are always the same, even if an error is detected in another processor unit, its own processor unit. It is permitted to write to the cache using the address and data held in the cache.

As described above, in the duplicated processor element, when an error is detected in the read data from the cache and it is found that the cached data has an error, the duplicated processor element It is possible to remove erroneous data in the cache without shifting the synchronization of the.

[0067]

As described above, according to the cache control circuit of the present invention, the error of the read data from the cache memory storing a part of the contents of the storage device is detected and the detected error is corrected. At the same time, the cache memory is stored in response to an error notification output from another processor element to the write-back means for writing back the stored content of the cache memory whose stored content does not match the content of the storage device due to the writing of data to the storage device. By instructing the contents to be written back to the storage device, even if an error occurs in the cache in the redundant processor element, it is possible to develop an uncorrectable error without shifting the synchronization of the redundant processor element. The effect is that it can be prevented.

Further, according to another cache control circuit of the present invention, an error in the read data from the cache memory storing a part of the contents of the storage device is detected, the detected error is corrected, and Write the data held in the correction data holding unit to the cache memory at the read address held in the address holding unit when at least one of the error notification from the processor element and the error notification from another processor element is input. By giving an instruction, even if an error occurs in the cache in the redundant processor element, it is possible to prevent the uncorrectable error from being developed without shifting the synchronization of the redundant processor element. .

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of an error detection / correction circuit of FIG.

FIG. 3 is a block diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of correction data writing means in FIG.

[Explanation of symbols]

1-4 processor elements 11,21,31,41 MPU 12,22,32,42 cache 13, 23, 33, 43 Error detection and correction circuit 13a error detection circuit 13b Syndrome generation circuit 13c Syndrome Decoder 13d error correction circuit, 13e Uncorrectable error detection circuit 14, 24 Interrupt generation circuit 34,44 address holding means 35, 45 correction data holding means 36,46 Correction data writing means 36a Error F / F 36b address register, 36c data register 36d OR circuit 110, 120, 130, 140 Error notification line

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-4-211841 (JP, A) JP-A-63-278162 (JP, A) JP-A-6-266574 (JP, A) JP-A-5- 265790 (JP, A) JP-A-6-35736 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 12/08 G06F 11/16 G06F 12/16

Claims (3)

(57) [Claims] 1. A cache memory that stores a part of the contents of a storage device, and a write-back process that writes back the stored contents of the cache memory to the storage device, the storage contents of which do not match the contents of the storage device due to the writing of data. A cache control circuit of an information processing system, comprising first and second processor elements, which include a returning means and operate in synchronization with each other, wherein an error of data read from the cache memory is detected and the detected error is detected. Error detecting and correcting means for correcting the error, and the storage content of the cache memory to the write back means in response to an error notification output from the error detecting and correcting means and the error detecting and correcting means of another processor element. An instruction means for instructing to write back to the first and second processor elements Yes people to
And, the write-back means, the cache eyes became a mismatch
When the contents stored in the memory are written back to the storage device, the error
-Correction of correctable errors detected by the detection and correction means
The cache control circuit is configured to be written back to the storage device after being stored . 2. The instructing means is configured to output to the rewriting means an interrupt signal for instructing to rewrite the contents stored in the cache memory to the storage device. Cache control circuit. 3. A cache control circuit of an information processing system, comprising a cache memory for storing a part of contents of a storage device, and comprising first and second processor elements operating in synchronization with each other, wherein the cache memory Error detection and correction means for detecting an error in read data from the memory and correcting a detected correctable error, address holding means for holding a read address of the cache, and the error detection and correction means for detecting the error. Error correction from the error detection and correction means of the own processor element and error notification from the error detection and correction means of another processor element are input. Sometimes, the address stored in the address storage means is used to correct the Each of the first and second processor elements has means for instructing to write the data held in the data holding means in the cache memory in synchronization with another processor element, Of the first and second processor elements by disconnecting one of the first and second processor elements when an uncorrectable error is detected by the error detection and correction means of one of the processor elements of A cache control circuit characterized in that the other one of them continues processing.