JP3420134B2 - D / A conversion system and D / A conversion method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oversampling D / A converter used as D / A conversion used in a voice codec such as a mobile phone and an audio system, and more particularly to a delta for performing 1-bit quantization. The present invention relates to a D / A conversion system and a D / A conversion method for performing D / A conversion from a sigma modulation output.

[0002]

2. Description of the Related Art A conventional D / A conversion system using an oversampling D / A converter will be described with reference to the drawings.

FIG. 3 shows a conventional circuit configuration in which the output of the noise shaper is output by 1 bit (referred to as "first conventional example"). Further, FIG. 4 shows a conventional circuit configuration in which the output of the noise shaper is output in a plurality of bits (P bits) (referred to as a "second conventional example").

The configuration of the first conventional example will be described with reference to FIG. The first digital signal is input, noise shaping for moving the noise component to the high frequency side is performed by delta sigma modulation, and the noise shaper 10 that outputs the 1-bit second digital signal and the second digital signal are output. A 1-bit D / A converter 31 that inputs and converts a digital signal to an analog signal and outputs a first analog signal, and a first analog signal that is input The post filter 41 is configured to attenuate high frequency noise and output a second analog signal.

Here, the noise shaper 10 converts quantization noise, which is generally distributed in white (a noise level that is uniform with respect to frequency), into a frequency-dependent distribution. And a differentiator,
By inputting a signal with a spectrum distribution in the low frequency region, increasing the gain in the low frequency region with the integrator, superimposing white quantization noise with the quantizer, and emphasizing the high frequency region due to the differential characteristic with the differentiator. Although the input spectrum distribution and the output spectrum distribution are almost the same, only the differentiator acts on the quantization noise to increase the S / N in the low frequency region. In the D / A converter, since the noise shaper is composed of a digital circuit, it is not divided into an integrator, a quantizer, a differentiator and a noise shaper circuit, and a flip-flop and an adder are used to remove the noise shaper. Constitute. Further, the configuration of the noise shaper is quite common in this field, and thus its details are omitted.

Incidentally, one of the A / D and D / A conversion techniques is an oversampling technique, and one of the modulation methods used for the oversampling technique is a delta sigma modulation technique. The A / D and D / A converter used is called a delta sigma modulator. This is also called a noise shaping converter. In other words, the noise shaper is one of A / D and D / A converters using the oversampling technique.

Next, the configuration of the second conventional example will be described with reference to FIG. Inputs the first digital signal, performs noise shaping to move the noise component to the high frequency side by delta-sigma modulation, and outputs a second digital signal of multiple bits (P bits, where P is an integer of 2 or more). P-bit D / A converter 3 that inputs the noise shaper 12 and the second digital signal, converts the digital signal into an analog signal, and outputs the first analog signal.
2 and a post filter 42 that inputs the first analog signal, attenuates the high frequency noise of the first analog signal, and outputs the second analog signal.

Here, the A / D converter described in comparison with the D / A conversion circuit will be described. A delta-sigma modulation type A / D converter by oversampling is well known, and is disclosed in, for example, Japanese Patent Laid-Open No. 6-53836, Japanese Patent Laid-Open No. 9-326703, and Japanese Patent Laid-Open No. 11-1.
No. 63731. In each of these publications,
The input analog signal is sequentially converted into digital data through a subtractor, an integrator, and a 1-bit AD conversion circuit, and its output is negatively fed back to the input side through a 1-bit digital-analog conversion circuit for 1 clock. By calculating the difference (delta) between the analog signal reconverted to the previous digital data and the input analog signal at the input section, integrating (sigma), and then quantizing with an extremely high sampling frequency (oversampling), It is converted into digital data.

The delta-sigma modulation type A / D converter by oversampling and the D / A converter are basically the same. The difference is that the delta-sigma modulator of the A / D converter is an analog circuit that forms an integrator, quantizer, and differentiator, while the delta-sigma modulator of the D / A converter is integrated by a digital circuit. And quantizer and differentiator. Therefore, although it is needless to compare with the A / D converter, it has been described for reference.

The operation of the first conventional example will be described with reference to FIGS. 3 and 5. When the input including the main signal component is supplied to the first digital signal, the second digital signal output from the noise shaper 10 has a spectrum as shown in FIG. F shown in FIG. 5 (A)
s is the sampling frequency of the noise shaper 10. As shown in FIG. 5A, a large amount of noise components are distributed on the high frequency side, and the post filter 4
By configuring 1 with a high-order filter, as shown in FIG. 5B, the main signal component can be the main component and the noise on the high frequency side can be attenuated.

Next, the operation of the second conventional example will be described with reference to FIGS. 4 and 5. When the input including the main signal component is supplied to the P-bit first digital signal, the second digital signal output from the noise shaper 12 has a spectrum as shown in FIG. 5C. As shown in FIG. 5C, since the second digital signal has a plurality of bits, the high frequency noise component is smaller than that in FIG. 5A. As a result, the post filter 42 has a filter configuration of a lower order than the post filter 41, and
It can have a spectrum equivalent to that of (B).

[0012]

However, in the first conventional example (see FIG. 3), when a no signal is continuously input to the first digital signal, a noise shaper of 1-bit output is generated. As shown in FIG. 5D, the spectrum of the second digital signal output from 10 outputs a certain signal frequency fi, so the frequency fi
Noise is generated. This is because the output value is only "+1" or "-1" because it is a 1-bit output, and "+1" and "-1" are repeated in a cycle of a certain signal frequency fi.

As a concrete example, the noise shaper 10 is a second-order delta-sigma modulator, and the sampling frequency is 1024.
When set to [KHz], the second digital signal is "+1,
Values of +1, -1, -1, +1, +1, -1, -1 "are output, which is output as a harmonic signal of 256 [KHz]. Also, a large amount of noise components are distributed on the high frequency side. Therefore, in the post filter 41, in order to attenuate noise on the high frequency side, a high-order filter having a high attenuation characteristic composed of a complicated analog circuit is required, and the analog circuit scale of the post filter 41 is large. There is a problem of becoming.

In the second conventional example (see FIG. 4), since the second digital signal has a plurality of bits, the spectrum of the second digital signal is as follows even when no signal is continuously input. As shown in FIG. 5E, the noise on the high frequency side is also reduced as compared with the first conventional example. Further, since the signal of the specific frequency is not output, the noise characteristic is better than that of the first conventional example. However, since the second digital signal has multiple bits, D of multiple bits
There is a problem that the configuration scale of the / A converter 32 becomes large. Further, when the noise shaper 12 for outputting a plurality of bits and the D / A converter 32 for a plurality of bits are different LSIs, there is a problem that the number of input / output terminals of each LSI increases.

Therefore, an object of the present invention is to provide a D / A conversion system which outputs a noise shaper with 1 bit, has a small circuit scale of a D / A converter and a post filter, and is excellent in noise characteristics.

[0016]

In order to achieve such an object, according to the present invention, a first digital signal is input and noise shaping is performed by a delta sigma modulation technique.
A noise shaper that outputs a second digital signal of bits and an output of the noise shaper that outputs a third digital signal of M bits (M is an integer of 2 or more) are N taps (N is 2 A moving average filter composed of the above integers), an M-bit D / A converter connected to the output of the moving average filter and outputting a first analog signal, and the M-bit D / A converter is the connection to the output, and post filter for outputting a second analog signal attenuates high frequency noise of the first analog signal, comprising a front
The moving average filter composed of N taps has the number of taps.
N D-types that are cascaded to each other by the amount equivalent to N
Between the flip-flop and the D-type flip-flop
Adder that adds outputs and decodes the output of the adder
Providing D / A conversion system is characterized in that a decoder circuit for.

Further, the D / A method according to the present invention is a noise shaper step of inputting the first digital signal, performing oversampling by the delta sigma modulation technique to perform noise shaping, and outputting a 1-bit second digital signal. And an N tap (N is an integer of 2 or more) inputting a 1-bit second digital signal by the noise shaper and outputting an M-bit (M is an integer of 2 or more) third digital signal. A moving average step of sequentially outputting an average value by a moving average filter composed of a shift register, and an M-bit D / which inputs an M-bit third digital signal by the moving average filter and converts it into a first analog signal. A
A conversion step; and a filtering step of inputting the first analog signal of the M-bit D / A converter and outputting a second analog signal that attenuates a high frequency region of the first analog signal. It is characterized by

The moving average filter composed of the N taps performs addition of N D type flip-flops connected in cascade corresponding to the number of taps N and outputs of the D type flip-flops, It is provided with an adder that outputs the result in M bits, and a decoder circuit that outputs the result of subtracting the output of the adder by a half of the number N of taps.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows a block diagram of an embodiment of the present invention. FIG. 2 shows a configuration diagram of an embodiment of the moving average filter 20 configured by the N taps (N is an integer of 2 or more) shown in FIG.

In FIG. 1, the noise shaper 10 has a first
The digital signal of 1 is converted into a 1-bit digital signal by delta sigma modulation, and a 1-bit second digital signal is output. The moving average filter 20 calculates moving average data based on the bit stream data of the second digital signal. Specifically, the data value "1" of the bit stream data is associated with "1", the data value "-1" is associated with "0", and the N values of the associated N taps are added. Generate moving average data. The D / A converter 30 converts the M-bit third digital signal output of the moving average filter 20 into a digital signal and outputs a first analog signal. The post filter 40 inputs the first analog signal and outputs the second analog signal by a filter that attenuates a high frequency component having a simple inclination characteristic of about 6 dB or 12 dB.

The 1-bit output noise shaper 10 shown in FIG. 1 performs the same operation as in the first conventional example shown in FIG. 3 and can perform 1-bit output by oversampling. Next, in the present embodiment, the 1-bit second digital signal output from the noise shaper 10 is input, and the shifter of the N tap (N is an integer of 2 or more) shifter, the adder, and the decoder are configured. Has been
Moving average filter 20 that outputs a third digital signal of M bits (M is an integer of 2 or more), and D / A conversion that inputs a third digital signal of M bits and outputs a first analog signal And a post filter 40 for inputting the first analog signal and outputting a second analog signal obtained by attenuating the high frequency noise of the first analog signal.

Further, as shown in FIG. 2, the moving average filter 20 composed of N taps includes N D-type flip-flops 22 (1 to N) connected in cascade corresponding to the number N of taps. , D type flip-flop 2
2 (1 to N) outputs are added and an M-bit addition result is output, and the output result of the adder 23 is subtracted by half the number N of taps, and the result is output as M bits. And a decoder circuit 24.

The operation of the D / A conversion system shown in FIG. 1 will be described below.

The second digital signal, which is a 1-bit output signal of the noise shaper 10, is input to the moving average filter 20. The moving average filter 20 has N D-type flip-flops 22 cascaded with each other by the number of taps N with the sampling frequency fs as CLK.
(1 to N), "1" when the second digital signal is "+1", and "0" when the second digital signal is "-1".
Take in as. The captured result is the N-bit signal A
DDIN [1], [2]-[N-1], [N] are output to the adder 23 for each sampling period. In the adder 23, ADDIN [1], [2] --- [N-
1] and [N] are added to adjacent bits, and ADDOUT [1], ADDOUT [1], of the addition result signal of M bits is added.
[2]-[M-1] and [M] are output. ADDOU
In the decoder circuit 24 for inputting T [1], [2]-[M-1], [M], the input value is subtracted by half the number of taps N, and the result is M bits. Output as a third digital signal of the M-bit D / A converter 3
After being input to 0, the post filter 40 attenuates high frequency noise.

The spectrum of the second digital signal, which is the 1-bit output signal of the noise shaper 10, becomes a spectrum as shown in FIG. 5 (D) as in the first conventional example, and a certain signal frequency fi is output. Frequency f
i noise is generated.

In order to attenuate this frequency fi with the moving average filter, if the sampling frequency of the noise shaper 10 is fs, then (fi / fs) × n (n is an integer)
By configuring the moving average filter with the number of taps N of the value obtained in, the frequency component of fi can be deleted with a simple characteristic.

As a specific example, when no signal is continuously input to the first digital signal, the noise shaper 10
2nd-order delta-sigma modulator, sampling frequency 1
When set to 024 [KHz], the second digital signal has
"+1, +1, -1, -1, +1, +1, -1, -1"
Is output as a signal of a harmonic of 256 [KHz]. When the number of taps of the moving average filter 20 is (256/1024) × 16 = 4 taps, the value of the D type flip-flop 22 (1 to 4) is always two “+1” and two “0”. Therefore, the value ADDOUT [4: 1] of the adder 23 is always "+2". Then, by the decoder circuit 24, the third
The digital signal of is + 2- (the number of taps is 4/2) = 0 and always has a value of "0", so that the signal component of 256 [KHz] is deleted. FIG. 5F shows the spectrum of the third digital signal which is the output of the moving average filter 20. The signal component of 256 [KHz] is attenuated,
Furthermore, high frequency noise is also attenuated.

Also in comparison with the second conventional example, the D / A converter 30 of the M-bit input is the same as the D / A converter 32 of the P-bit input shown in the second conventional example, that is, M = P
In this case, in the present invention, the noise on the high frequency side is attenuated by the amount passing through the moving average filter 20. Actually, since it is sufficient to obtain a spectrum equivalent to that of the second conventional example, M <P
Since the D / A converter 30 can be configured according to the above relationship, the circuit scale can be made smaller than the D / A converter 32 of the second conventional example. Specifically, m is 14 bits or more, M
Is preferably 8 bits or less.

[0029]

As described above, according to the present invention,
The noise shaper outputs 1 bit to emphasize the high frequency component, the subsequent processing is simplified, and the circuit scale of the moving average filter, D / A converter, and post filter is small, and the noise characteristics are excellent. Have.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a D / A conversion system of the present invention.

FIG. 2 is a circuit configuration diagram of a moving average filter 20 shown in FIG. 1 of the present invention.

FIG. 3 is a block diagram showing a configuration of a first conventional example.

FIG. 4 is a block diagram showing a configuration of a second conventional example.

FIG. 5: D according to the present invention, the first conventional example, and the second conventional example
It is an operation explanatory view of a / A conversion system.

[Explanation of symbols]

10, 11 noise shaper 20 Moving average filter 22 (1-N) DFF 23 adder 24 Decoder circuit 30, 31, 32 D / A converter 40, 41, 42 Post filter

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H03M 3/02 H03H 17/02

Claims (3)

(57) [Claims] 1. A noise shaper for inputting a first digital signal, performing noise shaping by a delta-sigma modulation technique, and outputting a 1-bit second digital signal, and a 1-bit second noise shaper of the noise shaper. A moving average filter composed of N taps (N is an integer of 2 or more) for inputting a digital signal output and outputting a third digital signal of M bits (M is an integer of 2 or more); An M-bit D / A which inputs the M-bit third digital signal output of the averaging filter and outputs a first analog signal
A converter and a post filter for inputting the first analog signal output of the M-bit D / A converter and outputting a second analog signal in which high-frequency noise of the first analog signal is attenuated. comprising, moving average filter that is composed of the N taps, the tap
N D-ties cascaded to each other by the number N
Flip-flop and the D-type flip-flop
The output of the adder and the output of the adder
And a decoder circuit for
Conversion system. Wherein said decoder circuit comprises from the value entered by M bits, according to claim 1, further comprising a circuit for outputting the result of subtraction of half the value of the number of taps N D / A conversion system. 3. A noise shaper step of inputting a first digital signal, performing oversampling by a delta-sigma modulation technique to perform noise shaping, and outputting a 1-bit second digital signal; The second digital signal is input and M bits (M
Is an integer greater than or equal to 2) N which outputs the 3rd digital signal.
A moving average step of outputting a successive average value by a moving average filter configured by a tap (N is an integer of 2 or more) shift register, and a first M-bit third digital signal input by the moving average filter are input. M-bit D / A conversion step for converting into an analog signal of
The first analog signal of the A converter is input and the first analog signal is input.
Comprising a filter step of outputting the second analog signal attenuate high frequency region of the analog signal, wherein the moving average process is dependent contact one bit of digital signals
Sequential shift is performed by the subsequent shift register
Respective output is added by the adder of the N taps, the pressure
The output of the calculator is converted into M-bit data by the decoder circuit
D / A converter wherein the that.