JP3413740B2 - Multi-frequency compatible display with automatic white balance correction function - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device such as a computer terminal, and more particularly to automatic white balance correction of a display capable of displaying video signals having different horizontal and vertical scanning frequencies output from various computers and video output devices.

[0002]

2. Description of the Related Art In a display device using a cathode ray tube such as a television receiver or a computer display,
The black level of the displayed image or the luminance ratio of the three primary colors of red, blue, and green in the high-luminance white portion may deviate from a predetermined value due to the effect of aging, temperature drift, or the like. Therefore, many television receivers and the like having an automatic white balance adjusting function have been proposed so far so that the black level and the display color of the displayed image and the color temperature of the reference white do not deviate from a predetermined value.

As the above example, for example, Japanese Patent Publication No. 6-957.
No. 66, JP-A No. 61-98089, and the like. The operation in the above conventional example is to insert a reference signal of a predetermined level generated inside the display into a predetermined portion of a vertical blanking period (a period in which there is no signal to be displayed on the cathode ray tube) of a video signal input to the display. ,
Detection of the cathode current flowing through the cathode ray tube in the reference signal portion is performed at the video circuit output section of the display.

Next, the detected value of the cathode current is compared with a preset predetermined reference value, and the gain and DC level of the video circuit are adjusted so that they match. The above adjustment is carried out in the same manner for each color of red, blue and green. By the above, the luminance balance of the red, blue, and green components displayed on the cathode ray tube is adjusted to a predetermined value, and the above deviation can be corrected.

On the other hand, at present, the display can display an appropriate image in accordance with various image signal specifications (for example, image scanning frequency, image display period, image blanking period, front porch period, back porch period, etc.). The so-called multi-scan display is used, and it is essential that the display can support various video signals.

However, in the above-mentioned conventional example, sufficient consideration has not been given to support various video signal specifications. In other words, the display generally uses the underscan method for displaying the video signal in the cathode ray tube, so that the reference signal may interfere with the display depending on the insertion position of the reference signal, or the cathode current may not be detected correctly. There is a possibility that you cannot do it.

Further, at present, the scanning frequency of the video signal is shifting to a higher one, and therefore the blanking period of the video signal in which the reference signal can be inserted in the display is becoming shorter.

Therefore, in the case of supporting various video signal specifications, it is inconvenient for the above-mentioned conventional example to support it as it is, and in some cases, it becomes difficult to secure the performance of white balance adjustment.

[0009]

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to reduce display interference caused by a reference signal for white balance correction even when video signals having various scanning frequencies and different display resolutions are input. An object of the present invention is to provide a display that automates the setting of the insertion position of the reference signal.

[0010]

In order to solve the above problems, a reference signal inserting means, a timing generating means for setting a reference signal inserting position or a signal width, and a video signal specification detecting means in a multi-frequency compatible display. And a control means.

Here, the reference signal inserting means performs an operation of inserting a reference signal pulse for white balance correction into the video signal input to the display, and the timing generating means performs the pulse insertion timing of the reference signal inserting means. And an operation of setting a pulse width, the video signal detecting means performs an operation of detecting or generating the signal specification of the video signal input to the display, and the control means controls the timing generating means so as to correspond to the signal specification. By operating as appropriate control, the reference signal insertion position and signal width for white balance correction are adjusted to the input video signal,
Optimize.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a block diagram of a display showing a first embodiment of the present invention. In the figure, 1 is a video signal input terminal, 2 is a reference signal insertion circuit for inserting a reference signal for performing automatic white balance correction, 3 is a video circuit, and contrast and brightness adjustment,
It is composed of a video pre-stage that performs gain adjustment and the like for each of the RGB channels independently and a video output stage that drives the cathode ray tube by increasing the video signal amplitude and setting the DC level.

4 is a diode, 5 is a resistor, 11 is a PNP
Type transistor, 12 is a resistor, 20 is a sample and hold circuit, 19 is an analog / digital conversion circuit (hereinafter referred to as A
/ D circuit), which form a circuit portion for detecting the cathode current flowing through the cathode ray tube. Reference numeral 6 is a deflection yoke, and 7 is a cathode ray tube, which is the same as a normal display. Reference numeral 8 denotes a timing generation circuit, which controls the insertion timing of the reference signal and the sampling timing of the sample hold circuit.

Reference numerals 9 and 10 denote digital / analog conversion circuits (hereinafter referred to as D / A circuits), which perform gain adjustment and DC level adjustment of the above video circuit with a DC voltage. Reference numerals 13 and 14 are horizontal and vertical sync signal input terminals, respectively, and 15 is a polarity unifying circuit for unifying the polarities of the horizontal and vertical sync signals input to the display to either negative or positive.

Reference numeral 16 is a signal identification for receiving the polarity information of the sync signal output from the polarity unifying circuit 15 and the sync signal having a uniform polarity to judge the signal specifications such as the scanning frequency and the display period of the input video signal. Reference numeral 17 denotes a circuit, which is a timing generating circuit or D /
The control circuit outputs control information to the A circuits 9 and 10 and the like. Here, the signal identifying circuit 16 and the control circuit 17 can be configured by the CPU circuit 18.

Reference numeral 21 denotes a control panel provided on the front surface or the lower portion of the display, which is composed of a push switch or the like through which a user of the display inputs a white balance correction instruction or the like. Reference numeral 22 is a multi-frequency-compatible deflection circuit that can support various video signal specifications.

In FIG. 1, the video signal path of the video circuit 2 and the like is shown for one of the three primary color video signal channels. However, in reality, the reference signal insertion circuit, the video circuit, and the cathode current detection are shown. It goes without saying that a circuit, a sample hold circuit, an A / D circuit, and a D / A circuit are required for each three channels. Further, the signal lines described thicker than the normal signal lines in the configuration diagrams of FIG. 1 and subsequent figures are signal lines composed of at least two signals.

The operation of the display of FIG. 1 will be described below. The signal identifying circuit 16 identifies the signal specification of the video signal from the polarity, frequency or period information of the sync signal output from the polarity unifying circuit 15. Based on the identification result, the control circuit 17 is a reference for performing white balance correction. The insertion position information of the signal is generated. The insertion position information is given to the timing generation circuit 8 to generate a timing signal of the reference signal insertion position for the reference signal insertion circuit 2.

Here, the signal identification circuit 16 and the control circuit 1
Reference numeral 7 can be constituted by a processor LSI, a so-called CPU circuit, which case is shown by a dotted line portion 18. In accordance with the timing signal, the reference signal inserting circuit 2 inserts the high luminance level reference signal and the low luminance level reference signal into the video signal.

After the video signal having the signal inserted is processed by the video circuit 3, the cathode current at the reference signal position is detected by the emitter follower circuit composed of the transistor 11 and taken out by the resistor 12 as a detection pulse. The pulse hold value of the pulse at the reference signal position is held by the sample and hold circuit 20, and is sent to the control circuit 17 as digital data by the A / D circuit 19.

The control circuit 17 compares the output data of the A / D circuit 19 with reference data stored in advance,
The D / A circuits 9 and 10 are controlled so that they match each other. The D / A circuits 9 and 10 are respectively connected to the video circuit 2
Adjust the video signal gain and DC level of. Here, the high brightness level reference signal is used for gain adjustment of the video signal, and the low brightness level reference signal is used for DC level adjustment of the video signal. As described above, the value of the cathode current flowing through the cathode ray tube 7 is corrected to the reference value, and the display color of the display image is readjusted as in the initial adjustment, so that the influence of drift or the like can be canceled.

Here, if the white balance correction operation is always performed on an underscan type display, it may be recognized as display interference due to the bright line of the reference signal portion. The user operates by inputting a correction request. The request signal is sent to the control circuit 17 to start the above correction operation. The types of correction requests include a case where the correction operation is performed only when a request is input to the control panel, and an automatic correction operation in which the correction is performed for each predetermined time operation of the display at a predetermined time interval input from the control panel. Can be set.

The timing relationship in the above operation is shown in FIG.
Is shown in the waveform diagram of. In FIG. 3, the video signal specification is judged from the vertical synchronizing signal V1 and the horizontal synchronizing signal H1 which have been subjected to the unified polarity, and the reference is made in the period excluding the horizontal blanking period Hb1 immediately after the end of the vertical blanking period Vb1 in the deflection circuit 22. Signal R
It is operating to insert 1.

Further, a sample hold pulse TH1 for the sample hold circuit 20 is generated within the pulse period of the reference signal R1. Although not shown in FIG. 1, the sample hold pulse TH1 is generated by the timing generation circuit 8 and output to the sample hold circuit 20. The timing relationship in FIG. 3 shows the case where the period TFP from the end of the vertical blanking period to the start of the video signal d1 is equal to or greater than a predetermined value on the time basis or the number of horizontal scanning lines.
In this case, since the inserted reference signal exists at a time point sufficiently earlier than the video signal start time, the reference signal does not interfere with the display image itself as a bright line.

Further, in recent years, the display area of the display has been expanded, and the display image is displayed in the full displayable area of the cathode ray tube 7, so that the reference signal is at the top of the cathode ray tube 7 or at a position outside the display area. Will be detected.
Further, the reference signal R1 of FIG.
This is an example in which the video circuit 3 is inserted over the lines and the gain adjustment and the DC level adjustment of the video circuit 3 are performed at the same time, but two lines are required as the insertion period.

Therefore, in order to further shorten the insertion period of the reference signal and reduce the influence on the displayed image, it is considered to display the high brightness level and the low brightness level at the same position as the reference signal R3 in FIG. To be In this case, in the display of FIG. 1, for example, only the high-brightness level reference signal is inserted, the gain of the video circuit 3 is adjusted, and then the low-brightness level reference signal is inserted to adjust the DC level. Hereinafter, such adjustment is repeated until the cathode current data detected by the A / D circuit 19 matches the target value. Therefore, the display image is less affected by the reference signal.

Next, FIG. 4 shows the video signal d from the vertical blanking period.
It shows the timing relationship when the period up to 2 is shorter than the predetermined period. In this case, the vertical blanking period Vb1 does not change because it is set to a predetermined value by the design value of the deflection circuit 22 of the display regardless of the video signal specifications, but when the video signal input to the display changes, the vertical blanking period Vb1 changes. The period TFP from the end of Vb1 to the start of the video signal d2 may change, and the period in which the reference signal can be inserted may be lost.

In such a case, the control circuit 17 and the timing generation circuit 8 are provided with respect to the reference signal insertion circuit 2.
Control is performed so that the signal insertion position is changed to the blanking period at the bottom of the display screen. Therefore, the reference signal is inserted within the vertical blanking period after the display of the video signal d2 is completed and before the vertical retrace of the deflection circuit 3 is started.
In this case, a bright line due to the reference signal may appear at the bottom of the screen, but as described above, when trying to maximize the display area of the video signal, it does not appear outside the displayable area of the cathode ray tube 7. .

Even when the display area is not enlarged, a computer image displayed on the display often has a menu mainly for software processing, control, or operation at the top of the screen. However, since the gazing point of the display user is directed toward the upper part of the screen, the degree of recognition of the interference by the reference signal is reduced.

FIG. 13 shows a control flow chart when the signal identifying circuit 16 and the control circuit 17 in FIG.

Each control flow STEP1 to STEP14 is the same as that of the operation of FIG. 1, but as a supplementary operation, STEP1.
3 to 6 are described. In STEP 3, the video signal identification operation is performed, and when the corresponding signal specifications are found, the control circuit 17 reads the reference signal insertion position information held in advance and controls the timing generation circuit 8.

However, if the signal specifications cannot be found, the specified value held in advance is read out, and the control circuit 17 controls the timing generation circuit 8 to generate the reference signal. At this time, if the reference signal position is not appropriate, in STEP 6, the control panel 21 gives an instruction to adjust the reference signal insertion position, and the control circuit 17 controls the timing generation circuit 8 based on this instruction to obtain an appropriate position. To adjust. The operations from STEP7 to STEP14 will be omitted because they are the same as the operation described in FIG. Further, in FIG. 13, the DC level adjustment is performed after the gain adjustment of the video circuit 3, but the control can be reversed. Furthermore, it is of course possible to perform the gain adjustment and the DC level adjustment at the same time.

Next, FIG. 2 shows the details of the reference signal insertion circuit 2. The video signal input from the video signal input terminal is added to the reference voltage source 25 or 26 output from the switch circuit 24 in the addition circuit 23. Then, a video signal in which a reference signal pulse for white level correction is inserted is obtained. The control signal of the switch circuit 24 is supplied from the timing generating circuit 8 and the reference signal inserting operation as described above is performed.

FIG. 5 is a block diagram showing another embodiment of the reference signal insertion circuit 2. In the figure, the difference from FIG. 2 is that the output DC voltage of the D / A converter is used instead of the voltage sources 25 and 26 as the reference signal. The output voltages of the D / A converters 27 and 28 are set at the time of initial adjustment of the display, and the optimum value is selected for each display. D /
Since the A converter is used, the initial adjustment can be performed from the CPU, which shortens the adjustment time.

FIG. 6 is a block diagram showing a second embodiment according to the present invention. In the figure, the same symbols as those in FIG. 1 have the same functions. The difference from FIG. 1 lies in the video signal position detection circuit 29. The operation of FIG. 6 will be described below with reference to the waveform chart of FIG. 7.

The video signal position detection circuit 29 is supplied with the horizontal and vertical sync signals H1 and V1 and the video signal D1 which have been subjected to the polarity unification processing and are output from the polarity unification circuit 15. The number of lines and time indicating the ranking period and the front porch period from the synchronization signal to the start of the video signal are measured.

In the example of the waveform diagram of FIG. 7, the vertical and horizontal front porch periods TVP and THP are measured. This measurement result is output to the signal identification circuit 16 as video signal data relating to the video signal specifications. The signal identification circuit 16 is
Based on the video signal data, the horizontal and vertical sync signals, and the sync polarity information, it is determined whether the video signal input to the display is a known signal or a completely new signal.

In the case of a known signal, the subsequent operation is the same as in the case of FIG. When it is determined that the video signal data is new data, the signal identification circuit 16 determines the video signal specifications (video scanning) based on the detection result of the video signal position detection circuit 29 and the cycle or frequency of the sync signal output from the polarity unifying circuit 15. Frequency or period, video blanking period, front porch period, etc.) are automatically generated. This signal specification is output to the control circuit 17, and the subsequent operation is shown in FIG.
Similarly, the timing generation circuit 8 and the like are controlled to perform automatic white balance correction.

In FIG. 7, the control circuit 17 determines that the vertical blanking period V
It is determined that the period from the end of b1 to the start of the video signal D1 is equal to or more than a predetermined value, and the reference signal is inserted immediately after the end of the vertical blanking period Vb1. This reference signal is inserted during the horizontal and vertical blanking periods of the video signal D1. Therefore, the reference signal insertion period is set to be the same as the horizontal display period TH of the video signal. The above is the operation of FIG. 6, but in FIG. 6, the newly created video signal specifications are held in the signal identification circuit 16 and used as signal identification data for the next automatic white balance correction control and thereafter. Is also possible.

FIG. 14 is a control flow chart when the signal identifying circuit 16 and the control circuit 17 of FIG. 6 are constituted by the CPU 18. The CPU 18 determines the reference signal insertion position from the video signal information detected in STEP 2'and generates insertion position information. In STEP 7, the reference signal insertion position information is sent to the timing generation circuit 8 and the reference signal insertion circuit 2
Is controlled to insert a reference signal at the determined position. With the above operation, the insertion position of the reference signal can be automatically determined regardless of the video signal. Subsequent operations are exactly the same as the processing from STEP7 onward in the flowchart in FIG.

Next, FIG. 8 is a block diagram of the video signal position detection circuit 29 in FIG. In the figure, reference numeral 30 denotes a video signal detection circuit, which detects a location where a video signal input to the display exists. Reference numeral 31 is a horizontal front porch period detection circuit, which detects a period from the horizontal synchronizing signal to the start of the video signal and outputs the detected value as digital data. A vertical front porch period detection circuit 32 detects the period from the vertical synchronization signal to the start of the video signal, and outputs the detected value as digital data, like the horizontal front porch period detection circuit 31. The signal identification circuit 16 generates a video signal specification based on the detection data.

Next, FIG. 9 shows a third embodiment according to the present invention. In the figure, the same symbols as those in FIG. 1 have the same functions. In FIG. 9, reference numeral 34 is a timing generation circuit, which is slightly different in operation from the timing generation circuit 8 shown in FIG. The operation of FIG. 9 will be described below with reference to the waveform chart of FIG.

In FIG. 9, horizontal and vertical blanking pulses obtained from the deflection circuit 22 are used as reference signals for determining the reference signal insertion period. That is, the signal identification circuit 16 determines the signal specifications of the video signal D1 from the horizontal and vertical sync signals having the unified polarity and the polarity information, and the period from the vertical blanking period Vb1 to the start of the video signal D1 is equal to or more than a predetermined value. In this case, as shown in FIG. 10, the timing generation circuit 34 operates so as to insert the reference signal in synchronization with the falling edge of the horizontal blanking pulse immediately after the end of the vertical blanking period. The reference signal insertion period TH at this time is set to a value instructed by the control circuit 17. The operation of each circuit thereafter is shown in FIG.
Is the same as.

Further, FIG. 11 shows a fourth embodiment according to the present invention. In the figure, reference numeral 35 is a gain control circuit, 36 is a 1OSD signal generation circuit for supplying an OSD signal for performing on-screen display on a video signal, 37 is a video circuit with an OSD input function, and the same reference numerals as those in FIG. Things have the same function.

11 is different from that of FIG. 1 in that a so-called on-screen display function for displaying a menu such as display adjustment of a display is also used as a reference signal insertion function. In FIG. 11, if there is an instruction input for performing automatic white balance correction on the control panel, the control circuit 17
Starts the white balance correction operation according to the instruction.

At this time, the control circuit 17 generates position information for generating a reference signal for white balance correction from the video signal specifications obtained by the signal identification circuit 16 performing the same operation as in FIG. 1, and the OSD signal generation circuit. Output to 36. The OSD signal generation circuit 36 generates an OSD signal as a reference signal based on the position information from the control circuit 17.

Since the OSD signal generally has only a constant signal level, the gain control circuit 35 adjusts the OSD signal level. As an adjusting method, for example, when a high-brightness reference signal for adjusting the gain of the video circuit 37 is generated, the OSD signal is set to the maximum input signal level to the video circuit 37. When the DC level of the video circuit 37 is adjusted, the reference signal level output from the OSD signal generation circuit 36 is switched to a predetermined level by the gain control circuit 35 and is inserted into the video circuit 37 as a low brightness reference signal.

FIG. 12 is an example of a screen showing the case where the reference signal by the OSD is inserted in the video signal. As shown in the figure, when the user of the display operates the control panel 21 of the display to start the automatic white balance correction, the display during the adjustment is displayed on the screen, and then the high brightness reference signal and the low brightness reference signal are displayed. Is displayed. In this case, since the automatic white balance correction is performed when the user desires, the reference signal and the display during adjustment appear on the screen. Therefore, it is possible to notify the user that correction is being performed, and the recognition of display interference is reduced.

FIG. 15 shows a fifth embodiment according to the present invention. In the figure, reference numeral 38 denotes a communication terminal, and other elements having the same reference numerals as those in FIG. 1 have the same function.

In FIG. 15, the control circuit 17 has a communication function, and the external device of the display is connected via the communication terminal 38.
For example, bidirectional communication with a computer can be performed. As a result, the automatic white balance correction can be performed according to the instruction from the external computer. For example, the video signal identification operation and the reference signal insertion position data generation operation, which were performed when performing white balance correction, become unnecessary by instructing the insertion position of the reference signal from the computer side via the communication line. It is possible to insert the reference signal and set the reference signal width at the optimum position.

When it is desired to change the color temperature of the white color set on the display in accordance with the application software of the computer or the contents of the image to be displayed, a white balance correction instruction command from the computer is controlled via the communication terminal 38. It is given to the circuit 17. According to this
The control circuit 17 performs a white balance correction control operation.

Further, the control circuit 17 controls the characteristic data of the cathode ray tube 7 and the cathode current detection value of the display at a predetermined color temperature and the gain adjustment value and DC level adjustment of the video circuit 3 set in the D / A circuits 9 and 10. By giving circuit characteristic data such as a value to the external computer through the communication terminal, the external computer arithmetically generates data to be set in the D / A circuits 8 and 9 at color temperatures other than the predetermined color temperature, It can be sent back to the display side.

Therefore, if the display performs white balance correction at a predetermined color temperature, it is not necessary to insert a reference signal to perform the white balance correction operation when resetting to another color temperature, and the control circuit 17 directly controls the D Only the / A circuit needs to be controlled. For this reason, the reference signal insertion operation in the white balance correction performed at the time of color temperature switching becomes unnecessary, and the influence on the screen interference can be reduced. The communication interface may be a serial communication interface used in a computer or VESA (Video Electronics Standards).
DDC (Display Data Chan) established by the Association
It is possible to use a communication interface or the like corresponding to the standard.

[0054]

As described above, in the display of the present invention,
It reduces the display interference caused by the reference signal part that accompanies the underscan display when performing automatic white balance correction on a multi-scan display that supports various video signal specifications. Further, the insertion position of the reference signal can be automatically set to the optimum position, and the white balance correction accuracy can be secured.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a first embodiment of a display according to the present invention.

FIG. 2 is a configuration diagram showing a reference signal insertion circuit according to the present invention.

FIG. 3 is a waveform diagram showing the operation of FIG.

FIG. 4 is a waveform diagram showing the operation of FIG.

FIG. 5 is a configuration diagram showing another embodiment of a reference signal insertion circuit.

FIG. 6 is a configuration diagram showing a second embodiment according to the present invention.

FIG. 7 is a waveform diagram showing the operation of FIG.

8 is a configuration diagram showing a video signal position detection circuit in FIG.

FIG. 9 is a configuration diagram showing a third embodiment according to the present invention.

10 is a waveform chart showing the operation of FIG.

FIG. 11 is a configuration diagram showing a fourth embodiment of the present invention.

12 is a diagram showing a display screen during the operation of FIG.

FIG. 13 is a control flowchart of FIG. 1.

FIG. 14 is a control flowchart of FIG.

FIG. 15 is a configuration diagram showing a fifth embodiment according to the present invention.

[Explanation of symbols]

1 Video signal input terminal 2 Reference signal insertion circuit 3, 37 video circuit 6 Deflection yoke 7 Cathode ray tube 8, 34 Timing generation circuit 9, 10 D / A circuit 13, 14 Horizontal and vertical sync signal input terminals 15 polarity unifying circuit 16 Signal discrimination circuit 17 Control circuit 18 CPU 19 A / D circuit 20 S / H circuit 21 Control panel 22 Deflection circuit 29 Video signal position detection circuit 35 Gain control circuit 36 OSD signal generation circuit 38 Communication terminal

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Koji Yokohama, 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa, Ltd. Information & Video Division, Hitachi, Ltd. (56) Reference JP-A-2-211660 (JP, A) Kaihei 5-300480 (JP, A) JP-A-6-178311 (JP, A) JP-A-7-107508 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04N 9 / 64-9/73 G09G 5/02 G09G 5/18

Claims (9)

(57) [Claims] 1. A video circuit in which video signals of three primary colors of red, blue, and green are input, and at least a gain and a DC level can be set for each video signal of each primary color, and a cathode ray tube connected to the video circuit. In a multi-frequency compatible display, which comprises a cathode current detection circuit for detecting a cathode current flowing through a cathode electrode of the cathode ray tube and can display various video signals having different signal specifications such as a video scanning frequency or a video blanking period. When a reference signal for white balance correction is inserted into the video signal, a means is provided for changing the insertion position or / and the signal width of the reference signal in accordance with the signal specification of the video signal. A multi-frequency compatible display with an automatic white balance correction function. 2. A video circuit, into which video signals of three primary colors of red, blue, and green are input, and at least gain and DC level can be set for each video signal of each primary color, and a cathode ray tube connected to the video circuit. In a multi-frequency compatible display, which comprises a cathode current detection circuit for detecting a cathode current flowing through a cathode electrode of the cathode ray tube and can display various video signals having different signal specifications such as a video scanning frequency or a video blanking period. A reference signal insertion circuit that inserts a reference signal for white balance correction for each of the primary color video signals in the preceding stage of the video circuit; and a timing generation circuit that sets an insertion position or / and a signal width of the reference signal. A polarity unifying circuit for aligning the polarities of the horizontal and vertical sync signals, which are input along with the primary color video signals, to either negative or positive, and the polarities. A CPU circuit that detects a signal specification of the video signal by an output signal from one circuit and outputs a control signal relating to the insertion position of the reference signal and / or the signal width to the timing generation circuit based on the detection result. And a multi-frequency compatible display with an automatic white balance correction function, characterized in that the insertion position and / or the signal width of the reference signal is changed according to the signal specifications of the video signal. 3. A video circuit, into which video signals of three primary colors of red, blue, and green are input, and at least gain and DC level can be set for each video signal of each primary color, and a cathode ray tube connected to the video circuit. In a multi-frequency compatible display, which comprises a cathode current detection circuit for detecting a cathode current flowing through a cathode electrode of the cathode ray tube and can display various video signals having different signal specifications such as a video scanning frequency or a video blanking period. A reference signal insertion circuit that inserts a reference signal for white balance correction for each of the primary color video signals in the preceding stage of the video circuit; and a timing generation circuit that sets an insertion position or / and a signal width of the reference signal. A polarity unifying circuit for aligning the polarities of the horizontal and vertical sync signals, which are input along with the primary color video signals, to either negative or positive, and the polarities. A video signal position detection circuit that detects the position where the video signal appears based on the sync signal position from the output synchronization signal and the video signal from one circuit, and the output from the detection circuit and the output of the polarity unifying circuit. A CPU circuit that generates the signal specifications of the video signal and outputs a control signal related to the insertion position of the reference signal and / or the signal width to the timing generation circuit based on the signal specifications is provided. A multi-frequency compatible display with an automatic white balance correction function, characterized in that the insertion position or / and the signal width of the reference signal is varied according to the signal specifications. 4. A video circuit, into which video signals of three primary colors of red, blue and green are inputted, and at least gain and DC level can be set for each of the video signals of each primary color, and a cathode ray tube connected to the video circuit. A multi-frequency compatible display capable of displaying various video signals having different signal specifications such as a video scanning frequency or a video blanking period, the display including a cathode current detection circuit for detecting a cathode current flowing through a cathode electrode of the cathode ray tube. A reference signal insertion circuit that inserts a reference signal for white balance correction for each of the primary color video signals in the preceding stage of the video circuit, and a timing generation circuit that sets an insertion position or / and a signal width of the reference signal, A polarity unifying circuit for aligning the polarities of the horizontal and vertical sync signals, which are input along with the primary color video signals, to either negative or positive, and the polarities. A deflection circuit for outputting a retrace signal deflects the synchronizing signal output from the first circuit with respect to receiving the timing generator circuit,
A CPU that generates the signal specification of the video signal from the output signal from the polarity unifying circuit and outputs a control signal related to the insertion position of the reference signal and / or the signal width to the timing generation circuit based on the signal specification. A multi-frequency compatible display with an automatic white balance correction function, characterized in that a circuit is provided, and the insertion position and / or the signal width of the reference signal is changed according to the signal specifications of the video signal. 5. A video circuit, into which video signals of three primary colors of red, blue and green are input, and at least gain and DC level can be set for each of the video signals of each primary color, and a cathode ray tube connected to the video circuit. In a multi-frequency compatible display, which comprises a cathode current detection circuit for detecting a cathode current flowing through a cathode electrode of the cathode ray tube and can display various video signals having different signal specifications such as a video scanning frequency or a video blanking period. An OSD signal generation circuit for supplying an OSD signal for performing on-screen display on the video signal, and a gain control for controlling the signal amplitude of the OSD signal and supplying it to the video circuit as a reference signal for white balance correction. Circuit and above O
A timing generation circuit for setting an SD signal insertion position or / and a signal width; and a polarity unifying circuit for aligning the polarity of the horizontal and vertical synchronization signals input accompanying the primary color video signal to either negative or positive. It receives a signal output from the polarity unifying circuit, generates a signal specification of the video signal, and outputs a control signal relating to the reference signal insertion position and / or the signal width to the timing generation circuit based on the signal specification. A multi-frequency compatible display with an automatic white balance correction function, which is provided with a CPU circuit for changing the insertion position and / or the signal width of the reference signal according to the signal specifications of the video signal. 6. The display according to claim 2, 3, 4 or 5, wherein the multi-frequency compatible display has a communication terminal with an external computer, and the CPU circuit has a bidirectional communication function with the external computer. A multi-frequency compatible display with an automatic white balance correction function, which exchanges control commands and information relating to white balance correction with the external computer. 7. The signal identification circuit according to claim 2, wherein the CPU circuit determines a signal specification such as a video scanning frequency or a video blanking period of an input video signal, A multi-frequency compatible display with an automatic white balance correction function, comprising a control circuit that outputs a control signal to at least the timing generation circuit. 8. The multi-frequency compatible display with automatic white balance correction function according to claim 2, 3 or 4, wherein the reference signal insertion circuit is provided with a D / A conversion circuit for generating a reference voltage. 9. The reference signal inserting circuit according to claim 1, wherein the reference signal inserting circuit generates a gain adjusting reference signal and a direct current level adjusting reference signal for the video circuit, and the gain adjusting reference signal is used for gain adjusting. A multi-frequency compatible display with an automatic white balance correction function, which outputs only a reference signal for gain adjustment, and outputs only the reference signal for DC level adjustment when adjusting the DC level, and inserts it into the input video signal.