JP3410186B2 - Tape-shaped recording medium device, recording device and reproducing device - Google Patents

Description

Detailed Description of the Invention

The present invention will be described in the following order. Industrial applications Conventional technology (Fig. 7) Problems to be Solved by the Invention Means for Solving the Problems (FIGS. 1, 2 and 5) Action (Fig. 2) Example (FIGS. 1 to 7) The invention's effect

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tape recording medium device,
The present invention relates to a recording device and a reproducing device, and is particularly suitable for application when recording or reproducing a digital video signal by a digital VTR (DVTR).

[0003]

2. Description of the Related Art Conventionally, when recording a digital video signal on a magnetic tape, a digital VTR employs shuffling which rearranges the order of data in order to disperse errors occurring during the recording / reproducing process. In addition to normal reproduction in which the tape speed is the same as that during recording, high-speed search reproduction in which the tape speed is several to several tens of times faster than that during recording is possible.

FIG. 7 shows a scanning locus at the time of a triple search in which the tape speed is triple the normal speed. A digital video signal for one frame is recorded on each of the tracks T1 to T10 formed on the magnetic tape. In the case of the triple search as shown in FIG. 7, the rotary head scans the magnetic tape across the tracks T1, T2 and T3 as indicated by S1, and similarly across the tracks T4, T5 and T6 as indicated by S2. Then scan the magnetic tape.

However, when the magnetic tape is scanned across the tracks in this manner, the track T2 is the boundary between the tracks T1 and T2 and the track T2 on the scanning locus S1 shown in FIG.
Error is likely to occur at the boundary between
The locations where this error is likely to occur are the same for the other scanning loci S2 and S3. Therefore, the error in the playback screen is
Even when a digital video signal is shuffled and recorded, it occurs at a substantially constant position. As a result, it is not possible to interpolate (conceal) errors that are spatially at the same position with correct temporally past data.

Further, in a consumer digital VTR and some professional digital VTRs, for example, a 1-frame screen is displayed so that a digital video signal having an extremely large amount of information can be recorded / reproduced with a relatively simple structure. Recording / reproduction is performed by removing redundancy added to the digital video signal by using high-efficiency coding in which blocks are subdivided into (4 × 4), (8 × 8), and encoded in block units. We are reducing the amount of information.

When the above-mentioned error occurs in such block coding, an error occurs in block units, it is difficult to satisfactorily correct the block data with the correct data in the periphery, and it becomes difficult to conceal in the space. Was significantly deteriorated.

In order to solve such a problem, the shuffling pattern is periodically changed in accordance with the search speed to disperse the positions of the errors generated during the search reproduction, so that the temporally past data is used. There is a DVTR designed to correct an error and improve the quality of a reproduced image (Japanese Patent Laid-Open No. 4-33484).

[0009]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
In R, when playing back a tape on which a digital video signal is recorded by periodically changing the sheafing pattern, it is necessary to play back the digital video signal using the shuffling pattern used at the time of recording. In such a case, the shuffling pattern used at the time of recording is recorded on the tape similarly to the data, and the digital video signal is reproduced according to this shuffling pattern, or the shuffling pattern is stored in the DVTR used at the time of recording. , It is possible to reproduce a digital video signal according to this shuffling pattern.

However, when recording a shuffling pattern on a tape, for example, when the search speed is considerably high, for example, 50 times or 60 times, it is general that only a small amount of data can be picked up from the tape. However, even in such a case, you must be able to pick up the shuffling pattern from the small amount of data that can be picked up,
In order to deal with this, it is necessary to record the unnecessary information called shuffling pattern on the tape many times,
There is a problem that the usage efficiency of the tape decreases.

Further, when the tape itself is damaged, not only the video signal data but also the shuffling pattern data cannot be used, which is not desirable as a medium for recording the shuffling pattern. Further, when the shuffling pattern is stored in the DVTR, there is a problem that the recorded digital video signal cannot be reproduced unless the DVTR used for recording is used and compatibility between recording and reproduction cannot be maintained.

The present invention has been made in consideration of the above points, and even if a digital video signal is recorded by periodically changing the shuffling pattern, the tape-like recording can maintain the compatibility between the recording and the reproducing. It aims to propose a medium device, a recording device, and a reproducing device.

[0013]

In order to solve such a problem, according to the present invention, a tape-shaped recording medium and a tape-shaped recording medium in which a memory means 8 is arranged at a predetermined position of a housing 10 accommodating the tape-shaped recording medium. In the recording medium device 9, a digital video signal is shuffled in a predetermined shuffling pattern and recorded on a helical recording track of a tape-shaped recording medium by a rotary head, and a memory means 8 is provided.
Is stored with the changing information of the shearing pattern and / or the shearing pattern which is changed according to the variable speed reproduction which is reproduced so as to straddle a plurality of helical recording tracks by the rotary head.

Further, in the present invention, in the recording apparatus 1 for recording a digital video signal on the helical recording track of the tape-shaped recording medium by means of the rotary head, a shearing pattern for shearing the digital video signal is provided by the rotary head. A shearing means 5 that changes in response to variable speed reproduction for reproducing over a plurality of helical recording tracks, and change information of the shearing pattern and / or the shearing pattern of a housing 10 in which a tape-shaped recording medium is stored. A memory writing means 6 for writing to the memory means 8 arranged at a predetermined position is provided.

Further, according to the present invention, in the reproducing apparatus 34 for reproducing the digital video signal recorded on the helical recording track of the tape recording medium by shuffling with the shearing pattern changed according to the variable speed reproduction, Memory reading means 40 for reading the shuffling pattern change information and / or the shuffling pattern written in the memory means 8 arranged at a predetermined position of the housing 10 accommodating the recording medium, and the shuffling pattern change information, Alternatively, a deshuffling means 39 for deshuffling the digital video signal reproduced from the helical recording track in accordance with the shuffling pattern is provided.

[0016]

The tape-shaped recording medium and the memory means 8 is arranged at a predetermined position of the housing 10 accommodating the tape-shaped recording medium, and the variable speed reproduction is carried out by the rotary head so as to cross over a plurality of helical recording tracks. The memory unit 8 stores the change information of the shuffling pattern and / or the shuffling pattern which is changed accordingly. As a result, compatibility can be maintained between recording and reproduction even when the digital video signal is recorded by periodically changing the shuffling pattern, and the usage efficiency of the tape-shaped recording medium can be improved.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

In FIG. 1, reference numeral 1 indicates the overall functional structure of the recording apparatus of the digital VTR. First, the digital video signal input from the input terminal 2 is digitally input to the A / D converter 3 in such a manner that one sample is 8 bits. Be converted. The output data thus obtained is sent to the block circuit 4, and the effective area of one frame is divided into blocks of a predetermined size. In the case of this embodiment, the effective area of one frame is divided into blocks each having a size of (8 × 8) pixels.

In this way, the video signals which are scan-converted in the block order divided by the block circuit 4 are sent to the shuffling circuit 5. The shuffling circuit 5 has two memory banks capable of shuffling input data in block units, for example, and storing coded data for one frame. That is, data is read from the other memory bank during the frame period in which data is written in one memory bank, data is read from one memory bank in the next frame period, and data is read into the other memory bank. Written.

Thus, by making the address at the time of reading different from the order of the address at the time of writing, shuffling can be performed. In this embodiment, the writing of data in the shuffling circuit 5 is performed with an incrementing write address. Data is read based on a read address for reading one frame of data stored in a shuffling table formed of a memory or control data for generating a read address.

Since the input terminal 6A of the switching circuit 6 is connected to the shuffling table 5A and the input terminal 6B of the switching circuit 6 is connected to the shuffling table 5B, the read address or control data is switched. The shuffling table 5A or 5B selected by the circuit 6 is sent to the shuffling circuit 5.

Here, the switching of the switching circuit 6 is periodically switched by a control pulse from the terminal 7. Therefore, by periodically switching the switching of the switching circuit 6, the order of addresses at the time of reading data and the order of addresses at the time of writing data can be changed, so that different shuffling can be performed. In this embodiment, the switching is switched every 3 frames. Therefore, the scanning patterns S1 and S2 shown in FIG. 7 have different shearing patterns.

What is important here is that a semiconductor memory 8 is connected to the switching circuit 6, and the shuffling pattern used at the time of recording is recorded in this semiconductor memory 8.

As shown in FIG. 2, the semiconductor memory 8 is built in a magnetic tape cassette 9. The cassette body 10 of the magnetic tape cassette 9 with a built-in memory is provided with two reels 11 around which a magnetic tape is wound and an opening 12 for drawing out the magnetic tape on the front side. The semiconductor memory 8 is arranged at the center of the opening 12 and is composed of an interface section 13 and a memory section 14 as shown in FIG. Here, the position where the semiconductor memory 8 is provided may be another position, and the interface unit 13
The plurality of terminals provided on the can be freely changed.

The interface unit 13 is mainly composed of an interface connector and is connected to a connector on the VTR side for data transmission / reception. The memory unit 14 is electrically connected to the interface unit 13 and is connected to the interface unit. 1
Data and the like are transmitted / received to / from the VTR side via 3. As shown in FIG. 3, the memory unit 14 has an R / W (read / wri
te) control and chip select circuit 15, SRAM (stat
ic random access memory) 16, a power supply control circuit 17, and a backup battery 18, and appropriately records or reproduces data from the VTR side in the SRAM 16.

R / W control and chip select circuit 15
Receives a control signal 19 such as a write signal or a read signal from the VTR side via the interface unit 13 or transmits the control signal 19 to the VTR side. Further, the R / W control and chip select circuit 15 receives an address signal 20 for taking in the control signal 19 via the interface section 13, and transmits and receives a control signal 21 for sending timings such as writing and reading to the SRAM 16. . Based on these signals, the R / W control and chip select circuit 15 sets the SR
Give appropriate instructions to AM16. In this case, the memory unit 14
Uses an SRAM 16 which does not require a circuit such as a refresh, but an IC memory may be used.

The SRAM 16 uses the address signal 22 and the data signal 23 sent through the interface unit 13 based on the control signal 19 from the R / W control and chip select circuit 15 to appropriately convert the data into the address signal of the memory. Can be written and read.

The power supply control circuit 17 supplies an appropriate power supply voltage V to the R / W control and chip select circuit 15 and the SRAM 16.
This is a circuit for supplying CC, which supplies the power supply VCC from the VTR side through the interface unit 13, and also supplies the proper voltage value VPP of the power supply and the ground GND.
When the power supply voltage VCC supplied to the power supply control circuit 17 has an appropriate voltage value, the power supply control circuit 17 sends a normal voltage value signal VBAT to the VTR side through the interface unit 13 and at the same time sends a reset signal for a predetermined time. And then R /
The W control and chip select circuit 15 is brought into an appropriate driving state, and the memory voltage is supplied to the SRAM 16.

The back-up battery 18 keeps the operating operation (especially during writing) up to a good state even when an instantaneous failure or a sudden failure due to voltage drop occurs while the SRAM 16 is being driven. It is a voltage supply source for backup.

By the way, when the magnetic tape cassette 9 is set in the digital VTR, the interface portion 13 of the semiconductor memory 8 built in the magnetic tape cassette 9 becomes V.
Since it is connected to the predetermined signal terminal and power supply terminal in TR,
The semiconductor memory 8 is held in a storable state.

Therefore, when the VTR is used in the recording mode, the shuffling pattern information is recorded in the SRAM 16 for each frame or each field of the picked-up image. At this time, the R / W control and chip select circuit 15 is
The control signal 19, the address signal 20 and the data signal are received from the side through the interface unit 13, and the SRAM 16 is controlled based on the control signal 19 and the address signal 20,
The address signal 22 and the data signal 23 are taken in via the interface unit 13 and stored.

As described above, if the shuffling pattern information used at the time of recording is stored in the semiconductor memory 8 built in the magnetic tape cassette 9, the shuffling data can be surely read out, and at the same time between recording and reproduction. Compatibility can be maintained. In addition, when the shuffling pattern is stored in the semiconductor memory 8, the shuffling pattern can be surely acquired by recording the shuffling pattern once regardless of the search speed. The degree can be remarkably reduced.

The data which has been shuffled in block units in the shuffling circuit 5 is a block coding circuit 24.
The data is compressed by requantizing the pixel data for each block. In this embodiment, ADRC (adaptive dynamic-range coding) reduces the amount of transmission data by reducing the redundancy of the image data in the level direction.
To use.

That is, as shown in FIG. 4, the shuffled data includes the maximum value detection circuit 25 and the minimum value detection circuit 2.
6 and the delay circuit 27, the maximum value detection circuit 25 and the minimum value detection circuit 26 detect the maximum value MAX and the minimum value MIN for each block, and the subtraction circuit 28 outputs (MAX-MI
N) is calculated to detect the dynamic range DR. In the subtraction circuit 29, the minimum value MIN is subtracted from the pixel data input from the delay circuit 27, and the pixel data from which the minimum value is subtracted, that is, the normalized pixel data is output to the quantization circuit 30 and the minimum value is The removed pixel data is adapted to the dynamic range DR and requantized. Assuming that the bit allocation is n and the data level of the pixel in the block is L, the following equations (1) and (2)

[Equation 1]

[Equation 2] The requantization code DT is calculated by. Through the above processing, the dynamic range DR, the minimum value MIN and the quantized data DT are output to the framing circuit 31.

The data compressed by the block coding circuit 24 is sent to the framing circuit 31, and the framing circuit 3
In No. 1, the parity of the error correction code is generated and the record data having a structure in which sync blocks are continuous is generated.
Here, as the error correction code, for example, a product code that performs error correction coding in each of the horizontal direction and the vertical direction of the data arranged in a matrix can be applied. A sync block synchronization signal and an ID signal are added to the encoded data and the parity, and the recorded data in which the sync blocks are continuous is the channel encoding circuit 32.
And the channel coding process is performed to reduce the DC component.

Next, the output data from the channel encoding circuit 32 is converted into a bit stream, and the recording amplifier 33
Is transmitted to the rotary head H via the recording head and recording data is recorded as a track on the magnetic tape T diagonally. Although only one rotating head is shown in FIG. 1 for convenience, multiple rotating heads are typically used.

Next, the case of reproducing the video signal data recorded as described above will be described with reference to FIG. In FIG. 5, reference numeral 34 denotes a DVTR reproducing apparatus as a whole. First, the recording data taken out from the magnetic tape T by the rotary head H is sent to a channel decoding circuit 36 via a reproducing amplifier 35 and is channel-encoded. Decrypt the data. The decoded recording data is supplied to the frame decomposing circuit 37, various data is separated from the recording data, and error correction is performed. After that, the recorded data is output to the block decoding circuit 38. The recorded data includes an error flag indicating whether or not there is an error after error correction in addition to the reproduced data.

The block decoding circuit 38 decodes the coded data using ADRC. In this case, the frame decomposing circuit 37 supplies the dynamic range DR, the minimum value MIN and the coded data for each pixel to the block decoding circuit 38. If the number of quantization bits is n, the decoded value L is Formula (3)

[Equation 3] Can be expressed as

The decoded data decoded by the block decoding circuit 38, that is, the restored data corresponding to each pixel is sent to the deshuffling circuit 39. The deshuffling circuit 39 has a complementary relationship with the shuffling circuit 5 on the recording side, and performs a process of returning the spatial position of the block to the original position.

Here, the digital V in this embodiment is
In TR, a time code for reading out the shuffling pattern information stored in the semiconductor memory 8 during reproduction is output from the deshuffling circuit 39 to the semiconductor memory 8. Based on this time code, the shearing pattern of the frame (or field) currently being reproduced is read from a predetermined position of the semiconductor memory 8 via the interface section 13 of the semiconductor memory 8.

Accordingly, the switching circuit 40 switches the switching table 39A and the switching table 39B on the basis of the switching pattern information read from the semiconductor memory 8 in the same procedure as the switching process. It is possible to perform deshuffling.

Here, the case of high speed search reproduction will be described. At the time of normal reproduction, the speed of the magnetic tape is the same as that at the time of recording, and the rotary head scans the oblique track formed on the magnetic tape. On the other hand, during high speed search / playback, the speed of the magnetic tape is set higher than that during recording. For example, in the case of a triple search in which the speed of the magnetic tape is three times that in normal reproduction, the scanning locus S1 of the rotary head is formed across the tracks T1, T2 and T3 as shown in FIG. The scanning locus S2 is track T4, T
5 and T6.

In the shuffling circuit 5 in the recording apparatus of the digital VTR shown in FIG. 1, the tracks T1, T2 and T are tracked.
Shuffling of data recorded in each of No. 3 is performed based on the shuffling table 5A, and shuffling of data recorded in each of the following tracks T4, T5, and T6 is performed based on the shuffling table 5B.

Therefore, since the data acquired in the scanning locus S1 during the high speed search reproduction is the deshuffling corresponding to the shuffling by the shuffling table 5A, the deshuffling based on the deshuffling table 39A is performed. Since the data acquired on the scanning locus S2 during the high speed search reproduction is the deshuffling corresponding to the shuffling by the shuffling table 5B, the deshuffling based on the deshuffling table 39B is performed.

The data de-scuffed in this way is sent to the block decomposition circuit 41, the data order is returned to the order of raster scanning, and sent to the error correction circuit 42. The error correction circuit 42 interpolates the error data in pixel units with the peripheral pixel data. For example, as the correction processing, it is possible to use one in which a spatial interpolation circuit and a temporal interpolation circuit are sequentially connected. The error-corrected data is sent to the D / A converter 43 and converted into analog data. Through the above processing, the output terminal 4
In 4, the restored data corresponding to each pixel and returned to the raster scanning order can be obtained.

When the data output from the output terminal 44 is reproduced, in the case of the scanning loci S1, S3, ... Shown in FIG. 7, the error occurring at the portions near both ends of the scanning locus is shown in FIG. The scanning loci S2, S appear at the position of "x" shown.
4 ... Appears at the position of "x" shown in FIG. 6 (B). This is because in each scanning locus S1, S2 ... SN,
This is because the shuffling pattern is made different for every three tracks, even though both ends of the scanning locus where an error occurs are the same in relative position on the tape. Therefore, during search reproduction, the position of the error in the obtained image will be different between two consecutive scans. As a result, it is possible to perform interpolation in the time direction with the correct data of one frame before, and it is possible to improve the quality of the reproduced image.

According to the above construction, the shuffling pattern used at the time of recording is recorded in the semiconductor memory 8 with the cassette, and the time code for reading out the shuffling pattern information from the semiconductor memory 8 at the time of search reproduction is outputted from the deshuffling circuit 39. Output to the semiconductor memory 8. Based on this time code, the shuffling pattern of the frame (or field) currently being reproduced is read from a predetermined position of the semiconductor memory 8.

Thus, by storing the shuffling pattern information in the semiconductor memory 8, the shuffling pattern can be surely read at the time of search and reproduction, and the compatibility between recording and reproduction can be maintained. Further, when the shuffling pattern information is stored in the semiconductor memory 8, the shuffling pattern can be surely acquired by recording once regardless of the search speed, so that the shuffling pattern is recorded as compared with the case of recording on the magnetic tape. The recording redundancy can be reduced, which is particularly effective in the case of the high speed search as in the above-mentioned embodiment.

Further, by periodically changing the shuffling pattern according to the search speed, it is possible to avoid the occurrence of an error at the same position in the reproduced image. It is possible to improve the image quality of the reproduced image at the time of search.

In the above embodiment, the case where ADRC is used as the high efficiency coding has been described, but the present invention is not limited to this, and other block coding such as DCT may be used, and higher coding is possible. It can also be applied to the case of non-compression without efficiency coding.

In the above-described embodiment, the case where the shuffling pattern is changed every three frames has been described, but the present invention is not limited to this, and the shuffling pattern is changed in frame units that are natural numbers times the maximum search speed. Changes can be made to achieve the desired result. For example, when the maximum search speed is 30 times, the shuffling pattern may be changed every 30 frames. However, in this case, 30 = 2 × 3 ×
Since it is 5, it is possible to search at a search speed of 2 times, 3 times, 5 times, 6 times, 10 times, 15 times and 30 times.

Further, in the above embodiment, the case where the used shuffling pattern is recorded in the semiconductor memory 8 has been described, but the present invention is not limited to this, and other memory means may be used as long as random access is possible. You may.

[0053]

As described above, according to the present invention, the memory means is arranged at a predetermined position of the tape-shaped recording medium and the housing in which the tape-shaped recording medium is housed, and a plurality of helical recording tracks are formed by the rotary head. By storing the change information of the shuffling pattern and / or the shuffling pattern, which is changed according to the variable speed reproduction that is played across the memory means, in the memory means, the shuffling pattern is periodically changed and the digital video is recorded. Even when a signal is recorded, compatibility can be maintained between recording and reproduction, and the usage efficiency of the tape-shaped recording medium can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a functional configuration of a recording device of a DVTR according to an embodiment of the present invention.

FIG. 2 is a side view showing a back surface of a magnetic tape cassette provided with a semiconductor memory.

FIG. 3 is a block diagram for explaining a functional configuration of a semiconductor memory according to an embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of an ADRC encoding circuit in the embodiment.

FIG. 5 is a block diagram showing a functional configuration of a DVTR playback device according to an embodiment of the present invention.

6 is a schematic diagram showing a difference between an error position (A) on the scanning loci S1 and S3 and an error position (B) on the scanning locus S2 in FIG.

FIG. 7 is a schematic diagram showing a scanning locus in a triple search.

[Explanation of symbols]

1 ... Recording device 2, 6A, 6B, 7, 40A, 40B
...... Input terminal, 3 ... A / D converter, 4 ... Blocking circuit, 5 ... Shuffling circuit, 5A, 5B ... Shuffling table, 6,40 ... Switching circuit, 8 ...
… Semiconductor memory, 9 …… Magnetic tape cassette, 10 ……
Cassette body, 11 ... reel, 12 ... opening, 13
... interface section, 14 ... memory section, 15 ... W
/ R control and chip select circuit, 16 ... SRAM,
17 ... power control circuit, 18 ... back-up battery, 1
9, 21 ... Control signal, 20, 22 ... Address signal,
23 ... Data signal, 24 ... Block coding circuit, 2
5 ... Maximum value detection circuit, 26 ... Minimum value detection circuit, 27
... delay circuit, 28, 29 ... subtraction circuit, 30 ... quantization circuit, 31 ... framing circuit, 32 ... channel encoding circuit, 33 ... recording amplifier, 34 ... reproducing device,
35: reproduction amplifier, 36: channel decoding circuit,
37 ... Frame disassembling circuit, 38 ... Block decoding circuit, 39 ... Desicculating circuit, 39A, 39B ...
Discrete fling table, 41 ... Block disassembly circuit,
42 ... Error correction circuit, 43 ... D / A section, 44 ...
Output terminal.

Claims (3)

(57) [Claims] 1. A magnetic tape device comprising a tape-shaped recording medium and a memory means disposed at a predetermined position of a housing in which the tape-shaped recording medium is housed, wherein a helical video track of the tape-shaped recording medium is a digital video. The signal is shuffled in a predetermined shuffling pattern and recorded by the rotary head, and the memory means is changed in response to the variable speed reproduction which is reproduced by the rotary head so as to straddle the plurality of helical recording tracks. A tape-shaped recording medium device, characterized in that the shuffling pattern change information and / or the shuffling pattern are stored. 2. A recording apparatus for recording a digital video signal on a helical recording track of a tape-shaped recording medium by means of a rotary head, wherein a plurality of shearing patterns for shearing the digital video signal are provided at the rotary head. Shearing means for changing in response to variable speed reproduction for reproduction so as to straddle the helical recording track, and the change information for the shearing pattern and / or the shearing pattern are provided in a predetermined manner in a housing in which the tape-shaped recording medium is housed. A memory writing means for writing to the memory means arranged at the position. 3. A reproducing apparatus for reproducing a digital video signal recorded by being shuffled in a shearing pattern which is changed according to variable speed reproduction, in a helical recording track of the tape recording medium, wherein the tape recording medium is housed. Memory reading means for reading the shuffling pattern change information written in the memory means arranged at a predetermined position of the housing and / or the shuffling pattern change information, and the shuffling pattern change information and / or the shuffling pattern. Accordingly, a reproducing apparatus comprising: a de-scattering means for de-scrambling the digital video signal reproduced from the helical recording track.