JP3402380B2 - Semiconductor circuit and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

The present invention relates to a thin film transistor (T
The present invention relates to a semiconductor circuit (for example, an image sensor) having an FT) and a thin film diode (TFD) and a manufacturing method thereof. The semiconductor circuit manufactured by the present invention is formed on either an insulating substrate such as glass or a semiconductor substrate such as single crystal silicon. In particular, the present invention is a TFT manufactured through crystallization and activation by thermal annealing.
And a semiconductor circuit having.

[0002]

2. Description of the Related Art Thin film semiconductor devices such as thin film transistors and thin film diodes are classified into amorphous devices and crystalline devices depending on the type of silicon used.
Amorphous silicon had a low fabrication temperature and was excellent in mass productivity, but because it was inferior to crystalline silicon in physical properties such as field effect mobility and conductivity, a crystalline semiconductor element was required to obtain high-speed characteristics. . On the other hand, amorphous semiconductors
It has been generally known that it can be used for an optical sensor or the like because the change in photoconductivity is large. Recently, a circuit (for example, an integrated image sensor circuit) has been proposed in which an optical sensor using an amorphous silicon diode is driven by a thin film transistor using crystalline silicon that can operate at high speed.

[0003]

FIG. 4 shows an example of a procedure for producing a circuit in which a conventional amorphous silicon diode and a crystalline silicon TFT are combined. An underlying insulating film 51 is formed on a glass substrate 50, an amorphous silicon film is formed on the underlying insulating film 51, and this is annealed at a temperature of 600 ° C. or higher for a long time to be crystallized and patterned to form an island-shaped silicon region 52. To get Then, the gate insulating film 53 is formed, and further the gate electrodes 54N and 54P are formed. (Fig. 4 (A))

Then, the N-type impurity region 55N and the P-type impurity region 55P are formed by using a known CMOS fabrication technique. In this impurity introducing step, impurities are introduced in a self-aligned manner with respect to the gate electrode. After implanting impurities,
The impurities are activated by means such as laser annealing and thermal annealing. (Fig. 4 (B))

Next, a first interlayer insulator 56 is formed,
Contact holes are formed in this, and electrodes / wirings 57a, 57b, 57c and an electrode 57d of the amorphous silicon diode are formed in the source and drain of the TFT. (FIG. 4C) Next, P-type, I-type (intrinsic) and N-type amorphous silicon films 58P, 58I, and 58N are sequentially stacked and patterned to form a diode junction. (Fig. 4
(D) Finally, a second interlayer insulator 59 is formed, a contact hole is formed in the second interlayer insulator 59, and an electrode 60 of the amorphous silicon diode is formed, thereby completing the circuit. (Fig. 4
(E))

In the conventional method which requires such a procedure,
Since it is necessary to form two layers each of a silicon film and an interlayer insulating film, which are required to be formed for a long time, and an N layer and a P layer in addition to the two layers, there is a problem that throughput is reduced. In addition, in the plasma CVD method and the low pressure CVD method used for forming these films, the dead time of the apparatus for maintenance is large, and the existence of these extra steps further lowers the throughput.

In addition, a temperature of 600 ° C. or higher is required to crystallize the silicon film used for the crystalline silicon TFT, and a long time of 24 hours or more is required for the crystallization, so that it is actually necessary. When mass-producing, a number of crystallization equipment facilities were required, and there was the problem that a huge amount of equipment investment would rebound into costs. The present invention overcomes the above problems by forming a silicon film used for a crystalline silicon TFT and a silicon film used for an amorphous silicon diode at the same time, and using only one interlayer insulating film. Provided is a technique for crystallizing a silicon film at a temperature equal to or lower than 0 ° C. and for a short time that does not substantially cause a problem.

[0008]

As a result of the research conducted by the present inventor,
Substantially amorphous state (In the present invention, the amorphous state and the substantially amorphous state are
A so-called amorphous state or a crystallinity which is extremely poor is included. It was revealed that the crystallization can be promoted, the crystallization temperature can be lowered, and the crystallization time can be shortened by adding a trace amount of the catalyst material to the silicon coating of (1). Nickel (Ni), iron (F
e), cobalt (Co) and platinum (Pt) are suitable.
Specifically, a film, particles, clusters, etc. containing these catalytic element simple substance or a compound such as a silicide are formed in intimate contact under or on the amorphous silicon film, or amorphous silicon is formed by a method such as ion implantation. These catalytic elements can be crystallized by introducing these catalytic elements into the film and then thermally annealing them at a suitable temperature, typically 580 ° C. or lower.

As a matter of course, the higher the annealing temperature, the shorter the crystallization time. Further, there is a relationship that the higher the concentration of the catalyst element, the lower the crystallization temperature and the shorter the crystallization time. According to the research conducted by the present inventors, in order to promote crystallization, the concentration of at least one of these elements is 1 × 10 ¹⁷ cm ⁻³ , preferably 5 × 10 ¹⁸ cm 3.
^-It turns out that it is necessary to exist more than ^-3 . It was also clarified that depending on the annealing temperature and time, the catalyst element was diffused by about 10 to 20 μm and the crystallization proceeded in the lateral direction. .

On the other hand, all of the above catalyst materials are unfavorable materials for silicon, so it is desirable that the concentration thereof be as low as possible. In the present inventors' research, especially when used as an active region, the total concentration of these catalyst materials is 2 in order to obtain sufficient reliability and characteristics.
It is desired not to exceed × 10 ²⁰ cm ^-3 .

Further, it should be noted that the amorphous state can be maintained in such a region where the catalyst material does not exist without any crystallization.
For example, crystallization of amorphous silicon without such a catalyst material usually starts at a temperature of 600 ° C. or higher, but does not proceed at 580 ° C. or lower. However, 30
Since hydrogen necessary for neutralizing dangling bonds in amorphous silicon is released in an atmosphere of 0 ° C. or higher, it is desirable that annealing be performed in a hydrogen atmosphere in order to obtain good photosensitivity.

The present inventor has paid attention to the effect of this catalytic element and found that by utilizing this, crystalline silicon is obtained by annealing at a lower temperature for a shorter time and used for TFT. In the present invention, the function of the element is enhanced by utilizing the characteristics of crystallization by the above-mentioned catalyst material to crystallize and activate only the TFT and leave the TFD in the amorphous state. Further, the present inventor further studied and found a method that enables simplification of the process which is another problem described above, that is, reduction of the film forming step. The outline is shown below. Deposition of amorphous silicon film 'Deposition of a substance having a catalytic element on the silicon film in the TFT area Deposition of insulating film (gate insulating film) Formation of gate electrode of TFT, mask material of TFD Introducing doping impurities (ion implantation) Or by ion doping method) Activation of doping impurities (600 ° C or less, within 8 hours) Formation of interlayer insulator Formation of source and drain electrodes of TFT

Film formation of amorphous silicon film'Introduction of catalytic element into silicon film of TFT area (by ion implantation or ion doping method) Film formation of insulating film (gate insulating film) Gate electrode of TFT, mask of TFD Material formation Doping impurity introduction (by ion implantation or ion doping method) Doping impurity activation (600 ° C or less, within 8 hours) Interlayer insulator formation TFT source / drain electrode formation

From the viewpoint of precisely controlling the concentration of the catalytic element, it is desirable to use a means such as an ion implantation method for the step '. Due to the presence of the catalytic element, a temperature of 600 ° C or lower, typically 550 ° C or lower is sufficient for crystallization and activation, and the annealing time is 8 hours or less, typically 4 hours or less. Is enough. In particular, when the catalyst element was evenly distributed from the beginning by the ion implantation method or the ion doping method, the crystallization was extremely easy to proceed.

In the present invention, the structure of the TFD will be briefly described. In contrast to the conventional TFD having a layered structure, the TFD of the present invention is characterized by having a planar (planar) structure. . In the present invention, the active region of the TFT and the intrinsic region of the TFD start from the same amorphous silicon film. However, since the catalytic element is not introduced into the TFD region, it does not crystallize in the subsequent annealing process. This is achieved because the annealing temperature in the present invention can be lowered by 50 ° C. or more compared to the conventional one. For this reason, conventionally, it was necessary to form a two-layer silicon film, whereas in the present invention, formation of a single-layer silicon film is sufficient. Then, the N layer and the P layer, which have been conventionally required, can be obtained by forming the N layer and the P layer in a plane at the same time as the impurity doping of the TFT. That is, the N-type region of the TFD is formed when the N-type impurity is injected into the TFT, and the P-type region of the TFD is formed when the P-type impurity is injected into the TFT. As a result, the interlayer insulator also becomes one layer.

Such a planar TFD has a feature not heretofore available. When a conventional TFD (having a shape as shown in FIG. 4) is used as an optical sensor, for example, the direction in which the electric field generated inside the semiconductor is applied is perpendicular to the light irradiation surface, and the light irradiation intensity is applied by the electric field. The direction was not uniform, and electrons / holes were efficiently generated and could not be taken out to the outside. In addition, the TFD may be short-circuited due to pinholes between layers. In the present invention, since the direction of the electric field generated in the TFD is parallel to the light irradiation surface, the light intensity in the electric field direction is constant, the photoelectric conversion efficiency is improved, and a short circuit hardly occurs.

In the present invention, 1000 is not crystallized by the usual thermal annealing due to the action of the catalytic element.
Thin amorphous silicon film of Å or less also crystallizes. T
The thickness of the crystalline silicon film is 1000 Å or less, preferably 50, from the viewpoint of preventing pinholes and insulation defects in the gate insulating film and disconnection of the gate electrode in the step portion of the FT.
Less than 0Å was required. Conventionally, it could not be realized by a method other than laser crystallization, but according to the present invention, it could be realized by thermal annealing even at low temperature. It goes without saying that this contributes to further improvement in yield.
Hereinafter, the present invention will be described in more detail with reference to examples.

[0018]

[Embodiment] [Embodiment 1] FIG. 1 shows a cross-sectional view of a manufacturing process of this embodiment. First, the substrate (Corning 7059) 10
An underlying film 11 of silicon oxide having a thickness of 2000 Å was formed on the upper surface by a sputtering method. Subsequently, the thickness is 500 to 1500 Å, for example, 1500 Å by the plasma CVD method.
Intrinsic (I-type) amorphous silicon film 12 was deposited. Continuously, the thickness is 5 to 2 by the sputtering method.
00Å, for example 20Å nickel silicide film (chemical formula NiS
i _x , 0.4 ≦ x ≦ 2.5, for example, x = 2.0) 13
Were selectively formed as shown in the figure. (Fig. 1 (A))

Then, this was annealed at 500 ° C. for 4 hours in a hydrogen reducing atmosphere (preferably, the partial pressure of hydrogen is 0.1 to 1 atm) to be crystallized. As a result, the amorphous silicon film below the nickel silicide film 13 was crystallized into a crystalline silicon film. On the other hand, the silicon film in the region where the nickel silicide film did not exist remained in the amorphous state.

Next, the obtained silicon film is patterned by photolithography to form island-shaped silicon regions 1.
4a (for TFT) and 14b (for TFD) were formed. The region 14a is crystallized in the previous annealing process, but the region 14b remains amorphous. further,
A 1000 Å thick silicon oxide film 15 was deposited as a gate insulating film by a sputtering method. For sputtering, silicon oxide is used as a target, the substrate temperature during sputtering is 200 to 400 ° C., for example 300 ° C., the sputtering atmosphere is oxygen and argon, and argon / oxygen = 0 to 0.5, for example 0.1 or less. did. Subsequently, the thickness of 6000 to 8000 is obtained by the low pressure CVD method.
A Å, for example, 6000Å silicon film (containing 0.1 to 2% of phosphorus) was deposited. It is desirable that the steps of forming the silicon oxide and the silicon film are continuously performed. Then, the silicon film was patterned to form the gate electrodes 16a and 16b of the TFT and the mask material 16c of the TFD. (Fig. 1 (B))

Next, as shown in FIG. 1C, a photoresist mask 17a was formed, and impurities (phosphorus) were implanted into the silicon region by plasma doping using the gate electrode as a mask. Phosphine (PH ₃ ) is used as the doping gas, the acceleration voltage is 60 to 90 kV,
For example, it is set to 80 kV. Dose amount is 1 × 10 ¹⁵ to 8 × 1
It was set to 0 ¹⁵ cm ^-2 , for example, 2 × 10 ¹⁵ cm ^-2 . As a result, the N-type impurity region 18a of the TFT and the N-type impurity region 19n of the TFD were formed. (Fig. 1 (C))

Next, as shown in FIG. 1D, a photoresist mask 17b was formed, and impurities (boron) were implanted into the silicon region by plasma doping using the gate electrode as a mask. Diborane (B ₂ H ₆ ) was used as a doping gas, and the acceleration voltage was 40 to 80 k.
V, for example, 65 kV. The dose amount is 1 × 10 ¹⁵ to 8
It was set to × 10 ¹⁵ cm ^-2 , for example, 5 × 10 ¹⁵ . As a result, the P-type impurity region 18b of the TFT and the P-type impurity region 19p of the TFD were formed. When this doping impurity is introduced, no impurities are injected into the region between the N-type region and the P-type region of the TFD by the mask material 16c of TFD, and the region becomes the intrinsic region 19i. (Fig. 1
(D))

Then, the impurities were activated by annealing at 500 ° C. for 4 hours in a hydrogen reducing atmosphere of 0.1 to 1 atm. At this time, since nickel has diffused into the region 14a of the TFT into which nickel has been implanted previously, crystallization is easily promoted by this annealing and the doping impurities are activated. On the other hand, the TFD area 14b
Since there was no nickel in the alloy, it remained amorphous. After the annealing was completed, the TFD mask material 16c was removed. (Fig. 1 (E))

Then, as an interlayer insulator, the thickness is 6000Å
A silicon oxide film 20 of
A contact hole is formed in this, and the TFT is made of a metal material, for example, a multilayer film of titanium nitride and aluminum.
Electrode / wiring 21a, 21b, 21c, TFD electrode /
The wirings 21d and 21e are formed. Finally, annealing was performed at 350 ° C. for 30 minutes in a hydrogen atmosphere of 1 atm. The semiconductor circuit is completed through the above steps. (Fig. 1
(F))

In this step, as is clear from the figure, both the silicon film and the interlayer insulator could be formed as one layer. As a result, the film forming process was greatly reduced. Further, when the concentration of nickel was measured by the secondary ion mass spectrometry (SIMS) method, it was found to be 1 × in the area 14a of the TFT.
10 ^{18 to} 5 × 10 ¹⁸ cm ⁻³ of nickel was detected. On the other hand, in the TFD region 14b, the measurement limit (1 × 10 ¹⁶ cm
^-3 ) It was below. These concentrations are the film thickness of the silicon film.
It is the minimum value of the density distribution in the direction. The TFD portion of the semiconductor circuit of this embodiment is shown in FIG. When this TFD is used as an optical sensor, light is incident from above. The energy band diagram along AA ′ of this TFD is shown as in FIG. 2 (B).

[Embodiment 2] FIG. 2 shows a cross-sectional view of a manufacturing process of this embodiment. A base film 31 of silicon oxide having a thickness of 2000 Å was formed on a substrate (Corning 7059) 30 by a sputtering method. Further, an amorphous silicon film 32 having a thickness of 500 to 1500 Å, for example, 500 Å, and a silicon oxide film 33 having a thickness of 200 Å were deposited by the plasma CVD method. Then, the amorphous silicon film 32 is masked with a photoresist 34, and nickel ions are selectively implanted by an ion implantation method so that nickel is 1 × 10 ¹⁸ to 2 × 10 ¹⁹ cm ⁻³ , for example, 5 × 10 ¹⁸ c.
A region 35 was prepared so that only m ^{−3 was} included.

The depth of this region 35 was set to 200 to 500Å, and the optimum acceleration energy was selected accordingly. In addition, nickel was not injected into the region which should be the channel formation region and the region where the TFD is formed in the TFT. However, the channel length of TFT is 2
The thickness is 0 μm or less, preferably 10 μm or less. This is because nickel can be diffused by annealing and the surrounding can be crystallized. By utilizing this action, crystallization can be promoted while reducing the nickel concentration in the active region of the TFT. (Fig. 3 (A))

Then, the amorphous silicon film was patterned to form island-shaped silicon regions 36a (for TFT) and 36b (for TFD). Further, using tetra ethoxy silane (Si (OC ₂ H ₅ ) ₄ , TEOS) and oxygen as raw materials, a 1000 Å-thick silicon oxide 37 was formed as a gate insulating film by the plasma CVD method. As the raw material, trichlorethylene (C ₂ HCl ₃ ) was used in addition to the above gas. Oxygen 400SCCM flow into the chamber before film formation, substrate temperature 300 ° C, total pressure 5P
a, plasma was generated with an RF power of 150 W, and this state was maintained for 10 minutes. After that, 300S oxygen is added to the chamber.
A silicon oxide film was formed by introducing 15 SCCM of CCM and TEOS and 2 SCCM of trichloroethylene. The substrate temperature, RF power, and total pressure are each 300
C., 75 W, 5 Pa. After the film formation was completed, 100 Torr of hydrogen was introduced into the chamber, and hydrogen annealing was performed at 350 ° C. for 35 minutes.

Subsequently, by the sputtering method,
A tantalum film having a thickness of 6000 to 8000Å, for example, 6000Å was deposited. It is desirable that the steps of forming the silicon oxide 37 and the tantalum film be continuously performed. Chromium, molybdenum, tungsten, titanium, or the like may be used instead of tantalum, but it is required that they can withstand the subsequent annealing step. Then, by patterning the tantalum film, the gate electrodes 38a, 38b of the TFT,
The TFD mask material 38c was formed. Further, the surface of this tantalum wiring was anodized to form an oxide layer on the surface. Anodization was performed in a 1-5% ethylene glycol solution of tartaric acid. The thickness of the obtained oxide layer is 20.
It was 00Å. (Fig. 3 (B))

Next, impurities (phosphorus) were implanted into the silicon region by the plasma doping method. Phosphine (PH ₃ ) was used as the doping gas, and the acceleration voltage was 6
It was set to 0 to 90 kV, for example, 80 kV. 1x dose
10 ¹⁵ to 8 × 10 ¹⁵ cm ^-2 , for example, 2 × 10 ¹⁵ cm ^-2
And Thus, the N-type impurity region 39 was formed. (Fig. 3 (C))

Further, the left TFT (N-channel type TF
T) and the region on the right side of the TFD (N-type region) are masked with the photoresist 40, and again the silicon region of the TFT on the right side (P-channel TFT) and the region on the left side of the TFD (P-type region) are formed by the plasma doping method. Impurity (boron) was injected into. As a doping gas, diborane (B
₂ H ₆ ) and an acceleration voltage of 50 to 80 kV, for example 6
It was set to 5 kV. Dose amount is 1 × 10 ¹⁵ to 8 × 10 ¹⁵ cm
^-2 , eg 5 × 10 ¹⁵ cm more than the previously injected phosphorus
^-2 . As a result, the N-type impurity region 41 of the TFT is
a, the same P-type region 41b and the N-type region 42n of the TFD,
A P-type region 42p was formed. (Fig. 3 (D))

Then, the impurities were activated by annealing at 500 ° C. for 4 hours in a hydrogen reducing atmosphere of 0.1 to 1 atm. At this time, in the region 36a into which nickel was previously implanted, crystallization easily proceeded by this annealing, and the doping impurities were activated. On the other hand, TF
Nickel was not present in the silicon of the D region 36b (including the intrinsic region 42i), so that it was not crystallized. (FIG. 3E) Subsequently, a 2000 Å-thick silicon oxide film 43 is formed as an interlayer insulator by a plasma CVD method, and a contact hole is formed in the silicon oxide film 43 to form a metal material, for example, a multilayer of titanium nitride and aluminum. The electrodes of the TFT / wiring 4 depending on the film
4a, 44b, 44c, TFD electrodes / wirings 44d, 4
4e was formed. Finally, in a hydrogen atmosphere at 1 atm, 350
Annealing was performed at 30 ° C. for 30 minutes. The semiconductor circuit is completed through the above steps. (Fig. 3 (F))

In this embodiment, the TFD mask material 38c is used.
Is insulated from other gate electrode wirings and is in a floating potential state. However, in this case, the operation of the TFD may be hindered by the accumulation of some electric charge. if,
If stable operation is required, it may be set to the same potential as the P-type region or N-type region of the TFD. Further, in this embodiment, since the mask material 38c is present on the intrinsic region 42i, when the TFD is used as an optical sensor, it is necessary to make light incident from the substrate side.

The characteristics of the manufactured TFT are 600 ° C. of the conventional one.
There was nothing inferior to the one produced by the step of crystallizing by annealing. For example, the shift register manufactured according to this embodiment has a drain voltage of 15
Operation at 11 MHz at V and 16 MHz at 17 V was confirmed. Also, in the reliability test, no difference from the conventional one was found.

[0035]

According to the present invention, a crystalline silicon TFT is provided.
The number of processes for manufacturing a semiconductor circuit having an amorphous silicon diode can be reduced and mass productivity can be improved. Further, the present invention can also improve the throughput by crystallization of silicon at a low temperature of 500 ° C. and a short time of 4 hours, for example. In addition, conventionally, when a process of 600 ° C. or higher is adopted, shrinkage or warpage of the glass substrate has been a problem as a cause of a decrease in yield, but by using the present invention, such a problem is solved at once. Resulting in.

This means that a large area substrate can be processed at one time. That is, by processing a large-area substrate, a large number of integrated circuits or the like can be cut out from one substrate, whereby the unit price can be significantly reduced. Thus, the present invention is an industrially useful invention.

[Brief description of drawings]

1A to 1C are cross-sectional views of a manufacturing process of Example 1.

FIG. 2 shows the TFD obtained in Example 1 and its band diagram.

3A to 3C are sectional views showing a manufacturing process of the second embodiment.

FIG. 4 shows a conventional manufacturing process example (cross-sectional view).

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Substrate 11 ... Base insulating film (silicon oxide) 12 ... Amorphous silicon film 13 ... Nickel silicide film 14 ... Island silicon region 15 ... Gate insulating film (silicon oxide) 16・ ・ ・ Gate electrode and mask material (phosphorus-doped silicon) 17 ・ ・ ・ Doping mask (photoresist) 18 ・ ・ ・ TFT source and drain regions 19 ・ ・ ・ TFD impurity region / intrinsic region 20 ・ ・ ・Interlayer insulator (silicon oxide) 21 ... Metal wiring / electrode (titanium nitride / aluminum)

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁷ Identification symbol FI H01L 29/786 H01L 29/78 618G (56) References JP-A-4-206969 (JP, A) JP-A-5-63172 ( JP, JP-A 63-142807 (JP, A) JP-A 2-140915 (JP, A) JP-A 5-41512 (JP, A) JP-A 6-267988 (JP, A) JP Japanese Patent Laid-Open No. 6-267989 (JP, A) Japanese Patent Laid-Open No. 6-267980 (JP, A) Japanese Patent Laid-Open No. 6-267979 (JP, A) Japanese Patent Laid-Open No. 6-268212 (JP, A) Japanese Patent Laid-Open No. 6-268185 (JP , A) JP-A-6-244104 (JP, A) JP-A-6-260651 (JP, A) JP-A-6-244105 (JP, A) JP-A-6-244103 (JP, A) JP-A-6-244103 (JP, A) 6-275806 (JP, A) JP 6-275805 (JP, A) JP 6-275808 (JP, A) JP 20 00-299454 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L27 / 146 H01L 21/20 H01L 21/336 H01L 21/8234 H01L 27/06 H01L 29/786 JISST file ( JOIS)

Claims (10)

(57) [Claims] 1. A semiconductor circuit having a thin film transistor and a thin film diode on an insulating surface, wherein a semiconductor film in which a channel forming region, a source region and a drain region of the thin film transistor are formed, and an N type region of the thin film diode, a P type The semiconductor film in which the region and the intrinsic region are formed is the same layer, the channel formation region, the source region, and the drain region include an element that promotes crystallization of amorphous silicon, and the channel formation region is formed of crystalline silicon. And a semiconductor circuit in which the intrinsic region includes amorphous silicon. 2. The semiconductor circuit according to claim 1 , wherein the element that promotes crystallization of the amorphous silicon is nickel, iron, cobalt or platinum. 3. The concentration of an element which promotes crystallization of the amorphous silicon contained in the source region and the drain region according to claim 1 or 2 , is 1 × 10 ¹⁸ cm ⁻³ to 2
A semiconductor circuit having a size of × 10 ¹⁹ cm ^-3 . 4. The concentration of an element that promotes crystallization of amorphous silicon according to claim 3 , is a value measured by secondary ion mass spectrometry, and is a minimum value of the concentration distribution in the film thickness direction. A semiconductor circuit characterized by the above. 5. A first amorphous silicon film is formed on an insulating surface, and an element that selectively promotes crystallization of amorphous silicon is added to the first amorphous silicon film. Is heated to crystallize a region to which an element that promotes crystallization of the amorphous silicon is crystallized, and the first amorphous silicon film is patterned to form a crystalline silicon film to be a thin film transistor and a thin film diode to be a thin film diode. A second amorphous silicon film is formed, a gate electrode is formed on the crystalline silicon film, and a mask material is formed on the second amorphous silicon film, and the crystalline silicon film and the second amorphous silicon film are formed. A method for manufacturing a semiconductor circuit, which comprises adding an impurity to a film. 6. An amorphous silicon film is formed on an insulating surface, and an element that promotes crystallization of amorphous silicon is added to regions of the amorphous silicon film that will be a source region and a drain region of a thin film transistor. By patterning, a first amorphous silicon film to be the thin film transistor and a second amorphous silicon film to be the thin film diode are formed, a gate electrode is formed on the first amorphous silicon film, and the second amorphous film is formed. A mask material is formed on the silicon film, impurities are added to the first amorphous silicon film and the second amorphous silicon film, and the first amorphous silicon film and the second amorphous silicon film are heated. By the above The method for manufacturing a semiconductor circuit, which comprises crystallizing only amorphous silicon film. 7. The element according to claim 5 or 6 , wherein the element promoting crystallization of the amorphous silicon is nickel, iron,
A method for manufacturing a semiconductor circuit, which is cobalt or platinum. 8. The concentration of the element that promotes crystallization of the amorphous silicon according to any one of claims 5 to 7 , which is 1 × 10 ¹⁸ cm ⁻³ to 2 × 10 ¹⁹ cm ^−3. And a method for manufacturing a semiconductor circuit. 9. The concentration of an element that promotes crystallization of amorphous silicon according to claim 8 , which is a value measured by secondary ion mass spectrometry and is a minimum value of the concentration distribution in the film thickness direction. A method for manufacturing a semiconductor circuit, comprising: 10. The method according to any one of claims 5 to 9 ,
The method for manufacturing a semiconductor circuit, wherein the heating is performed in a hydrogen atmosphere.