JP3359689B2 - Semiconductor circuit and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a thin film transistor (T
FT) and a method of manufacturing the same. The thin film transistor manufactured by the present invention is formed on an insulating substrate such as glass and a semiconductor substrate such as single crystal silicon. In particular, the present invention relates to a semiconductor circuit having a low-speed operation matrix circuit and a high-speed operation peripheral circuit for driving the same, such as a monolithic active matrix circuit (used for a liquid crystal display or the like).

[0002]

2. Description of the Related Art In recent years, studies have been made on an insulating gate type semiconductor device having a thin-film active layer (also called an active region) on an insulating substrate. In particular, a thin film insulated gate transistor, a so-called thin film transistor (TFT), has been enthusiastically studied. These are formed on a transparent insulating substrate and are used for controlling each pixel or for a driving circuit in a display device such as a liquid crystal having a matrix structure. The amorphous silicon TFT and the crystalline silicon TFT are distinguished according to the crystalline state.

Generally, the electric field mobility of a semiconductor in an amorphous state is small, and therefore, a TF which requires high-speed operation is required.
Not available for T. Further, in the case of amorphous silicon, the P-type electric field mobility is extremely small, so that a P-channel TFT (PMOS TFT) cannot be manufactured.
T) and complementary MOS circuit (CMOS)
Cannot be formed.

[0004] However, a TFT formed of an amorphous semiconductor is characterized by a small OFF current. Therefore, as in the case of a transistor in a pixel circuit of an active matrix of a liquid crystal display, such a high-speed operation is not required, and only one conductivity type is sufficient and a TFT having a high charge retention capability is required. It's being used. However, it cannot be used for peripheral circuits that require high-speed operation.

On the other hand, a crystalline semiconductor has a higher electric field mobility than an amorphous semiconductor, and therefore can operate at high speed. In crystalline silicon, not only NMOS TFTs but also PMOS TFTs can be obtained in the same manner.
An S circuit can be formed. For example, in an active matrix type liquid crystal display device, a so-called monolithic structure in which not only the active matrix portion but also peripheral circuits (drivers and the like) are formed of CMOS crystalline TFTs is used. Are known.

However, the crystalline silicon TFT has a larger leakage current when no voltage is applied to the gate (when not selected) than the amorphous silicon TFT.
For use in a liquid crystal display, a measure has been taken to provide an auxiliary capacitor for compensating for the leak current, and to further reduce the leak current by connecting two TFTs in series.

FIG. 3 shows a block diagram of an active matrix circuit used for a liquid crystal display. Substrate 7
A column decoder 1 and a row decoder 2 are provided on the upper side as a peripheral driver circuit, and a pixel circuit 4 composed of a transistor and a capacitor is formed in a matrix region 3. Connected by The TFT used for the peripheral circuit operates at high speed,
In addition, a TFT used for a pixel circuit is required to have a low leakage current, but their characteristics are physically inconsistent, but they need to be formed on the same substrate by the same process.

[0008] Usually, to obtain crystalline silicon, 600 ° C
Long annealing at a temperature of about
Annealing at a high temperature of not less than ° C was necessary. For example, utilizing the high OFF resistance of amorphous silicon TFT,
Further, it was impossible to monolithically form a peripheral circuit of a polysilicon TFT having a high mobility on the same substrate because amorphous silicon was crystallized in the above annealing step.

[0009]

Although the present invention seeks to provide an answer to such a difficult problem, it is not desirable that the process becomes complicated, resulting in a decrease in yield and an increase in cost. . The gist of the present invention is to easily fabricate two types of TFTs, TFTs requiring high mobility and TFTs requiring low leakage current, while maintaining mass productivity by minimizing process changes. Is to divide.

[0010]

As a result of the research by the present inventors,
It has been found that the crystallization can be promoted by adding a small amount of a catalyst material to the silicon film in a substantially amorphous state, the crystallization temperature can be reduced, and the crystallization time can be shortened. As the catalyst material, a simple substance of nickel (Ni), iron (Fe), cobalt (Co), platinum (Pt), or a compound such as a silicide thereof is suitable. Specifically, films, particles, clusters, and the like having these catalyst elements are formed in close contact with or below the amorphous silicon film, or these catalyst elements are formed in the amorphous silicon film by a method such as ion implantation. And then crystallized by thermal annealing at a suitable temperature, typically at or below 580 ° C.

Further, when an amorphous silicon film is formed by a chemical vapor deposition method (CVD method), the amorphous silicon film is formed in a raw material gas. When an amorphous silicon film is formed by a physical vapor method such as sputtering, These catalyst materials may be added to a film-forming material such as a target or an evaporation source. As a matter of course, the higher the annealing temperature, the shorter the crystallization time. In addition, the higher the concentration of nickel, iron, cobalt and platinum, the lower the crystallization temperature and the shorter the crystallization time. According to the study of the present inventor, in order to promote crystallization, the concentration of at least one of these elements should be 1 × 10 ¹⁷ cm ⁻³ or more,
It has been found that it is necessary to preferably exist at 5 × 10 ¹⁸ cm ⁻³ or more.

Since the above-mentioned catalyst materials are all unfavorable materials for silicon, it is desirable that their concentrations be as low as possible. In the present inventors' research, it is desirable that the total concentration of these catalyst materials does not exceed 1 × 10 ²⁰ cm ⁻³ .

Further, it should be noted that an amorphous state can be maintained without crystallization at all in a region where such a catalyst material is not present. For example, it usually does not have such a catalyst material, typically its concentration is 1 × 10 ¹⁷ cm ⁻³ or less, preferably 1 × 1 ¹⁷ cm ^−3.
Crystallization of amorphous silicon of 0 ¹⁶ cm ^-3 or less is 60
It starts at a temperature of 0 ° C. or higher, but does not progress at a temperature of 580 ° C. or lower. However, in an atmosphere of 300 ° C. or more, hydrogen necessary for neutralizing dangling bonds in amorphous silicon is released, so that it is desirable that annealing be performed in a hydrogen atmosphere to obtain good semiconductor characteristics.

In the present invention, an amorphous silicon film is formed by utilizing the characteristics of crystallization by the above-mentioned catalyst material, and a part thereof is selectively crystallized to form a crystalline silicon TFT in a peripheral circuit of an active matrix circuit. And the other amorphous portion is used as an amorphous silicon TFT in a matrix region (pixel circuit). As a result, circuits having inconsistent transistors having low leakage current and high-speed operation can be simultaneously formed on the same substrate. Hereinafter, the present invention will be described in more detail with reference to Examples.

[0015]

[Embodiment 1] This embodiment shows an example in which a crystalline silicon TFT and an amorphous silicon TFT are formed on the same substrate by substantially the same process. FIG. 1 shows a cross-sectional view of a manufacturing process of this embodiment. First, a 2000-nm-thick silicon oxide base film 11 was formed on a substrate (Corning 7059) 10 by a sputtering method. Further, the thickness is 500 to 1500 by a plasma CVD method.
An intrinsic (I-type) amorphous silicon film 12 having a thickness of, for example, 1500 ° is deposited. Continuously, by sputtering, the thickness 5～200A, e.g. 20Å of nickel silicide film (chemical formula _{NiSi x, 0.4 ≦ x ≦ 2.5} , for example, x = 2.0) 13 as shown in FIG. Selectively formed. (Fig. 1 (A))

Then, this was annealed at 500 ° C. for 4 hours in a hydrogen reducing atmosphere (preferably, the partial pressure of hydrogen was 0.1 to 1 atm) to be crystallized. As a result, the amorphous silicon film below the nickel silicide film 13 crystallized to become the crystalline silicon film 12a. On the other hand, the silicon film in the region where the nickel silicide film did not exist was in the amorphous state (12b). (FIG. 1 (B))

The obtained silicon film is patterned by photolithography to form an island-like silicon region 14a.
(Crystalline silicon region) and 14b (amorphous silicon region). Further, a silicon oxide film 15 having a thickness of 1000 ° was deposited as a gate insulating film by a sputtering method. For sputtering, silicon oxide was used as a target, and the substrate temperature during sputtering was 200.
The sputtering atmosphere was oxygen and argon, and argon / oxygen = 0 to 0.5, for example, 0.1 or less. Subsequently, a silicon film (containing 0.1 to 2% of phosphorus) having a thickness of 6000 to 8000, for example, 6000, was deposited by a low pressure CVD method. It is desirable that the step of forming the silicon oxide and the silicon film be performed continuously. Then, the silicon film was patterned to form gate electrodes 16a, 16b and 16c. (Fig. 1 (C))

Next, impurities (phosphorus and boron) were implanted into the silicon region by a plasma doping method using the gate electrode as a mask. Phosphine (PH ₃ ) and diborane (B ₂ H ₆ ) were used as doping gases.
In the former case, the acceleration voltage is 60 to 90 kV, for example, 80 kV.
kV, in the latter case 40-80 kV, for example 65 kV
And The dose was 1 × 10 ¹⁵ to 8 × 10 ¹⁵ cm ⁻² , for example, phosphorus was 2 × 10 ¹⁵ cm ⁻² and boron was 5 × 10 ¹⁵ . As a result, P-type impurity regions 17a and N-type impurity regions 17b and 17c were formed. In this case, after doping with phosphorus, nickel is added in an amount of 1 × 10 ¹³ to 1
× 10 ¹⁵ cm ^-2, for example 5 to × 10 ¹⁴ cm ^-2 doping. (Fig. 1 (D))

Then, at 500 ° C. in a hydrogen reducing atmosphere,
The impurities were activated by annealing for a time. At this time, since nickel is diffused in the previously crystallized region 14a, recrystallization is easily progressed by this annealing, and the phosphorus-doped region 17c is also formed in the island-like semiconductor region 14b. Since nickel was also doped at the same time, it was sufficiently crystallized even with this degree of annealing. Thus, impurity regions 17a to 17a
c was activated. It should be noted that no nickel was present in the active region of the amorphous silicon TFT, so that it was not crystallized. Subsequently, a silicon oxide film 18 having a thickness of 6000.degree. Is formed as an interlayer insulator by a plasma CVD method, a contact hole is formed in the silicon oxide film 18, and a crystalline silicon TF is formed by a metal material such as a multilayer film of titanium nitride and aluminum.
T electrode / wiring 19a, 19b, 19c and amorphous silicon TFT electrode / wiring 19d, 19e were formed. Finally, annealing was performed at 350 ° C. for 30 minutes in a hydrogen atmosphere at 1 atm. The semiconductor circuit was completed by the above steps. (FIG. 1 (E)) When the concentration of nickel contained in the active region of the obtained TFT was measured by a secondary ion mass spectrometry (SIMS) method, the crystal silicon TFT showed a concentration of 1 × 10 ^{18 to} 5 × 10 5
Nickel of ¹⁸ cm ⁻³ was observed, but nickel was less than the measurement limit (1 × 10 ¹⁶ cm ⁻³ ) in amorphous silicon.

[Embodiment 2] In this embodiment, a crystalline silicon TFT is used for a peripheral driver circuit, and an amorphous silicon TFT is used for a pixel circuit. FIG. 2 shows a cross-sectional view of the manufacturing process of this embodiment. Substrate (Corning 7
059) Sputtering on 20 with thickness of 500-
A tantalum film of 2000 °, for example, 1000 ° is formed, and is patterned to form amorphous silicon TF.
A gate electrode wiring 21 of T was formed. The thickness of the tantalum wiring is 1000 to 3000 by anodic oxidation.
The anodic oxide film 22 is provided, for example, 1500 °.

Then, a silicon oxide film 23 having a thickness of 2000 ° was formed by a sputtering method. This silicon oxide film 23 functions not only as a gate insulating film of the amorphous silicon TFT but also as a base insulating film of the crystalline silicon TFT. Thereafter, an amorphous silicon film 24 having a thickness of 200 to 1500 °, for example, 500 ° was deposited by a plasma CVD method. Then, the amorphous silicon film 24 is masked with a photoresist 25, and nickel ions are selectively implanted by an ion implantation method, so that nickel is 1 × 10 ¹⁸ to 2 × 10 ¹⁹ cm ⁻³ , for example, 5 × 10 ¹⁸ cm ⁻³ . A region 26 containing only ^-3 was prepared.

The depth of the region 26 was set at 200 to 500 °, and the optimum acceleration energy was selected in accordance with the depth. Further, nickel is not injected into a region to be an active region in the crystalline silicon TFT.
However, the channel length is 20 μm or less, preferably 10 μm.
m or less. With a longer channel length, the entire active region could not be crystallized. (Fig. 2 (A))

Then, under a hydrogen atmosphere of 0.1 to 1 atm.
Annealing was performed at 550 ° C. for 8 hours for crystallization. By this crystallization step, not only the region into which nickel was implanted, but also the region sandwiched between the regions and the periphery thereof (indicated by 24a in FIG. 2B) were crystallized. By annealing at 550 ° C. for 8 hours, crystallization of about 10 μm progressed in the lateral direction. On the other hand, the region 24b where nickel was not implanted remained in an amorphous state. (FIG. 2 (B))

Thereafter, the silicon film was patterned to form island-like silicon regions 27a (crystalline silicon regions) and 27b (amorphous silicon regions). Further, tetraethoxysilane (Si (OC ₂ H ₅ )
₄ , TEOS) and oxygen were used as raw materials, and a silicon oxide 28 having a thickness of 1000 Å was formed as a gate insulating film of a crystalline silicon TFT by a plasma CVD method. The raw materials include, in addition to the above gases, trichloroethylene (C ₂ HCl ₃ )
Was used. 400 SCCM oxygen in chamber before film formation
Flow, substrate temperature 300 ° C, total pressure 5Pa, RF power 15
Plasma was generated at 0 W, and this state was maintained for 10 minutes.
Then, a silicon oxide film was formed by introducing 300 SCCM of oxygen, 15 SCCM of TEOS, and 2 SCCM of trichloroethylene into the chamber. Substrate temperature, RF
The power and total pressure were 300 ° C., 75 W, and 5 Pa, respectively. After the film formation was completed, 100 Torr of hydrogen was introduced into the chamber, and hydrogen annealing was performed at 350 ° C. for 35 minutes.

Subsequently, by a sputtering method,
An aluminum film (containing 2% silicon) having a thickness of 6000 to 8000, for example, 6000, was deposited. Tantalum, titanium, tungsten, or molybdenum may be used instead of aluminum. It is desirable that the step of forming the silicon oxide 28 and the aluminum film be performed continuously.
Then, the aluminum film was patterned to form gate electrodes 29a and 29b of the TFT. Further, the surface of the aluminum wiring was anodized to form an oxide layer on the surface. Anodization was performed in a 1-5% solution of tartaric acid in ethylene glycol. The thickness of the obtained oxide layer was 2000 °. In addition, a photoresist mask 30 was formed on the silicon of the amorphous silicon TFT in self-alignment with the gate electrode 21 by exposure from the back surface. (Fig. 2 (C))

Next, an impurity (phosphorus) was implanted into the silicon region by a plasma doping method. Phosphine (PH ₃ ) was used as the doping gas, and the accelerating voltage was 6
0 to 90 kV, for example, 80 kV. Dose amount is 1 ×
10 ¹⁵ to 8 × 10 ¹⁵ cm ⁻² , for example, 2 × 10 ¹⁵ cm ⁻²
And Thus, N-type impurity regions 31a and 31c were formed. Further, this time, the left crystalline silicon TFT (N-channel TFT) and the amorphous silicon TFT (matrix region) are masked with a photoresist, and the silicon region of the right crystalline silicon TFT (P-channel TFT) is again formed by the plasma doping method. (Boron) was implanted. As a doping gas, diborane (B ₂ H ₆ ) was used, the acceleration voltage was 50 to 80 kV,
For example, it was set to 65 kV. Dose amount is 1 × 10 ¹⁵ to 8 × 1
0 ¹⁵ cm ^-2 , for example 5 × 1 more than the previously implanted phosphorus
It was set to 0 ¹⁵ cm ^-2 . Thus, the P-type impurity region 3
1b was formed.

Thereafter, the impurities were activated by laser annealing. As a laser, a KrF excimer laser (wavelength 248 nm, pulse width 20 ns)
Although c) was used, other lasers, for example, XeF excimer laser (wavelength 353 nm), XeCl excimer laser (wavelength 308 nm), ArF excimer laser (wavelength 193 nm), and the like may be used. The energy density of the laser was 200 to 400 mJ / cm ² , for example, 250 mJ / cm ^2, and ² to 10 shots, for example, 2 shots were irradiated at one location. During laser irradiation, the substrate may be heated to about 200 to 450 ° C. It should be noted that when the substrate is heated, the optimum laser energy density changes with temperature. The active region of the amorphous silicon TFT was not crystallized because the mask 30 was present thereon. As a result, the impurity regions 31a and 31b of the crystalline silicon TFT and the impurity region 31c of the amorphous silicon TFT were activated. (FIG. 2 (D))

Subsequently, as an interlayer insulating material, a thickness of 2000
CV using TEOS as a raw material for silicon oxide film 32
The indium tin oxide film (ITO) having a thickness of 500 to 1000 Å, for example, 800 に よ っ て was deposited by a sputtering method. Then, this was etched to form the pixel electrode 33. Further, a contact hole is formed in the interlayer insulator 32, and a metal material,
For example, the source and drain electrodes / wirings 34a, 34b, 34c of the crystalline silicon TFT (peripheral driver circuit) and the electrodes / wiring 34 of the amorphous silicon TFT (pixel circuit) are formed of a multilayer film of titanium nitride and aluminum.
d, 34e were formed. The semiconductor circuit was completed by the above steps. (FIG. 2 (E))

In the manufactured semiconductor circuit, the characteristics of the crystalline silicon TFT (peripheral driver circuit) are 60
There was nothing inferior to those produced by the step of crystallization by annealing at 0 ° C. For example, it was confirmed that the shift register manufactured according to this embodiment operates at 11 MHz at a drain voltage of 15 V and at 16 MHz at 17 V. No difference was found in the reliability test from the conventional one. Furthermore, amorphous silicon T
Regarding the characteristics of the FT (pixel circuit), the leakage current is 10
^-13 A or less.

[0030]

According to the present invention, crystalline silicon TF capable of operating at high speed on the same substrate by the same process
Amorphous silicon T featuring T and low leakage current
FT could be formed. When this is applied to a liquid crystal display, improvement of mass productivity and improvement of characteristics can be achieved.

The present invention can also improve the throughput by crystallizing silicon at a low temperature of, for example, 500 ° C. and a short time of 4 hours. In addition, conventionally, when a process at 600 ° C. or higher was employed, shrinkage or warpage of a glass substrate had been a problem as a cause of a decrease in yield. However, such a problem can be solved at a stretch by using the present invention. Resulting in.

This means that a large area substrate can be processed at one time. That is, by processing a large-area substrate, a large number of semiconductor circuits (such as a target circuit) can be cut out from one substrate, so that the unit price can be significantly reduced. Thus, the present invention is an industrially useful invention.

[Brief description of the drawings]

FIG. 1 shows a cross-sectional view of a manufacturing process in Example 1.

FIG. 2 shows a cross-sectional view of a manufacturing process in Example 2.

FIG. 3 shows a configuration example of a monolithic active matrix circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Substrate 11 ... Base insulating film (silicon oxide) 12 ... Amorphous silicon film 13 ... Nickel silicide film 14 ... Island-shaped silicon region 15 ... Gate insulating film (silicon oxide) 16 ... Gate electrode (phosphorus-doped silicon) 17 ... Source / drain region 18 ... Interlayer insulator 19 ... Metal wiring / electrode (Titanium nitride / aluminum)

──────────────────────────────────────────────────続 き Continued on the front page (56) References JP-A-6-268212 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29/786 H01L 21/20 H01L 21 / 336 G02F 1/1368

Claims (13)

(57) [Claims] 1. A semiconductor circuit comprising: a first thin film transistor having an active region made of an amorphous silicon film; and a second thin film transistor having an active region made of a crystalline silicon film. The concentration of a metal element that promotes crystallization of silicon is less than 10 ¹⁷ cm ⁻³ , and the concentration of a metal element that promotes crystallization of amorphous silicon in the crystalline silicon film is 1 × 10 ¹⁷ to 1 × 10 7
A semiconductor circuit having a size of ²⁰ cm ^-3 . 2. A semiconductor circuit comprising: a first thin film transistor having an active region formed of an amorphous silicon film; and a second thin film transistor having an active region formed of a crystalline silicon film. The amorphous silicon film is provided in contact with the same insulating film, a concentration of a metal element for promoting crystallization of the amorphous silicon in the amorphous silicon film is less than 10 ¹⁷ cm ⁻³ , and an amorphous silicon in the crystalline silicon film is The concentration of the metal element that promotes crystallization of 1 × 10 ¹⁷ to 1 × 10
A semiconductor circuit having a size of ²⁰ cm ^-3 . 3. A semiconductor circuit comprising: a first thin film transistor having an active region made of an amorphous silicon film; and a second thin film transistor having an active region made of a crystalline silicon film, wherein the first thin film transistor is: A gate electrode, the insulating film provided on the gate electrode, and the amorphous silicon film provided on the insulating film, wherein the second thin film transistor is provided on the insulating film and on the insulating film. The crystalline silicon film provided in contact with the substrate, and a gate electrode provided on the crystalline silicon film. The concentration of the metal element for promoting crystallization of amorphous silicon in the amorphous silicon film is 10%. ¹⁷ is less than cm ^-3, the concentration of the metal element for promoting crystallization of amorphous silicon of the crystalline silicon film is 1 10 ¹⁷ ~1 × 10
A semiconductor circuit having a size of ²⁰ cm ^-3 . 4. The semiconductor circuit according to claim 2, wherein the insulating film is a silicon oxide film . 5. The method according to claim 1, wherein:
A semiconductor circuit, wherein the concentration of a metal element that promotes crystallization of amorphous silicon is defined by a minimum value measured by a secondary ion mass spectrometry. 6. The method according to claim 1, wherein
A semiconductor circuit, wherein the metal element that promotes crystallization of amorphous silicon is at least one of nickel, iron, cobalt, and platinum. 7. An amorphous silicon film is formed by selectively adhering a substance having a metal element that promotes crystallization of amorphous silicon to the amorphous silicon film, and heating the amorphous silicon film. Crystallizing the amorphous silicon film at a portion where a metal element for promoting crystallization is adhered, and patterning the amorphous silicon film to form a region made of amorphous silicon and a region made of crystallized silicon; The region made of amorphous silicon and the crystallized region
A thin-film transistor on each of the
A method for manufacturing a semiconductor circuit, comprising: 8. An amorphous silicon film is formed, a film containing a metal element for promoting crystallization of amorphous silicon is selectively formed on the amorphous silicon film, and the amorphous silicon film is heated to form the amorphous silicon film. Crystallizing the amorphous silicon film in a portion where a metal element for promoting crystallization of silicon is formed, and patterning the amorphous silicon film to form a region made of amorphous silicon and a region made of crystallized silicon The region made of amorphous silicon and the crystallized region
A thin-film transistor on each of the
A method for manufacturing a semiconductor circuit, comprising: 9. The method of claim 8, a film having a metal element for promoting crystallization of the amorphous silicon, a method for manufacturing a semiconductor circuit, wherein the a film of a compound of a metal element and silicon. 10. An amorphous silicon film is formed, a metal element for promoting crystallization of amorphous silicon is selectively added to the amorphous silicon film, and the amorphous silicon film is heated by heating the amorphous silicon film. to crystallize the amorphous silicon film portion adding a metal element for promoting the amorphous silicon film is patterned to form a region made of amorphous silicon, a region made of crystallized silicon, said amorphous Silicon region and said crystallized region
A thin-film transistor on each of the
A method for manufacturing a semiconductor circuit, comprising: 11. A method for manufacturing a semiconductor circuit in which a thin film transistor is formed in first and second regions, wherein a first gate electrode is formed in the first region, and the first and second regions are formed. Forming an insulating film so as to cover above the first gate electrode in the region; forming an amorphous silicon film on the insulating film in the first and second regions; and forming the amorphous silicon film in the second region. A silicon element is selectively added with a metal element that promotes crystallization of amorphous silicon, and the region to which the metal element is added is crystallized by heating the amorphous silicon film, and the amorphous silicon film is patterned. Forming a region made of amorphous silicon and a region made of crystallized silicon, The method for manufacturing a semiconductor circuit and forming a second gate electrode on that region. 12. The semiconductor circuit according to claim 7, wherein the metal element for promoting crystallization of the amorphous silicon is at least one of nickel, iron, cobalt, and platinum. Production method. 13. The concentration of a metal element which promotes crystallization of amorphous silicon in a region made of amorphous silicon according to claim 7,
Less than ¹⁷ cm ^-3 , and the concentration of the metal element that promotes crystallization of amorphous silicon in the crystallized silicon region is 1 × 10
^A method for manufacturing a semiconductor circuit, which is ¹⁷ to 1 × 10 ²⁰ cm ⁻³ .