JP3398045B2 - Display drive circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [0001] The present invention relates to a display driving circuit.
I do. [0002] FIG. 8 is a block diagram showing a conventional display driving circuit.
FIG. 2 is a diagram illustrating a configuration integrated on the same chip. In FIG. 8, (1) is an interface
Circuit, from an external device (microcomputer, etc.)
Operation enable signal CE, clock signal CL, write
Various data DI are supplied. FIG. 1 shows a specific example of an interface circuit (1).
It is shown in FIG. In FIG. 9, (2) is an address register.
The chip enable signal CE is “L” (low level).
8) in the state shown in FIG.
Address data (for example, 8 bits) with the clock signal CL.
It is expected to be kept. (3) is an address decoder
And whether the value of the address register (2) is a normal value
It is determined whether or not the value of the address register (2) is a normal value.
It outputs "H" (high level) when there is
You. The determination operation by the address decoder (3) ends.
Then, the operation permission signal CE changes from “L” to “H”.
The operation permission signal CE is supplied to one input terminal of the AND gate (4).
And a delay circuit (5) and an inverter
(6) to the other input terminal of the AND gate (4)
Supplied. That is, the operation permission signal CE changes from "L"
When rising to "H", the AND gate (4)
An “H” pulse signal is output. On the other hand, the operation permission signal
CE is supplied to one input terminal of the OR gate (7).
And O via a delay circuit (5) and an inverter (6).
It is supplied to the other input terminal of the R gate (7). That is,
When the operation permission signal CE falls from “H” to “L”,
An "L" pulse signal is output from the OR gate (7).
You. (8) is a D-type flip-flop whose D terminal is
Connected to the output of the dress decoder (3), and the C terminal is connected to AN.
Connected to the output of D gate (4), R terminal is OR gate
It is connected with the output of (7) inverted. Therefore,
The D-type flip-flop (8) outputs the operation enable signal CE.
Address decoder when changed from "L" to "H"
The “H” output of (3) is held. From this, AND game
(9) and (10) are open, and the AND gate (9)
From the various data D for writing to the subsequent memory.
I (hereinafter SDI) is output, and the AND gate (10)
Output a clock signal CL (hereinafter SCL). I
The output of the interface circuit (1) is a shift register (example
For example, 24 bits), and various data SDI are
Supply to shift register in synchronization with clock signal SCL
Is done. All bits of various data SDI are shift registers
, The operation permission signal CE changes from “H” to “L”.
And the D-type flip-flop (8) is reset
AND gates (9) and (10) are closed and shift
The shift operation of the register stops. Returning to FIG. 8, (11) shows the shift register described above.
And various data for writing to the memory.
Data SDI (24 bits: D0-D23)
Serial input is performed in synchronization with SCL. shift
The register (11) has 24 D-type flip-flops (see FIG.
(Not shown) in cascade connection
It has a barrel output form. In addition, various data S
DI stores address data, display data, instruction codes, etc.
Including. (12) Character generator ROM
Character to be displayed on the display panel (not shown).
Character data (for example, 5 horizontal x 7 vertical dots)
Is stored. The character generator
The ROM (12) is a nonvolatile memory such as a mask ROM.
Character data that is unlikely to be changed during the manufacturing
Is stored. (13) is character generator RAM
And is the same as the character generator ROM (12).
The characters representing other characters to be displayed on the display panel
This is where the tractor data is stored. The character
Generator RAM (13) is a volatile memo such as SRAM
Character data that is likely to change
Stored as needed under the control of the device
You. (14) is a display RAM, which is a character generator.
Data ROM (12) and character generator RAM
Character code for addressing (13) is displayed.
Is stored at the address corresponding to each digit on the display panel.
is there. For example, if the display panel has 64 digits, the first digit
The address of the corresponding display RAM (14) is 00H (H:
Display RAM corresponding to the 64th digit
The address of (14) is added by +1 to 3FH.
You. (15) is an accessory RAM, which is displayed on the display panel.
Accessory data indicating information other than the characters to be displayed
Is stored at the address corresponding to each digit on the display panel
Things. For example, if the accessory information has 16
Of the accessory RAM (15) corresponding to the first digit
If the address is 0H, the accessory RAM corresponding to the 16th digit
The address of (15) is added by +1 to become FH.
The accessory RAM (15) has a character generator.
Volatile memory such as SRAM as well as data RAM (13)
And the accessory data can be rewritten as needed
It is. (16) Character code and accessor
Address counter for reading re-data
6-bit address data DCR for RAM (14)
DA0 to DCRDA5 are supplied and the accessory RAM (1
For 5), 4-bit address data ADRDA0 to ADDRA-A
Supply DRDA3. (17) is an instruction decoder
Yes, the character is stored in the character generator RAM (13).
Signal WCCK, display RA for writing
Command signal for writing character code to M (14)
Accessory data in WDCK and accessory RAM (15)
Command signal WACK for writing data
You. [0009] The components of the instruction decoder (17)
A body example is shown in FIG. In FIG. 10, (18) is deco
And the instruction code held by the shift register (11).
The instruction signal WCC according to the decoding result of the code D20 to D23
Signals WCENB, W on which K, WDCK, and WACK are based
Selectively generates one of DENB and WAENB
Things. D type inside the interface circuit (1)
The output DIENB of the lip flop (8) is the NOR gate.
(19) and the delay time
NOR gate via the road (20) and the inverter (21)
(19) to the other input terminal. That is, NO
From the R gate (19), the shift register (11)
After the shift operation for 4 bits is completed, the signal DIENB becomes
When "H" changes to "L", the "H" pulse signal
Is output. The output of the NOR gate (19) is an AND gate.
(22), (23), and (24).
And the signals WDENB, WAENB, WCENB are AND
Gate (22) (23) (24)
Be paid. Therefore, the AND gates (22), (23), (2)
From 4), the output of the NOR gate (19) becomes "H".
Command signals WDCK, WACK, WCCK
Is forced. FIG. 11 shows a specific example of the display RAM (14).
You. In FIG. 11, (25) is a volatile cell array.
Yes, read enable terminal OE, write enable terminal WE,
Address terminals A0 to A5, data input / output terminals IO0 to I
It has O7. (26-0) to (26-5) are two A
A switching circuit comprising an ND gate and one OR gate;
To form each of the switching circuits (26-0) to (26-5).
Read one input terminal of the AND gate at the top of the drawing
Address data DCRDA0 to DCRDA5 are supplied
The switching signal DCRWCT is supplied to the other input terminal.
Is done. On the other hand, each switching circuit (26-0) to (26-5)
To one input terminal of the AND gate at the bottom of the drawing
Is the write address held by the shift register (11).
Data D8 to D13 are supplied to the other input terminal.
Are supplied with the switching signal DCRWCT inverted. (27
−0) to (27-5) are latch circuits.
Switching terminals (2-0) are connected to L terminals of (27-0) to (27-5).
6-0) to (26-5), the output of the OR gate
Clock signal DCLCK is supplied to the C terminal.
The output of the Q terminal is the address terminal of the cell array (25).
It is supplied to A0 to A5. The read enable signal DCOE is
It is supplied to the read permission terminal OE. (28) is written
Only the enable signal generation circuit
When the command signal WDCK is supplied from the
Generate write enable signal DCWE at timing and write
It is supplied to only the permission terminal WE. Shift register
Character codes D0 to D7 held by (11)
Data input / output via files (29-0) to (29-7)
It is supplied to terminals IO0-IO7. [0011] Character code from display RAM (14)
Is read, the switching signal DCRWCT becomes “H”.
Address output from the address counter (16).
The data DCRDA0 to DCRDA5 correspond to the switching circuit (26-
0) to (26-5). afterwards,
The clock signal DCLCK becomes “H” and the address data
Data DCRDA0 to DCRDA5 are latch circuits (27-
0) to (27-5). That is, the display RAM
Address data DCRDA of all addresses in (14)
An address corresponding to 0 to DCRDA5 is designated. So
After that, the read permission signal DCOE changes to "H" and the display
Character code D from specified address in RAM (14)
CDT0 to DCDT7 are read. At this time,
The signal DCWRDT is "L" and the buffers (29-0) to (2
9-7) is in a high impedance state.
Character codes DCDT0 to DCDT7 at the time of protrusion
Interference with character codes D0 to D7 at the time of writing
And not. A character code is stored in the display RAM (14).
When writing, the switching signal DCRWCT becomes "L",
Address data D8 held by the shift register (11)
D13 through the switching circuits (26-0) to (26-5)
Output. Then, the clock signal DCLCK is
"H", and the address data D8 to D13 are latched
Latched at the roads (27-0) to (27-5). That is,
Address data of all addresses in the display RAM (14)
Addresses corresponding to D8 to D13 are specified. That
Thereafter, the write enable signal DCWE becomes “H” and the display R
Character codes D0 to AM (14) specified address
D7 is written. FIG. 1 shows a specific example of the accessory RAM (15).
It is shown in FIG. In FIG. 12, (30) is a volatile cell.
, Read enable terminal OE, write enable terminal
WE, address terminals A0 to A3, data input / output terminal IO
0 to IO4. (31-0) to (31-3) are 2
Switching circuit consisting of two AND gates and one OR gate
And each of the switching circuits (31-0) to (31-3)
One input terminal of the AND gate at the top of the drawing
Address data ADRDA0 to ADRDA3 for readout
Is supplied to the other input terminal and the switching signal ADRWCT
Is supplied. On the other hand, each of the switching circuits (31-0) to (31)
-3) one input of the AND gate at the bottom of the drawing
The terminal is for writing that is held by the shift register (11).
Are supplied, and the other input data
The switching signal ADRWCT is supplied to the terminal in an inverted manner.
(32-0) to (32-3) are latch circuits.
The switching terminals are connected to the L terminals of the switches (32-0) to (32-3).
Of OR gates constituting paths (31-0) to (31-3)
The output is supplied, and the clock signal ADLCK is
The output of the Q terminal is supplied to the address of the cell array (30).
Are supplied to the terminals A0 to A3. Read enable signal AD
OE is supplied to the read permission terminal OE. (33) is
Write enable signal generation circuit
A command signal WACK is supplied from the decoder (17).
And a write enable signal ADWE is generated at a predetermined timing.
It is supplied to the write enable terminal WE. shift
Accessory data D0 to D held by register (11)
4 is the data through buffers (33-0) to (33-4).
It is supplied to the data input / output terminals IO0 to IO4. Accessory RAM (15) to Accessory
When reading data, the switching signal ADRWCT is set to "H".
And the address output from the address counter (16).
Data ADRDA0 to ADRDA3 are provided by the switching circuit (3
1-0) through (31-3). That
Then, the clock signal ADLCK becomes “H” and the address
The data ADRDA0 to ADRDA3 are stored in the latch circuit (32
−0) to (32-3). That is, the accessor
Address data A among all addresses of the re-RAM (15)
An address corresponding to DRDA0 to ADRDA3 is specified.
It is. Thereafter, the read permission signal ADOE becomes “H”.
Access from the specified address of the accessory RAM (15).
Sesary data ADDT0 to ADDT4 are read.
At this time, when the signal ADWRDT is "L" and the buffer (3
3-0) to (33-4) enter the high impedance state.
The accessory data ADDT0 at the time of reading.
To ADDT4 are accessory data D0 to D at the time of writing.
4 does not interfere. An accessory data is stored in the accessory RAM (15).
When writing data, the switching signal ADRWCT changes to "L".
Address data held by the shift register (11).
Switches D8 to D11 are switching circuits (31-0) to (31-3)
Is output via. After that, the clock signal ADLCK
Becomes "H" and the address data D8 to D11 are latched.
Latched by the circuits (32-0) to (32-3). Immediately
Of all addresses in the accessory RAM (15),
Address corresponding to the address data D8 to D11 is specified.
You. Thereafter, the write enable signal ADWE becomes “H”.
Access the specified address in the accessory RAM (15).
Sali data D0 to D4 are written. The display RAM (14), accessory RA
Character code and accessory data for M (15)
Is written, all 24 bits of the shift register (11)
After changing the data. Returning to FIG. 8, for example, the number of display panels is 60.
Matrix electrodes and eight common electrodes
Is placed. That is, the character font is horizontal 5X
In the case of 7 dots vertically, the display panel displays 12 characters
It becomes possible. Note that one common electrode is
Used for display. (34) is a latch circuit,
Information to be displayed on one horizontal line of the display panel
Generator ROM (12), character generator R
Import from AM (13) and accessory RAM (15)
Latch. (35) is a segment drive circuit
And the output terminals SEG1 to SEG60 are connected to the display panel.
Connected to 60 segment electrodes, the latch circuit (3
Turn on or off the segment electrode according to the value of 4)
The driving signal is output. (36) is Como
Output terminals COM1 to COM8 display
Connected to the eight common electrodes of the panel, the segment electrodes
Drive signal for activating the motor at a predetermined frequency.
The next output is. (37) is timing signal generation
It is a circuit that synchronizes each block and
Items that reliably display tractor information and accessory information
It is. [0018] Now, segment driving.
Signals SEG1 to SEG60 and common drive signal COM1
~ COM8, 60 x 8 dots
Once, character information and accessory information are displayed in the
When the display contents are changed after the display, the display RAM (1
4) and the contents of the accessory RAM (15) must be changed.
I have to. That is, the contents of the shift register (11) are
Must be changed. However, in the display of the display panel
When changing the contents over each digit, the display RAM (14) or
Enter the write start address of the accessory RAM (15).
After writing the character code or accessory data
Also, an address obtained by sequentially adding +1 from the write start address
Character data or accessory data for dress data
And transfer it to the shift register (11).
No longer. Therefore, external devices (microcomputer
) To the shift register (11)
The number of data bits increases, and as a result, external devices
There was a problem that the burden of software processing on the side became heavy.
In particular, this problem significantly changes the information displayed on the display panel.
When it is made to appear, it appears remarkably. Accordingly, the present invention provides a method for displaying information on a display panel.
Drive that can reduce the burden on the external device for changing the display
It is intended to provide a circuit. [0020] The present invention solves the above problems.
This is done to determine the
This is a circuit for displaying characters, and displays characters.
Display memory means for storing display data;
Based on the display data read from the memory means
A character corresponding to the display data is displayed on the display panel.
Panel driving means to be displayed, and writing of the display memory means
For storing address data and display data for
A display drive circuit comprising:
Indicating memory meansCounting means for counting the address data of
The register means stores the write address data;
Instruction decoding means for decoding the instruction code held together;
Wherein the counting means comprises:
When the code is decoded and the first command signal is output,
The register means holds the instruction code together with the instruction code.
Write address data is initially stored in the display memory means.
The command decoding means then supplies the command value.
Each time a second command signal that does not require a code is output,
The write address data is sequentially incremented.
And supplying it to the display memory means.Characterized by
You. Further, the register means is adapted to write display data.
Instruction code, and the instruction code
Reading means, and according to the decoding result of the instruction decoding means.
Wherein the counting means starts counting operation.
You. [0022] BRIEF DESCRIPTION OF THE DRAWINGS FIG.
Will be explained. FIG. 1 is a block diagram showing a display driving circuit according to the present invention.
FIG. In FIG. 1, the same blocks as those in FIG.
Therefore, the same reference numerals are given and the description is omitted. In FIG. 1, reference numeral 38 denotes a display RAM.
Character generator ROM (12) and character
To address the generator generator RAM (13)
Characters corresponding to each digit on the display panel
Is stored in the address. For example, if the display panel is 6
In the case of four digits, the address of the display RAM (38) corresponding to the first digit is
64th digit if the dress is 00H (H: hexadecimal)
The address of the display RAM (14) corresponding to
It is calculated as 3FH. (39) is an accessory RAM
Yes, information other than characters to be displayed on the display panel
The accessory data to be displayed corresponds to each digit on the display panel.
It is stored in the dress. For example, accessory information
If there are 16 types of information, the accessory RA corresponding to the first digit
If the address of M (39) is 0H, it corresponds to the 16th digit
The address of the accessory RAM (39) is incremented by +1
To FH. Note that the accessory RAM (39)
SRAM similar to the character generator RAM (13)
Volatile memory, etc.
Data can be rewritten. (40) is an instruction decoder
And the instruction code D held by the shift register (11)
Character generator according to the decoding result of 20 to D23
Data RAM (13), display RAM, (38), accessor
A command signal for rewriting the contents of the re-RAM (39) is issued.
It is the one that produces it. Instruction decoder (4
FIG. 2 shows a specific example of (0). 2 is the same as FIG. 10
The same numbers are given to the components and the description is omitted. Figure
In (2), (41) is a counter,
Output from the AND gate (10) inside the chair circuit (1).
The clock signal SCL is counted. Paraphrase
Then, the counter (41) is stored in the shift register (11).
Counts the number of bits of various data SDI transferred serially
Is what you do. The counter (41) receives the clock signal S
When CL is counted 24 times, a signal SCL24B is output,
When the clock signal SCL is counted 16 times, the signal SCL1
6B is output and the clock signal SCL is counted eight times.
The signal SCL08B is output. The counter (41)
Any of the signals SCL24B, SCL16B and SCL08B
Or a new signal is generated.
Then, the current signal disappears. D16 is a shift register
(11) of various data SDI serially transferred to
1 bit, indicating R to shift register (11)
Ad for AM (38) or Accessory RAM (39)
"L" when shift data is supplied, shift register
(11) display RAM (38) or accessory RA
When not supplying address data for M (39)
This is a control bit that becomes “H”. When the signal DIENB falls, the instruction signal
The signal WDCK is generated and the signal SCL24B is generated.
From the AND gate (42), the display RAM (38)
With address data added to the character code,
Command signal WDNR to be supplied to the shift register (11)
CK is output. The signal SCL24B and the signal SCL16B are
One of the AND gate (44) through the OR gate (43)
Command signal WDCK is supplied to the
To the other input terminal of the port (44). D type free
The flip-flop (45) is connected to the output of the AND gate (44).
The control bit D16 is synchronously held. D type
The flip-flop (46) is activated when the signal DIENB rises.
Output signal IMCK of the AND gate (47)
Holds the output of D-type flip-flop (45) in synchronization with
Is what you do. That is, the D-type flip-flop (46)
Is the output of the signal SCL24B or the signal SCL16B.
"H" when signal IMCK occurs during the live period or
It becomes "L". The output of the D-type flip-flop (46)
In the state of "H", the command signal WDCK is generated and the signal SC
When L16B occurs, a table is output from the AND gate (47).
Increment the address of the indication RAM (38) by +1
Command signal WDIMCK is output. In addition, D-type
NOR when the output of the lip flop (46) is "H"
The output signal LCK of the gate (19) is generated and the signal SC
When L08B occurs, an instruction is issued from the AND gate (48).
Command signal WDIMCK is output. AND gate (4
7) The command signal WDIMCK output from (48) is O
The signal is output via the R gate (49). When the signal DIENB falls, the instruction signal
A signal WACK is generated and a signal SCL24B is generated.
And from the AND gate (50), the accessory RAM (3
9) Address data added to accessory data
Signal W for supplying to the shift register (11) in the state
ANRCK is output. The signal SCL24B and the signal SCL16B are
One of the AND gate (51) through the OR gate (43)
Command signal WACK is supplied to one of the input terminals
Port (51) is supplied to the other input terminal. D type free
The flip-flop (52) is connected to the output of the AND gate (51).
The control bit D16 is synchronously held. D type
The flip-flop (53) is activated when the signal DIENB rises.
Output signal IMCK of the AND gate (47)
Holds the output of D-type flip-flop (52) in synchronization with
Is what you do. That is, the D-type flip-flop (53)
Is the output of the signal SCL24B or the signal SCL16B.
"H" when signal IMCK occurs during the live period or
It becomes "L". The output of the D-type flip-flop (53)
In the state of "H", the command signal WACK is generated and the signal SC
When L16B occurs, an AND signal is output from the AND gate (54).
The address of the accessory RAM (39) is incremented by +1.
Command signal WAIMCK is output. Also,
When the output of the D-type flip-flop (53) is "H"
The output signal LCK of the NOR gate (19) is generated and further
When signal SCL08B occurs, the AND gate (55)
They also output a command signal WAIMCK. AND gate
(54) Command signal WAIMCK output from (55)
Is output via an OR gate (56). (57) is a character code and accessor.
Address counter for writing re-data
6-bit address data DCW for RAM (38)
RA0 to DCWRA5 are supplied, and the accessory RAM (3
9), 4-bit address data ADWRA0-ADWRA-A
Supply DWRA3. FIG. 3 shows an address card for writing.
A specific example of the counter (57) will be described. In FIG. 3, (5
8) is an address counter for the display RAM (38).
When the command signal WDNRCK is supplied, the shift register
Address data D8 to D set from the master (11)
13 is output as it is as DCWRA0 to DCWRA5
However, when the command signal WDIMCK is supplied, the current address
+1 increment the address data DCWRA0 to DCWRA5
And output it. On the other hand, (59)
It is an address counter for Sesary RAM (39),
When the command signal WANRCK is supplied, the shift register
Address data D8 to D11 set from (11)
Are output as ADWRA0 to ADWRA3 as they are,
When the command signal WAIMCK is supplied, the current address
Data ADWRA0 to ADWRA3 are incremented by +1
And output it. FIG. 4 shows a specific example of the display RAM (38).
You. In FIG. 4, the same components as those in FIG.
The description is omitted. In FIG. 4, (60
−0) to (60-7) correspond to three AND gates and one
A switching circuit comprising an OR gate, and each switching circuit (60
−0) to one input of the right-hand AND gate of (60-7)
The terminal is connected to the signal SCL24B and the other input
The terminals are connected to D0 to D7 of the shift register (11).
One input terminal of the central AND gate is connected to the signal SCL1.
6B and the other input terminal is a shift register.
Connected to D8 to D15 of the
When one of the input terminals is connected to the signal SCL08B,
In both cases, the other input terminal is D16 of the shift register (11).
To D23. Each switching circuit (60-0) to (6
The output terminal of the OR gate of (0-7) is a buffer (29-).
0) to (29-7). In addition, display
Basic write and read operations of RAM (38)
The operation is the same as that of the display RAM (14). Hereinafter, based on the time chart of FIG.
The write operation of the AM (38) will be described. First,
-In the face circuit (1), the operation permission signal CE is
Becomes "H" and the 24-bit data DI, that is, D0 to D23
(Instruction codes D20 to D23, control bit D16,
Address data D8 to D13, character codes D0 to D
7) is synchronized with the clock signal CL and the shift register (1)
Transferred to 1). At this time, the instruction codes D20 to D23
Is for generating a command signal WDCK.
D16 is "H". Shift register (11)
When the shift operation ends, the signal SCL24B is generated
When the command signal WDNRCK is the same as the command signal WDCK
Generated from the instruction decoder (40)
You. At this point, the D-type flip-flop (46)
Command signal WDIMCK is generated because output is "L".
There is no. In FIG. 3, writing in the display RAM (38)
The address counter (58) for only the instruction signal WDNR
Since CK is supplied, the address data D8 to D13 are
The data is output as it is as CWRA0 to DCWRA5. Figure
At 4, the switching signal DCRWCT becomes "L" and
The value of the dress counter (58) DCWRA0 to DCWRA
5 is output via the switching circuits (26-0) to (26-5)
Is done. Thereafter, the clock signal DCLCK becomes “H”.
Address data DCWRA0 to DCWRA5
(27-0) to (27-5). Immediately
That is, the address data of all the addresses of the display RAM (38) is
Data write corresponding to data DCWRA0 to DCWRA5
The start address An is specified. Then, write permission signal
Signal DCWE becomes "H" with the generation of the command signal WDNRCK.
And the write start address of the display RAM (38) is
Switching circuits (60-0) to (60-7) and (29-0)
Through (29-7) to character codes D0 to D7
Written. In this write operation, the operation enable signal CE is
It is executed during the period of “L”. Thereafter, the operation permission signal CE changes to "H".
Then, a signal IMCK is generated and the D-type flip-flop is
The output of (46) becomes "H". On the other hand, 8-bit data
DI, that is, only character codes D16 to D23
Transferred to the shift register (11) in synchronization with the clock signal CL.
It is. At this time, the instruction code, control bits, address data
No need for data. The shift operation of the shift register (11)
When the processing is completed, the command signal W
DIMCK has the same timing as the signal LCK.
From the action decoder (40). The signal SC
L24B disappears with generation of signal SCL08B
You. In FIG. 3, for writing in the display RAM (38),
Address counter (58) receives the instruction signal WDIMCK.
Is supplied, the current address indicating the write start position
Data DCWRA0 to DCWRA5 by +1 increment
Output. In FIG. 4, the switching signal DCRWC
T becomes “L” and the value DC of the address counter (58)
WRA0 to DCWRA5 are switching circuits (26-0) to (2
6-5). Then, the clock signal D
CLCK becomes “H” and the address data DCWRA0
To DCWRA5 are latch circuits (27-0) to (27-
5) is latched. That is, writing in the display RAM (38)
Address (An + 1) next to the write start address is specified.
You. After that, the write enable signal DCWE changes to the command signal WD.
It becomes “H” with the occurrence of IMCK and the display RAM (3
8) The switching circuit (60-0) to the address (An + 1)
Via (60-7) and (29-0) to (29-7)
Character codes D16 to D23 are written. this
The write operation is executed during the period when the operation permission signal CE is “L”.
Is done. Then, the 8-bit data is stored in the shift register (11).
If the character code is transferred, the shift register (1
At the end of the shift operation of 1), the signal LCK is generated,
Command WDIMCK is issued at the same timing as signal LCK.
And the address of the display RAM (38) is incremented by +1.
And character codes D16 to D23 are written
It is. The write operation of the display RAM (38) ends.
When the operation permission signal CE changes to “H”,
16-bit data D8 to D23 (instruction codes D20 to D
23, control bit D16, character codes D8 to D1
5) is synchronized with the clock signal CL and the shift register (1)
Transferred to 1). At this time, the instruction codes D20 to D23
Is for generating a command signal WDCK.
D16 is "L". Shift register (11)
When the shift operation ends, the signal SCL16B is generated
When the command signal WDIMCK is the same as the command signal WDCK
Generated from the instruction decoder (40)
You. In FIG. 3, for writing in the display RAM (38),
Address counter (58) receives the instruction signal WDIMCK.
Is supplied, the current address data DCWRA0 to DCWRA0
DCWRA5 is incremented by +1 and output. FIG.
, The switching signal DCRWCT becomes “L” and the
Value of the counter 58 (DCWRA0 to DCWRA5)
Are output through the switching circuits (26-0) to (26-5).
It is. Thereafter, the clock signal DCLCK becomes “H”.
Address data DCWRA0 to DCWRA5
(27-0) to (27-5). Immediately
Next, the next address (An + m + 1) of the display RAM (38)
Is specified. After that, the write enable signal DCWE is commanded.
It becomes “H” with the generation of the command signal WDIMCK, and the display R
The switching circuit (60) is connected to the address (An + m) of the AM (38).
-0) to (60-7) and (29-0) to (29-7)
Character codes D8 to D15 are written via
You. This write operation is performed when the operation permission signal CE is at “L”.
Executed in between. Thereafter, the operation permission signal CE changes to "H".
Then, when the signal IMCK is generated, the D-type flip-flop
The output of (46) becomes “L” and the command signal WDIMCK
Does not occur, and the series of write operations ends. FIG. 6 shows a specific example of the accessory RAM (39).
Is shown. In FIG. 6, the same components as those in FIG.
And the description is omitted. In FIG.
(61-0) to (61-4) are three AND gates and
A switching circuit comprising one OR gate, wherein each switching circuit
One of the right-side AND gates of (61-0) to (61-4)
Is connected to the signal SCL24B and
Input terminals are connected to D0 to D4 of the shift register (11).
One input terminal of the central AND gate is connected to the signal SC.
L16B and the other input terminal is
Connected to D8-D12 of the register (11), left AND
One input terminal of the gate is connected to the signal SCL08B.
And the other input terminal is D of the shift register (11).
16 to D20. Each switching circuit (61-0)
The output terminal of the OR gate of (61-4) is a buffer (33
−0) to (33-4). In addition,
Basic writing operation and reading of accessory RAM (39)
The protrusion operation is the same as that of the display RAM (38). The following is an explanation based on the time chart of FIG.
The write operation of the sali RAM (39) will be described. First,
The operation permission signal CE in the interface circuit (1)
Becomes "H" and the 24-bit data DI, that is, D0 to D2
3 (instruction codes D20 to D23, control bit D16,
Dress data D8 to D11, accessory data D0 to D
4) is synchronized with the clock signal CL and the shift register (1)
Transferred to 1). At this time, the instruction codes D20 to D23
Is for generating a command signal WACK, and a control bit
D16 is "H". Shift register (11)
When the shift operation ends, the signal SCL24B is generated
When the command signal WANCK is the same as the command signal WACK
Generated from the instruction decoder (40)
You. At this point, the D-type flip-flop (53)
Command signal WAIMCK is generated because output is "L".
There is no. In FIG. 3, the accessory RAM (39)
The address counter (59) for writing the instruction signal WA
Since NRCK is supplied, the address data D8 to D11
Are output as ADWRA0 to ADWRA3 as they are.
You. In FIG. 6, the switching signal ADRWCT becomes "L".
And the value ADWRA0-ADWR of the address counter (59).
WRA3 is connected via switching circuits (31-0) to (31-3)
Output. Then, the clock signal ADLCK is
It becomes "H" and the address data ADWRA0-ADWR
A5 is latched by the latch circuits (32-0) to (32-3)
Is done. That is, all addresses of the accessory RAM (39)
Address data ADWRA0 to ADWRA3
The corresponding write start address An is specified. That
Thereafter, the write enable signal ADWE is changed to the command signal WANRCK.
Becomes “H” with the occurrence of the accessory RAM (39)
Switching circuits (61-0) to (6-0)
1-4) and (33-0) to (33-4).
Sesary data D0 to D4 are written. This writing
The operation is executed during a period when the operation permission signal CE is “L”. Thereafter, the operation permission signal CE changes to "H".
Then, a signal IMCK is generated and the D-type flip-flop is
The output of (53) becomes "H". On the other hand, 8-bit data
DI (actual transfer is 4-bit accessory data D16
To D20) are shifted in synchronization with the clock signal CL.
(11). At this time, the instruction code and control
No data or address data is required. Shift register (1
When the shift operation of 1) is completed, the signal SCL08B is generated.
The instruction signal WAIMCK is the same as the signal LCK
Generated from the instruction decoder (40) at the moment
I do. Note that the signal SCL24B is generated from the signal SCL08B.
Disappears with In FIG. 3, an accessory RAM
The write address counter (59) in (39)
Since the command signal WAIMCK is supplied, the write start position
Address data ADWRA0-ADWR representing the location
A3 is incremented by +1 and output. Figure 6
As a result, the switching signal ADRWCT becomes “L” and the address
Counter (59) value ADWRA0-ADWRA3 is switched
It is output via circuits (31-0) to (31-3).
After that, the clock signal ADLCK becomes “H” and the
Less data ADWRA0-ADWRA3 are latch circuits
Latched at (32-0) to (32-3). That is,
Next to the write start address of the accessory RAM (39)
The dress (An + 1) is designated. After that, write permission
The enable signal ADWE is generated with the generation of the command signal WAIMCK.
It becomes "H" and the address of the accessory RAM (39)
Switching circuits (61-0) to (61-4) and (An + 1)
And accessory data via (33-0) to (33-4)
Data D16 to D20 are written. This write operation
It is executed during the period when the operation permission signal CE is “L”. That
Then, the 8-bit accessory data is stored in the shift register (11).
When the data is transferred, the shift operation of the shift register (11) is performed.
At the end of the operation, a signal LCK is generated and the command signal WAIM
CK is generated at the same timing as the signal LCK, and the accessor
The address of the re-RAM (39) is incremented by +1.
Thus, accessory data D16 to D20 are written. Write operation of accessory RAM (39)
Is terminated, the operation permission signal CE changes to “H”.
Then, the 16-bit data D8 to D23 (the instruction code D2
0 to D23, control bit D16, accessory data D8
To D12) are shifted in synchronization with the clock signal CL.
(11). At this time, the instruction codes D20 to
D23 is for generating a command signal WACK.
The control bit D16 is "L". Shift register (1
When the shift operation of 1) is completed, the signal SCL16B is generated.
The command signal WAIMCK is the same as the command signal WACK
Instruction decoder (40) at the same timing
Occurs. In FIG. 3, the accessory RAM (39)
Address counter (59) for writing
Since WAIMCK is supplied, the current address data A
DWRA0 to ADWRA3 are incremented by +1 and output.
Power. In FIG. 6, the switching signal ADRWCT is "L".
And the value ADWRA0 of the address counter (59)
ADWRA3 controls the switching circuits (31-0) to (31-3).
Output via Then, the clock signal ADLCK is
It becomes "H" and the address data ADWRA0-ADWR
A3 is latched by the latch circuits (32-0) to (32-3)
Is done. That is, the next address of the accessory RAM (39)
(An + m + 1) is specified. After that, write permission
The signal ADWE is generated with the generation of the command signal WAIMCK.
It becomes "H" and the address of the accessory RAM (39)
Switching circuits (61-0) to (61-4) and (An + m)
And character code via (33-0) to (33-4)
The data D8 to D12 are written. This write operation is
It is executed during the period when the operation permission signal CE is “L”. Thereafter, the operation permission signal CE changes to "H".
Then, when the signal IMCK is generated, the D-type flip-flop
The output of (53) becomes “L” and the command signal WAIMCK
Does not occur, and the series of write operations ends. As described above, according to the embodiment of the present invention,
All of display RAM (38) and accessory RAM (39)
Rewrite data in address area or partial address area
The write start position for address information.
Transfer only address data to the shift register (11)
The shift register (1
1) The number of serial data transfer bits to 1) can be reduced,
The burden of software processing on the external device can be reduced. [0042] According to the present invention, the entire memory of the display memory means is provided.
Rewrite data in address area or partial address area
In the case, the address information indicates the write start position.
External device because only address data needs to be supplied
The number of bits of data supplied from the
Can reduce the burden of software processing on external devices
It works. In particular, the present invention is applicable to a device having a high display speed.
It is effective.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a display drive circuit of the present invention. FIG. 2 is a diagram illustrating details of an instruction decoder of FIG. 1; FIG. 3 is a diagram showing details of an address counter of FIG. 1; FIG. 4 is a diagram showing details of a display RAM of FIG. 1; FIG. 5 is a time chart showing a write operation of the display RAM of FIG. 1; FIG. 6 is a diagram showing details of an accessory RAM of FIG. 1; FIG. 7 is a time chart showing a write operation of the accessory RAM of FIG. 1; FIG. 8 is a block diagram showing a conventional display drive circuit. FIG. 9 is a diagram showing details of the interface circuit of FIGS. 1 and 8; FIG. 10 is a diagram illustrating details of an instruction decoder of FIG. 8; FIG. 11 is a diagram showing details of a display RAM of FIG. 8; FIG. 12 is a drawing showing details of an accessory RAM of FIG. 8; [Description of Signs] (1) Interface circuit (11) Shift register (38) Display RAM (39) Accessory RAM (40) Instruction decoder

Continuation of front page (56) References JP-A-3-273773 (JP, A) JP-A-5-313652 (JP, A) JP-A-7-152339 (JP, A) JP-A 8-255107 (JP) (A) JP-A-1-266593 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G09G 3/20 631 G09G 3/20 660 G09G 5/00 550

Claims (1)

(57) [Claim 1] A circuit for displaying a predetermined character on a display panel, a display memory means for storing display data representing the character, and a readout from the display memory means. A display comprising: panel driving means for displaying a character corresponding to the display data on the display panel based on the displayed display data; and register means for holding write address data and display data of the display memory means. In the drive circuit, a counter for counting address data of the display memory means.
And the register means includes the address data for writing.
Instruction decoding means for decoding the instruction code held together;
The counting means, wherein the instruction decoding means converts the instruction code
When the first instruction signal is output after decoding,
The write the stage is holding with the instruction code
Address data for the display memory means as initial values.
After that, the instruction decoding means needs the instruction code.
Each time an unnecessary second command signal is output,
The address data for
A display drive circuit for supplying to a display memory means .