JPS6032091A - Hidden surface processing system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention defines a plurality of windows, assigns a job to each window, and displays data necessary for executing the job in the corresponding window. The present invention relates to a hidden surface processing method that can be performed at high speed using a processing mechanism dedicated to hidden surface processing χ in an information processing system having a multi-window function.

[Conventional technology and problems]

Define multiple windows on the display screen.

It has been conventional practice to display data output from a job corresponding to each window. When windows overlap on the physical display screen, data that should be displayed on the window that is defined as being on the top will be prioritized for the overlapping part, and data that should be displayed on the window that is defined as being on the bottom will not be displayed. must be done.

This is called IL: Hidden surface processing in multi-window.

Hidden surface processing in conventional i-multi-windows has been mainly performed by software. With this conventional method, when a large number of windows exist on the physical display screen and their overlapping is complicated, the amount of calculation required to configure each window increases, resulting in a decrease in display speed and control software. There are drawbacks such as double tracks. [Object of the Invention] The present invention is based on the above consideration.

In an information processing system with a multi-window function, the display area t on the actual physical display of each window
j5K can be calculated without using software etc.
The purpose of this invention is to provide a hidden surface processing method.

[Structure of the invention]

Therefore, the hidden surface processing method of the present invention includes a 1wA surface buffer, each of which has a one-to-one relationship with each of a plurality of windows.
If the same address information as the address information supplied to the above screen buffer is supplied along with the correspondence of , and the value of the address information specifies a point within the window, multiple pieces of mask data of a predetermined value are output. masking means, each having a one-to-l pair E with each of the plurality of masking means.
It has a plurality of input terminals, each having a one-to-one correspondence with each of the plurality of one-scroll means, and has a plurality of output terminals, each of which has a one-to-one correspondence with each of the plurality of one-scroll means, and one-scroll data of a predetermined value is inputted to the input terminal. When all the mask data with higher priority have other predetermined values, the mask data of the predetermined value is output from the corresponding output terminal, and in other cases, the mask data of the other predetermined value is output. a logic circuit for hidden surface erasing configured to output mask data from a corresponding output terminal; A selector having an input terminal 7 and outputting mask data supplied to one input terminal according to a control signal, and a signal line supplying the mask data output from the selector to the screen buffer, and further comprising: The screen buffer is inserted into the storage location specified by the read data address information if the supplied mask data has a predetermined value of 7, and if the mask data has another predetermined value. It is characterized in that it is configured so that no write data is written.

[Embodiments of the invention] The present invention will be explained below with reference to drawing t#.

FIG. 1 is a block diagram of one embodiment of the present invention, FIG. 2 is a block diagram of one embodiment of the logic circuit for hidden surface erasing of the present invention, and FIG. 3 is for explaining the operation of the embodiment of FIG. 1. diagram,
FIG. 4 is a block diagram of another embodiment of the invention.

In the iris 1 diagram, %Mt or M is the mask area.

LC represents a hidden surface erasing logic circuit, S represents a selector, and BF represents a screen style buffer t.

The screen data stored in the screen buffer BF is.

The character code is in the form of t. For the write data sent from the host group computer (not shown), the write permission/inhibition signal output from the selector S is logic "1".
It is written to the one-screen buffer BF on the condition that . Mask area Mi (where i is 1, 2...
. . n) corresponds to the Mi-th window, and each has a plurality of memory locations in one-to-one correspondence with a plurality of character code memory locations in the screen buffer BF, and the mask area Mi One bit of data is stored in each storage location. In the mask area Mi, all the bits belonging to the memory area corresponding to the i-th index are set to logic "1". When writing one write data to the screen buffer BF, the same address information as the address information supplied to the screen buffer BF is supplied to the mask areas M1 to %n.
Bit data corresponding to address information is read from Mn. The bit data read from one frame area M1 to M3 is supplied to the hidden surface erasing logic circuit LC&C.

FIG. 2 shows 11j! of the hidden surface erasing logic circuit LC. It is a block diagram of an example. In FIG. 2, T through Tn are input terminals, Ill and Ill are output terminals, 0. or 0
The circuit is an OR circuit, and ■ and ln are inverters.

At to As indicate AND circuits t, respectively. Data read from the i-space area Mi is input to the input terminal Tittc, and data output from the output terminal Tif is supplied to the i-th input terminal of the selector S. The bit data of logic "1" inputted to the input terminal TiK is output only when the one-bit data inputted to the input terminals TI to T i -1 are all logic "0". In addition, in FIG. 2, the priority is Ml
-M snow -Ms...Mn is assumed to be lower in the order.

Output terminals T11 to T of the hidden surface erasing logic circuit LC, /
The data output from the selector S is input to the selector S. The selector S selects and outputs the data input to the i-th input terminal when the mask number applied to the control input terminal is equal to the i-th number χ.

FIG. 3 is a diagram showing the operation of the embodiment of FIG. 1.

In FIG. 3, MD is a mask data area consisting of logic ``1'' bits corresponding to window W, and MD is a mask data area % MD1' consisting of logic ``1'' bits corresponding to window Wl. is the mask data area MD,
Y Modified modified mask data area.

MDI' indicates mask data area MDI ``t'' modified mask data area, t, respectively. Modified mask data area MD, , '1f, , 1, in, de w1
Mask data portion t corresponding to the overlapping portion of and W
This is what was removed from the mask data area MD. The mask number supplied to the control input terminal of the selector S is 11# when writing 1 data to the window W□ of the 1-screen buffer BF, and 2'' when writing window 2 data of the 1-screen buffer BP. In the example shown,
Write data D for window w weight is rABcD
IFGHJ 1h9. flin)'W.

The write data Da for the 1i write data D is rIJKLMNOP.

is written to the screen buffer BF based on the contents of the modified mask data area MD,', so a part of it is not written to the screen buffer BF.

FIG. 4 is a block diagram of another embodiment of the invention. #L
In FIG. 4, MO, to M(, & indicate mask calculation logic circuits. Note that the same reference numerals as in FIG. 1 indicate the same components. In the case of the embodiment of FIG.
The size of the address area of the screen buffer BF must be the same as the size of the address area of the screen buffer BF. The storage capacity increases, making it difficult to implement. The embodiment shown in FIG. 4 realizes an isometric mask by logical operations and is intended to reduce the storage capacity for the mask. The mask specifies whether window data can be written to the storage location of the screen buffer BF. Since the storage location of the screen buffer BF has a one-to-one correspondence with the address, an address value consisting of The mask is a logic function that determines whether or not data can be written when the data is written. In order to express the shape of an arbitrary window, it is best to express it by a set of bits corresponding to the storage location of the screen buffer, as shown in the example in Figure 1, but the shape of the window is usually rectangular. Since there are many cases, this logic function can also be realized by a wired logic circuit if the window shape is limited to a rectangle. The mask calculation logic circuit MC1 (i=1.2... path) in Figure 4 has a rectangular window, and if the input address information specifies a point within the window, the logic 11 bit is set.・Output data.

A window start address, width, etc. are given to the mask calculation logic circuit MCi in order to define the window.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, when realizing a system with a multi-window function, there is no need to calculate the display area of each window on the actual screen using software.

You can expect faster processing and simpler multi-window control software.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, FIG. 2 is a block diagram of one embodiment of the hidden surface erasing logic circuit of the present invention, and FIG. 3 is for explaining the operation of the embodiment of FIG. 1. diagram,
FIG. 4 is a professional diagram of another embodiment of the present invention.@M to Mn...mask area, LC...logic circuit for hidden surface erasing, S...selector, BF...screen ~Buffer, MC, or MC le...mask calculation logic circuit. Patent author: Fujitsu Limited Representative Patent Attorney Yotsube Kyotani

Claims (1)

[Claims] A screen buffer, each having a one-to-one correspondence with each of a plurality of windows, is supplied with address information identical to that supplied to the screen buffer, and the value of the address information specifies a point within the window. In the case of a plurality of masking means, each masking means outputs one screen data of a predetermined value, and a plurality of input terminals Y have a one-to-one correspondence with each of the plurality of masking means. A plurality of output terminals are provided in a one-to-one correspondence with each of the masking means, and when mask data of a predetermined value is input to the input terminal, all mask data with a higher priority than that are input to other predetermined values. Hidden surface erasure configured to output mask data of the predetermined value from the corresponding output terminal only when the data has the predetermined value, and to output mask e data of another predetermined value from the corresponding output terminal in other cases. a mask logic circuit having a plurality of input terminals, each of which is connected in a one-to-one correspondence to each of the plurality of output terminals of the hidden surface erasing logic circuit; The screen buffer includes a selector that outputs data, and a signal line that supplies mask data output from the selector to the screen buffer, and the screen buffer further includes:
If the supplied mask data has a predetermined value, it is written to the storage location specified by the write data sound address information, and if the mask data has another predetermined value, the write data is not written. A hidden surface processing method characterized by being configured as follows.