JP3387409B2 - Digital demodulation circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital demodulation circuit used in a communication system such as a satellite communication system. 2. Description of the Related Art In order to cope with diversified forms of communication information such as information data, voice, video, etc., technical development of digital communication systems has been actively carried out. Improvement of communication quality such as error reduction is an important theme. This bit error reduction is
The quality of the transmitted wave on the transmitting side, attenuation and noise in the transmission path,
This is achieved by improving the accuracy of digital demodulation on the receiving side. Digital demodulation on the receiving side is performed by detecting the phase and amplitude of the detected received signal and converting it into a digital quantity. FIG. 8A is a signal space diagram showing four phase states in, for example, a four-phase phase modulation (QPSK) system. The received signal detected due to the quality of the transmission wave on the transmission side, the application of noise on the transmission path, etc.
The signal has a spread in phase and amplitude as shown in FIG. When the receiver is manufactured, the reference level for processing the received signal is adjusted in the digital demodulation circuit, but the reference level is offset due to a temperature change or an aging change. As this offset increases, FIG.
As shown in (c), the quadrant moves from the original quadrant on the signal space diagram to a quadrant having a different state, and the result of digital demodulation becomes a bit error. FIG. 9 is a block diagram of a conventional digital demodulation circuit for reducing the above-mentioned offset. 1 is an input terminal of a received signal after detection, 2 is an analog low-pass filter (analog LPF) for removing high frequency noise of the received signal, 3
Is an AD converter for digitally converting the received signal passed through the analog LPF 2. 7 is DC from the AD converter output
A digital low-pass filter (digital LPF) 8 for detecting components, an adder 8 for subtracting a reference level from the output of the digital LPF 7, an input terminal 8 for the reference level, and an offset 10 from the output of the AD converter 3 An adder for subtraction, 11 is a demodulator, and 12 is an output terminal of a demodulated signal. Next, the operation of the conventional digital demodulation circuit will be described. The received signal after detection is converted to an analog LP in order to avoid the influence of aliasing generated in the AD converter 3.
After removing high frequency components in F2, the AD converter 3
Is converted into a digital signal. Digital LPF
7, the DC component of the output signal of the AD converter 3 is detected,
By subtracting the reference level input to the input terminal 9 from the DC component in the adder 8, the offset of the reference level of the received signal is estimated. The adder 10 subtracts the estimated offset from the output signal of the AD converter 3, and
The offset included in the received signal is removed. [0005] The detected signal after detection is Rm (t), and the offset is
Assuming Ro, the received signal R (t) after AD conversion can be expressed by the following equation. R (t) = Ro + Rm (t) If the data pattern of the detected received signal Rm (t) has strong randomness, the low-frequency component of Rm (t) can be sufficiently reduced. Since it is small, the received signal R (t) after AD conversion
Is passed through the digital LPF 7 to detect Ro. [0008] In such a conventional digital demodulation circuit, if a data pattern such that Rm (t) is constant exists in the received signal after detection, the output of the digital LPF 7 is output. There is a problem that the DC component of Rm (t) remains and the offset Ro cannot be estimated. For example, FIG. 10 is a schematic diagram showing offset estimation in the case of two-phase modulation (BPSK). If the received signal fluctuates as shown in FIG. 10A, the output of the digital LPF 7 becomes only Ro and the offset can be estimated.
As shown in (b), when there is a highly biased reception signal such that the data pattern is constant for a long time, the digital L
The output of the PF 7 is the sum of Ro and Rm (t), and the offset Ro is erroneously estimated. When a data pattern having such a large bias exists in a received signal, if the length of the signal is short, there is a method of making the band of the digital LPF 7 narrow so as not to be easily affected.
7, there is a limit in narrowing the bandwidth. Also, even if the digital LPF 7 is narrowed, if there is a data pattern having a large bias periodically in the received signal,
The effects cannot be avoided. SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems. Even when a received signal has a highly biased data pattern, it is not affected by the temperature change or the temperature change after circuit manufacture. It is an object of the present invention to obtain a digital demodulation circuit that adaptively estimates and corrects an offset due to aging or the like. A digital demodulation circuit according to claim 1 is a digital demodulation circuit for performing intermittent reception.
, Which converts the detected received signal into a digital signal.
Converting means for removing high frequency components of the output of the AD converting means.
Offset extracting means for extracting the offset
The offset extracted by the offset extracting means is represented by A
Offset extracting means for removing from the output of the D converting means;
The presence of the received signal is detected and if the received signal is not present
The offset is extracted by the offset extraction means when
And a carrier detector for generating a control signal . DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 The digital demodulation circuit according to the first embodiment will be described with reference to FIG. FIG.
1 is a configuration diagram of a digital demodulation circuit according to Embodiment 1 of the present invention. Reference numeral 1 denotes an input terminal of a received signal after detection, 2 denotes an analog LPF that removes high-frequency noise of the received signal, and 3 denotes an AD converter that digitally converts a received signal that has passed through the analog LPF 2. Reference numeral 4 denotes an offset extracting unit that removes high-frequency components of the output of the AD converter 3 and partially extracts an offset. Reference numeral 5 denotes a switch for partially extracting the output of the AD converter 3, and reference numeral 6 denotes a control signal input terminal to the switch 5. 7 is a digital LP for detecting a DC component
F and 8 are adders for subtracting the reference level from the output of the digital LPF 7, and 9 is an input terminal of the reference level to the adder 8. Reference numeral 10 denotes an adder for subtracting the offset extracted by the offset extracting unit 4 from the output of the AD converter 3 to remove the offset, reference numeral 11 denotes a demodulator, and reference numeral 12 denotes an output terminal of a demodulated signal. The detected signal input to the input terminal 1 is passed through an analog LPF 2 so that aliasing does not occur in the AD converter 3, and is converted into a digital signal by the AD converter 3. The switch 5 in the offset extractor 4 is turned on / off by a control signal from the input terminal 6 and outputs a received signal of a data pattern having a small bias suitable for offset extraction to the digital LPF 7. When the switch 5 is on, the digital LPF 7 removes high-frequency components of the input signal and outputs a DC component. When the switch 5 is off, the digital LPF 7 holds and outputs the output value when the switch 5 was on. An adder 8 subtracts the reference level of the received signal from the DC component output by the digital LPF 7 to extract an offset. The adder 10 subtracts the offset extracted by the offset extracting unit 4 from the output of the AD converter 3 to remove the offset, and the received signal is corrected. Since the input signal to the demodulator 11 is a received signal whose offset has been corrected by the adder 10, the demodulated signal obtained at the output terminal 12 includes a bit error due to the offset as shown in FIG. Is less likely to occur. As described above, the method of holding the DC component partially extracted by turning on / off the switch 5 and using it to correct the received signal when the switch 5 is turned off is based on the fact that the offset of the received signal is affected by a temperature change, an aging change, or the like. It is suitable when it is caused by a long cycle factor. When the reference level for processing the received signal is 0, the output of the digital LPF 7 is the offset itself, so that the adder 8 and the input terminal 9 for the reference level are unnecessary, and the output of the digital LPF 7 is added to the adder. 10 can be connected. Embodiment 2 FIG. In the first embodiment, the switch 5 is connected between the AD converter 3 and the digital LPF 7 in the offset extracting unit 4 to partially extract the offset. However, the offset is partially extracted. The timing may be set by detecting a known pattern in the frame format of the received signal using a pattern detector as shown in FIG. In FIG.
Reference numeral 13 denotes a pattern detector that detects a specific known pattern from the received signal demodulated by the demodulator 11 and generates an offset extraction timing in the offset extraction unit 4. FIG. 3 is a schematic diagram showing an example of the frame format of the received signal and the operation of the pattern detector 13.
At the head of the frame format of the received signal, there is a CW pattern (carrier pattern) added for frequency synchronization, and this CW pattern is followed by a known pattern and a transmission data sequence. When detecting the known pattern, the pattern detector identifies the received frame from the position of the known pattern, and generates a control signal for turning on the switch 5 only during the period of receiving the transmission data sequence. If the transmission data sequence is subjected to scramble processing by taking an exclusive OR with a random data component, for example, the data pattern becomes highly random and has a small bias regardless of the content of the transmission data. It is suitable as a received signal for estimating the offset extracted by the unit 7. For example, in the case of BPSK, the CW pattern is a pattern in which only 0s or only 1s continuously occur. Since the data pattern has a large bias, it is not suitable for a received signal used for offset estimation. The known pattern may have a large or small data pattern deviation. However, if a known pattern with a small deviation is adopted, a control signal for turning on the switch 5 only during the period of receiving the known pattern is detected. The offset may be extracted by the generator 13. In FIG. 2, the pattern detector 13 is configured to detect a known pattern from the output of the demodulator 11, but may be configured to detect a known pattern from the input to the demodulator 11.
Note that a UW (unique word) pattern used in many communication systems may be used as the known pattern. In this case, the pattern detector 13 is composed of a UW detector provided in the communication system and a monitor circuit that monitors a period during which the UW pattern is detected and generates an on / off signal to the switch 5 so that the UW detection is performed. The on / off of the switch 5 can be controlled without adding a new pattern detector 13 to an existing digital demodulation circuit having a detector. Embodiment 3 In the second embodiment, a known pattern is detected by the pattern detector 13 from the output of the demodulator 10 to identify a received frame, and in a portion where the data pattern in the received signal has a small bias, the switch 5 is turned on to extract the offset. However, in the case of receiving a received wave intermittently in a burst, a configuration may be adopted in which a carrier signal is detected, a received frame is identified, and an offset is extracted. In FIG. 4, reference numeral 14 denotes a carrier detector that detects a carrier signal of a received signal from the output of the AD converter 3 and outputs an on / off control signal for extracting an offset to the switch 5. When a received wave arrives intermittently and is burst received, the arrival of the received wave is detected by the carrier detector 14 based on characteristics such as received signal strength. FIG. 5 is a schematic diagram showing an example of the frame format of the received signal and the operation of the carrier detector 14. At the beginning of the received frame, there is a CW pattern added for carrier detection and frequency synchronization.
When a pattern is detected, a control signal for turning on the switch 5 and turning off the switch 5 at the end of the transmission data sequence is generated after waiting for a necessary time until the transmission data sequence is received. As described in the second embodiment, for example, in the case of BPSK, the CW pattern is a pattern in which only 0 continuously or only 1 continuously follows.
Since the data pattern has a large bias, it is not suitable as a received signal used for offset estimation. If the transmission data sequence is scrambled by, for example, performing an exclusive OR operation with a random data component, the data pattern has high randomness and a small bias regardless of the content of the transmission data. 7 is suitable as a received signal for estimating the offset to be extracted. Embodiment 4 In the third embodiment, when the received wave intermittently arrives, the carrier detector 1
4, the carrier signal of the received signal is detected, and the offset is extracted in the transmission data sequence.
As shown in FIG. 6, offset extraction may be performed during a period in which a received wave does not arrive. During a period in which no received wave arrives, only noise is received and the randomness is high, so that the output of the AD converter 3 is in a state where the bias of the data pattern is small. In order to extract the offset during the period when the received wave has not arrived, the carrier detector 1
The switch 4 turns off the switch 5 when detecting the CW pattern, and generates a control signal for turning on the switch 5 at the end of the transmission data sequence. Embodiment 5 In the first embodiment, the DC component is detected by the digital LPF 7 and then input to the adder 8, but as shown in FIG.
A configuration may be adopted in which a limiter is provided so that the output of the PF 7 is equal to or less than a certain value. In FIG. 7, reference numeral 15 denotes a limiter for monitoring the output value of the digital LPF 7 and feeding back the output value to the digital LPF 7 so that the output value becomes equal to or less than a predetermined value. This limiter 15 is a digital LPF.
7 prevents the data from overflowing due to erroneous detection such that the DC component output by the output signal 7 becomes extremely large, and stabilizes the operation of the circuit. When the digital LPF 7 internally performs an integration process such as an IIR filter (infinite impulse response filter), the limiter 15 limits a DC component at the time of erroneous detection to prevent an abnormal value from remaining in the integration process. Thus, the output of the digital LPF 7 is quickly returned to a normal value. According to the first aspect of the present invention, intermittent reception is performed.
Digital demodulation circuit that performs
The presence of the received signal is detected from the
Signal based on the DC component of the noise signal
Signal with large bias
The offset and remove it from the received signal
Can be [0029]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a configuration diagram of a digital demodulation circuit according to Embodiment 1 of the present invention. FIG. 2 is a configuration diagram of a digital demodulation circuit according to Embodiment 2 of the present invention. FIG. 3 is a schematic diagram showing an example of a received signal frame format and an operation of a pattern detector according to Embodiment 2 of the present invention. FIG. 4 is a configuration diagram of a digital demodulation circuit according to Embodiment 3 of the present invention. FIG. 5 is a schematic diagram showing an example of a received signal frame format and an operation of a carrier detector according to Embodiment 3 of the present invention. FIG. 6 is a schematic diagram showing an example of a received signal frame format and an operation of a carrier detector according to Embodiment 4 of the present invention. FIG. 7 is a configuration diagram of a digital demodulation circuit according to Embodiment 5 of the present invention. FIG. 8 is a signal space diagram showing the spread and offset of four phase states in the four-phase modulation scheme. FIG. 9 is a configuration diagram of a conventional digital demodulation circuit. FIG. 10 is a schematic diagram illustrating offset estimation according to a conventional digital demodulation circuit. [Description of Signs] 3 AD converter 4 Offset extraction unit 5 Switch 7 Digital LPF 8, 10 Adder 13 Pattern detector 14 Carrier detector 15 Limiter

Claims (1)

(57) [Claims 1] Digital demodulation circuit for intermittent reception
, Which converts the detected received signal into a digital signal.
Converting means for removing high frequency components of the output of the AD converting means.
Offset extracting means for extracting the offset
The offset extracted by the offset extracting means is represented by A
Offset extracting means for removing from the output of the D converting means;
The presence of the received signal is detected and if the received signal is not present
The offset is extracted by the offset extraction means when
And a carrier detector for generating a control signal.
Characteristic digital demodulation circuit.