JP3381690B2 - Field effect transistor and method of manufacturing the same - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor having a gate electrode having a structure in which silicon and copper are laminated and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, further miniaturization of LSI has been studied for higher performance and higher integration. Under such circumstances, along with the miniaturization, it is indispensable to reduce the resistance of the gate electrode of the field effect transistor for high performance. For this reason, the use of a two-layer structure of metal and polysilicon for the gate electrode material has been studied. Therefore, due to its low electrical resistance and its superior workability and chemical stability over gold and silver, it is possible to avoid
It has been proposed to form the gate electrode with a layered structure.

The conventional field effect transistor described above will be described. As shown in FIG. 14, a lower gate electrode 1403 made of polysilicon is first provided on a silicon substrate 1401 with a gate insulating film 1402 interposed. Further, an upper gate electrode 1405 made of copper is provided on the lower gate electrode 1403 via a barrier film 1404 made of titanium nitride or the like. Further, a barrier film 1406 made of titanium nitride or the like is provided on the upper gate electrode 1405. Then, the lower gate electrode 14
03 and the upper gate electrode 1405 form the gate electrode of the transistor.

A sidewall 1407 made of silicon oxide is formed so as to cover the side surface of the gate electrode. Further, a low-concentration impurity region 1408 is formed in the silicon substrate 1401 below the sidewall 1407. A source 1409 and a drain 1410 are formed on the silicon substrate 1401 so as to sandwich the low concentration impurity region 1408. Then, the low-concentration impurity region 1408, the source 1409 and the drain 1410, the gate insulating film 1402, and the gate electrode composed of the lower gate electrode 1403 and the upper gate electrode 1405 constitute a field effect transistor having an LDD structure. With this LDD structure, the single channel effect can be suppressed.

The above transistor is covered with an interlayer insulating film 1411 made of silicon oxide, and a gate electrode wiring 1412 and a source electrode wiring 1413 made of aluminum are formed on the interlayer insulating film 1411. The gate electrode wiring 1412 is connected to the upper gate electrode 1405 via the barrier film 1406 by the plug 1414 in the through hole formed in the interlayer insulating film 1411. The plug 1414 is made of tungsten, and a barrier film 1414a made of titanium nitride or the like is formed on the side surface and the bottom surface of the plug 1414.

Further, the source electrode wiring 1413 is connected to the source 1409 by the plug 1415 in the contact hole formed in the interlayer insulating film 1411. The plug 1415 is also made of tungsten, and a barrier film 1415a made of titanium nitride or the like is formed on the side surface and the bottom surface. Further, barrier films 1412a and 1413a made of titanium nitride or the like are formed on the gate electrode wiring 1412 and the source electrode wiring 1413. In addition, the above-mentioned gate electrode wiring 1412
A protective insulating film 1416 is formed over the interlayer insulating film 1411 so as to cover wirings such as the source electrode wiring 1413 and the like.

[0007]

As described above, in order to further reduce the resistance, when the gate electrode is composed of a two-layer structure of polysilicon and copper, the upper gate electrode 1405 made of copper has a lower surface and an upper surface. And barrier film 1404,1
406 is provided to suppress the diffusion of copper into the lower layer polysilicon and the upper layer wiring metal. However,
Since copper also diffuses in the silicon oxide film, it diffuses in the sidewall 1407 and the interlayer insulating film 1411 which are silicon oxides, as shown by the arrow line in FIG.
When copper diffuses toward the silicon substrate 1401,
This causes problems such as generation of junction leakage current, reduction of on-current of the transistor, and fluctuation of threshold value. Further, if copper diffuses in the direction of the upper wiring layer, it causes a problem of leak current between wirings.

The present invention has been made in order to solve the above problems, so that copper can be used as the material of the gate electrode of a field effect transistor without deteriorating the characteristics of the transistor. The purpose is to do.

[0009]

A field effect transistor according to claim 1 of the present invention comprises a lower gate electrode made of silicon formed on a silicon substrate via a gate insulating film, and formed on the lower gate electrode. An upper gate electrode made of copper, and conductive to inject a current sufficient to drive a channel portion into the lower gate electrode to prevent diffusion of copper formed to cover the lower surface of the upper gate electrode.
Of the barrier film, a second barrier film which is formed so as to contact the lower end of the first barrier film and covers both side surfaces of the upper gate electrode, and which prevents diffusion of copper, and the second barrier film. A third barrier film formed to cover the upper surface of the upper gate electrode to prevent the diffusion of copper is formed so as to contact the end portions, and a source / drain formed on the silicon substrate so as to sandwich the region under the lower gate electrode. comprising, a first barrier film is composed of a layer lowest layer is made of a compound of a metal silicide layer or a refractory metal metal, silicon and nitrogen, with the layer or refractory metal metal, silicon and nitrogen of the metal silicide layer arrangement of a refractory metal nitride onto a compound layer
The uppermost layer is a multi-layer film composed of a refractory metal. According to the present invention, the upper gate electrode made of copper is configured to be in contact with the other portion of the field effect transistor via the first, second, and first barrier films. A field effect transistor according to claim 2 of the present invention is a lower gate electrode made of silicon formed on a silicon substrate via a gate insulating film, and an upper gate made of copper formed on the lower gate electrode. A first gate electrode and a lower gate electrode, which has conductivity to inject a sufficient current to drive a channel portion and prevents diffusion of copper formed to cover a lower surface of the upper gate electrode;
Of the barrier film, a second barrier film which is formed so as to contact the lower end of the first barrier film and covers both side surfaces of the upper gate electrode, and which prevents diffusion of copper, and the second barrier film. A third barrier film formed to cover the upper surface of the upper gate electrode to prevent the diffusion of copper is formed so as to contact the end portions, and a source / drain formed on the silicon substrate so as to sandwich the region under the lower gate electrode. The first barrier film comprises a metal silicide layer or a layer composed of a compound of a refractory metal metal and silicon and nitrogen as a lowermost layer. The metal silicide layer or the refractory metal metal, silicon and nitrogen is used as the lowermost layer. A layer of a refractory metal nitride is arranged on a layer made of a compound, and the uppermost layer is a multilayer film made of a refractory metal,
In addition, a side wall formed on the side surfaces of the lower gate electrode and the upper gate electrode is provided, and the second barrier film is constituted by a part of this side wall.

A field effect transistor according to a third aspect of the present invention comprises a lower gate electrode made of silicon formed on a silicon substrate via a gate insulating film, and a copper formed on the lower gate electrode. And a first barrier film which has conductivity so as to inject a current sufficient to drive the channel portion into the lower gate electrode and which is formed to cover the lower surface of the upper gate electrode to prevent diffusion of copper. , A second barrier film formed to cover both side surfaces of the upper gate electrode to prevent diffusion of copper, the lower end of which contacts the first barrier film, and the second barrier film whose end contacts the second barrier film. And a third barrier film formed of an insulating material that covers the upper surface of the upper gate electrode and blocks diffusion of copper,
A source / drain formed on a silicon substrate so as to sandwich the region under the lower gate electrode, and the first barrier film is a layer in which the lowermost layer is a metal silicide layer or a compound of a refractory metal metal and silicon and nitrogen. A multi-layered structure in which a refractory metal nitride layer is disposed on the metal silicide layer or the refractory metal metal / silicon / nitrogen compound layer, and the uppermost layer is composed of the refractory metal. It is made to be a membrane. The field effect transistor according to claim 4 of the present invention is a lower gate electrode made of silicon formed on a silicon substrate through a gate insulating film, and an upper gate made of copper formed on the lower gate electrode. An electrode, a first barrier film having a conductivity capable of injecting a current sufficient to drive a channel portion into the lower gate electrode, and formed to cover the lower surface of the upper gate electrode to prevent the diffusion of copper; A second barrier film formed to cover both side surfaces of the upper gate electrode so as to prevent diffusion of copper, the lower end of which contacts the first barrier film and an end portion of the second barrier film which contacts the second barrier film. A third barrier film formed of an insulating material which covers the upper surface of the gate electrode and which blocks diffusion of copper; and a source / drain formed on the silicon substrate so as to sandwich the region under the lower gate electrode. In the first barrier film, the lowermost layer is composed of a metal silicide layer or a layer formed of a compound of a refractory metal metal and silicon and nitrogen. The metal silicide layer or the refractory metal metal, silicon and nitrogen is used as the lowermost layer. A refractory metal nitride layer is disposed on the compound layer , and the uppermost layer is a multilayer film composed of refractory metal. The insulating film is formed on the insulating layer, and the third barrier film is formed so as to extend on the insulating layer.

A field effect transistor according to a fifth aspect of the present invention comprises a lower gate electrode made of silicon formed on a silicon substrate via a gate insulating film, and a copper formed on the lower gate electrode. And a first barrier film which has conductivity so as to inject a current sufficient to drive the channel portion into the lower gate electrode and which is formed to cover the lower surface of the upper gate electrode to prevent diffusion of copper. , A second barrier film formed to cover both side surfaces of the upper gate electrode to prevent diffusion of copper, the lower end of which contacts the first barrier film, and the second barrier film whose end contacts the second barrier film. And a third barrier film formed to cover the upper surface of the upper gate electrode to prevent the diffusion of copper, and a source / drain formed on the silicon substrate so as to sandwich the region below the lower gate electrode. The lowermost layer of the barrier film is composed of a metal silicide layer or a layer made of a compound of refractory metal metal and silicon and nitrogen, and a layer of the metal silicide or a layer made of a compound of refractory metal metal, silicon and nitrogen. A layer of a refractory metal nitride is disposed on the upper side , and the uppermost layer is a multilayer film composed of a refractory metal. The second barrier film and the third barrier film are made of a refractory metal or a refractory metal. It is made of a nitride. The field effect transistor according to claim 6 of the present invention is a lower gate electrode made of silicon formed on a silicon substrate via a gate insulating film, and an upper gate made of copper formed on the lower gate electrode. An electrode, a first barrier film having a conductivity capable of injecting a current sufficient to drive a channel portion into the lower gate electrode, and formed to cover the lower surface of the upper gate electrode to prevent the diffusion of copper; A second barrier film formed to cover both side surfaces of the upper gate electrode so as to prevent diffusion of copper, the lower end of which contacts the first barrier film and an end portion of the second barrier film which contacts the second barrier film. A third barrier film formed of either one of silicon nitride or boron nitride, which is formed to cover the upper surface of the gate electrode and blocks diffusion of copper, and silicon so as to sandwich the region below the lower gate electrode. The first barrier film comprises a metal silicide layer or a layer composed of a compound of a refractory metal metal and silicon and nitrogen. The source and drain are formed on the plate. A refractory metal nitride layer is disposed on a layer composed of a refractory metal metal, a compound of silicon and nitrogen, and the uppermost layer is a multilayer film composed of a refractory metal.

A method of manufacturing a field effect transistor according to a seventh aspect of the present invention includes a step of forming a gate insulating film on a silicon substrate and a step of forming a lower gate electrode made of silicon on the gate insulating film. A step of forming an etching stopper layer on the lower gate electrode, and
A step of forming a sacrificial pattern on the stopper layer, a step of forming a source / drain by introducing impurities into a predetermined amount region of the silicon substrate using the lower gate electrode and the sacrificial pattern as a mask, a step of forming the lower gate electrode and the sacrificial pattern Forming a first interlayer insulating film made of silicon oxide on the silicon substrate so as to cover the silicon substrate, removing the first interlayer insulating film to expose the upper surface of the sacrificial pattern, and selectively removing the sacrificial pattern. To remove the etching
Step of exposing top surface of per layer and etching stopper
The a step of forming a groove at the bottom gate electrode upper to expose the lower gate electrode upper surface by removing the layers, a conductive to prevent diffusion of copper to cover the side surfaces of the lower gate electrode upper surface and the groove 1 forming a barrier film and the second barrier film, the bottom surface of the first barrier film and the second barrier film through forming an upper gate electrode made of copper upper gate electrode on the inner portion of the groove and Forming a state in which both side surfaces are covered with the first barrier film and the second barrier film, and forming a third barrier film that blocks the diffusion of copper so as to close the exposed upper surface of the upper gate electrode And at least the step of performing. According to the present invention, the upper gate electrode includes the first to third parts, which are different from other parts constituting the field effect transistor.
It is produced in a state of being in contact through the barrier film of.

Further, a method of manufacturing a field effect transistor according to claim 8 of the present invention comprises a step of forming a gate insulating film on a silicon substrate, and a step of forming a lower gate electrode made of silicon on the gate insulating film. By forming an etching stopper layer on the lower gate electrode, forming a sacrificial pattern on the etching stopper layer, and introducing impurities into a predetermined amount region of the silicon substrate using the lower gate electrode and the sacrificial pattern as a mask. A step of forming the source / drain, a step of forming a first interlayer insulating film made of silicon oxide on the silicon substrate so as to cover the lower gate electrode and the sacrificial pattern, and a step of selectively forming the first interlayer insulating film. forming a groove in the lower gate electrode upper to expose the upper surface of the sacrificial pattern is removed, selectively the sacrificial pattern Conductive and removed by the blocking thereby exposing an etching stopper layer top surface, a step of exposing the lower gate electrode upper surface by removing the etching stopper layer, the diffusion of copper to cover the side surfaces of the lower gate electrode upper surface and the groove Of forming a first barrier film and a second barrier film having a property, and forming an upper gate electrode made of copper inside the groove through the first barrier film and the second barrier film to form an upper gate The bottom and both sides of the electrode are the first barrier
A step of covering with the film and the second barrier film,
And a step of forming a third barrier film that blocks the diffusion of copper so as to block the exposed upper surface of the upper gate electrode. According to the present invention, the upper gate electrode is formed in a state of being in contact with other portions forming the field effect transistor via the first to third barrier films. The sacrificial pattern is under the specified etching treatment conditions.
Is it a material that etches faster than silicon oxide?
Consists of

The field effect according to claim 17 of the present invention.
The method of manufacturing a transistor is based on the fact that a gate is formed on a silicon substrate.
The process of forming the edge film and the silicon on the gate insulating film
Forming a lower gate electrode, and the lower gate electrode
The process of forming a sacrificial pattern on top and the lower gate electrode and
And a predetermined amount of silicon substrate using the sacrificial pattern as a mask
Source / drain is formed by introducing impurities into the region
Process and both sides of lower gate electrode and sacrificial pattern
A side wall made of an insulating material that prevents the diffusion of copper
To cover the process and the lower gate electrode and the sacrificial pattern
A first layer of silicon oxide on a silicon substrate
The step of forming an insulating film, and removing the first interlayer insulating film
The step of exposing the upper surface of the sacrificial pattern and the sacrificial pattern
Are selectively removed to form a groove above the lower gate electrode
Process and cover the top surface of the lower gate electrode so that both ends contact the sidewalls
First burr having conductivity to prevent copper diffusion
A step of forming a film, and the first barrier film is placed inside the groove.
To form an upper gate electrode made of copper.
The bottom of the pole is covered with the first barrier film
And a step of making it covered with the second barrier film
Diffuse copper so as to cover the exposed upper surface of the gate electrode.
Forming a third barrier film for blocking at least
Provided, in addition, a film of refractory metal in contact with the lower gate electrode
And a heat treatment to contact the lower gate electrode
The refractory metal film is silicided to contact the lower gate electrode.
To form a silicide film of a refractory metal to form a first barrier
And a step of forming a part of the film.
According to the present invention, the upper gate electrode is formed in a state of being in contact with other portions forming the field effect transistor via the first to third barrier films. Also, the second barrier film
Is also used on the side wall.

According to an eighteenth aspect of the present invention, there is provided a method of manufacturing a field effect transistor, comprising: forming a gate on a silicon substrate.
The process of forming the edge film and the silicon on the gate insulating film
Forming a lower gate electrode, and the lower gate electrode
Step of forming an etching stopper layer on top and etching
Forming a sacrificial pattern on the insulating stopper layer,
Use the lower gate electrode and the sacrificial pattern as a mask
By introducing impurities into the specified amount area of the substrate,
Drain formation process, lower gate electrode, etch
Copper on both sides of the stopper layer and the sacrificial pattern.
Forming sidewalls of insulating material that prevent diffusion
And the lower gate electrode, etching stopper layer, and
And silicon on the silicon substrate to cover the sacrificial pattern.
A step of forming a first interlayer insulating film made of a silicon oxide,
The first interlayer insulating film is removed to expose the upper surface of the sacrificial pattern
Etching and selectively removing the sacrificial pattern
Step of exposing the upper surface of the stopper layer and etching
Remove the stopper layer to form a groove above the lower gate electrode
And the lower gate electrode in close contact with the upper surface
Has a conductivity that blocks the diffusion of copper so that it contacts the sidewalls.
Forming a first barrier film, and
Forming an upper gate electrode made of copper through the barrier film of
The bottom surface of the upper gate electrode is covered with the first barrier film.
It is assumed that the side surface is covered with the second barrier film having the side wall.
And the exposed upper surface of the upper gate electrode.
Of forming a third barrier film that blocks the diffusion of copper
And at least. According to this invention,
The upper gate electrode is formed in a state of being in contact with the other part of the field effect transistor via the first to third barrier films. The second barrier film is also used as the side wall.

According to a nineteenth aspect of the present invention, there is provided a method of manufacturing a field effect transistor, comprising: forming a gate on a silicon substrate.
The process of forming the edge film and the silicon on the gate insulating film
Forming a lower gate electrode, and the lower gate electrode
Step of forming an etching stopper layer on top and etching
Forming a sacrificial pattern on the insulating stopper layer,
Use the lower gate electrode and the sacrificial pattern as a mask
By introducing impurities into the specified amount area of the substrate,
Drain formation process, lower gate electrode, etch
Copper on both sides of the stopper layer and the sacrificial pattern.
Forming sidewalls of insulating material that prevent diffusion
And the lower gate electrode, etching stopper layer, and
And silicon on the silicon substrate to cover the sacrificial pattern.
A step of forming a first interlayer insulating film made of a silicon oxide,
On the sacrificial pattern by selectively removing the first interlayer insulating film
Step of exposing the surface and forming a groove above the lower gate electrode
, The sacrificial pattern is selectively removed to remove the etching
Step of exposing top surface of per layer and etching stopper
The process of removing the layer and the upper surface by adhering to the lower gate electrode
A conductor that blocks the diffusion of copper so that both ends of the cover contact the sidewalls.
The step of forming the first barrier film having electrical conductivity and the inside of the groove
Upper gate electrode made of copper through the first barrier film
And the bottom surface of the upper gate electrode is covered with the first barrier film.
And was covered with a second barrier film that has sidewalls on both sides
State and the upper surface where the upper gate electrode is exposed
A third barrier film that blocks the diffusion of copper so as to block the
And at least the step of performing . According to the present invention, the upper gate electrode is formed in a state of being in contact with other portions forming the field effect transistor via the first to third barrier films. The second barrier film is also used as the side wall.

According to a twenty-fourth aspect of the present invention, there is provided a method of manufacturing a field effect transistor, comprising: forming a gate on a silicon substrate.
The process of forming the edge film and the silicon on the gate insulating film
Forming a lower gate electrode, and the lower gate electrode
The process of forming a sacrificial pattern on top and the lower gate electrode and
And a predetermined amount of silicon substrate using the sacrificial pattern as a mask
Source / drain is formed by introducing impurities into the region
Process and cover the lower gate electrode and the sacrificial pattern.
First layer of silicon oxide on a silicon substrate
The step of forming the inter-layer insulation film and removing the first interlayer insulation film.
Exposing the upper surface of the sacrificial pattern, and the sacrificial pattern
To selectively expose the upper surface of the lower gate electrode.
Form a groove above the lower gate electrode of the first interlayer insulating film
To cover the process and the upper surface of the lower gate electrode and the side surface of the groove.
The first barrier film and the conductive first barrier film that prevent the diffusion of copper.
And a step of forming a second barrier film, and
Made of copper through the barrier film and the second barrier film of
Forming a gate electrode on the bottom surface of the upper gate electrode and both
The side surface is covered with the first barrier film and the second barrier film
State and the upper surface where the upper gate electrode is exposed
A third barrier film that blocks the diffusion of copper so as to block the
And at least the step of
Is exposed and the groove is formed, the first refractory metal film is formed.
The step of forming a film and the refractory metal on the first refractory metal film.
On the nitride film of this refractory metal
The step of forming a second refractory metal film and the film of copper
Process, copper in the area other than the groove, the first refractory metal film, high melting
The point metal nitride film and the second refractory metal film are removed, and copper is removed.
Upper gate electrode and first refractory metal film, refractory metal
Barrier film consisting of the second nitride film and the second refractory metal film
And a step of forming a second barrier film . According to the present invention, the upper gate electrode has the first to the other parts forming the field effect transistor.
It is produced in a state of being in contact with the third barrier film .

The field effect according to claim 25 of the present invention
The method of manufacturing a transistor is based on the fact that a gate is formed on a silicon substrate.
The process of forming the edge film and the silicon on the gate insulating film
Forming a lower gate electrode, and the lower gate electrode
The process of forming a sacrificial pattern on top and the lower gate electrode and
And a predetermined amount of silicon substrate using the sacrificial pattern as a mask
Source / drain is formed by introducing impurities into the region
Process and cover the lower gate electrode and the sacrificial pattern.
First layer of silicon oxide on a silicon substrate
The step of forming the inter-layer insulation film and removing the first interlayer insulation film.
Exposing the upper surface of the sacrificial pattern, and the sacrificial pattern
To selectively expose the upper surface of the lower gate electrode.
Form a groove above the lower gate electrode of the first interlayer insulating film
To cover the process and the upper surface of the lower gate electrode and the side surface of the groove.
The first barrier film and the conductive first barrier film that prevent the diffusion of copper.
And a step of forming a second barrier film, and
Made of copper through the barrier film and the second barrier film of
Forming a gate electrode on the bottom surface of the upper gate electrode and both
The side surface is covered with the first barrier film and the second barrier film
State and the upper surface where the upper gate electrode is exposed
A third barrier film that blocks the diffusion of copper so as to block the
And a lower gate electrode
After the upper surface is exposed and the groove is formed, refractory metal and silicon
Of forming a compound film consisting of a compound of nitrogen and nitrogen
And a nitride film of refractory metal is formed on this compound film
A step, a step of forming a copper film to be an upper gate electrode, and a groove
Copper, compound film, and nitride film of refractory metal in areas other than
The upper gate electrode made of copper, the compound film, and the refractory metal
Barrier film and second barrier film made of the above nitride film
And a step of forming.

A field effect according to claim 26 of the present invention.
The method of manufacturing a transistor is based on the fact that a gate is formed on a silicon substrate.
The process of forming the edge film and the silicon on the gate insulating film
Forming a lower gate electrode, and the lower gate electrode
The process of forming a sacrificial pattern on top and the lower gate electrode and
And a predetermined amount of silicon substrate using the sacrificial pattern as a mask
Source / drain is formed by introducing impurities into the region
Process and cover the lower gate electrode and the sacrificial pattern.
First layer of silicon oxide on a silicon substrate
The step of forming the inter-layer insulation film and removing the first interlayer insulation film.
Exposing the upper surface of the sacrificial pattern, and the sacrificial pattern
To selectively expose the upper surface of the lower gate electrode.
Form a groove above the lower gate electrode of the first interlayer insulating film
To cover the process and the upper surface of the lower gate electrode and the side surface of the groove.
The first barrier film and the conductive first barrier film that prevent the diffusion of copper.
And a step of forming a second barrier film, and
Made of copper through the barrier film and the second barrier film of
Forming a gate electrode on the bottom surface of the upper gate electrode and both
The side surface is covered with the first barrier film and the second barrier film
State and the upper surface where the upper gate electrode is exposed
A third barrier film that blocks the diffusion of copper so as to block the
And a lower gate electrode
After the upper surface is exposed and the groove is formed, refractory metal and silicon
Of forming a compound film consisting of a compound of nitrogen and nitrogen
And a nitride film of refractory metal is formed on this compound film
Process and forming a refractory metal film on this refractory metal nitride film.
Film forming process and copper film forming upper gate electrode
And nitriding of copper, compound film, and refractory metal in regions other than trenches
The upper gate electrode made of copper by removing the film and refractory metal film
And compound film, refractory metal nitride film, refractory metal film
Forming a first barrier film and a second barrier film
And at least.

The electric field effect according to claim 27 of the present invention
The method of manufacturing a transistor is based on the fact that a gate is formed on a silicon substrate.
The process of forming the edge film and the silicon on the gate insulating film
Forming a lower gate electrode, and the lower gate electrode
The process of forming a sacrificial pattern on top and the lower gate electrode and
And a predetermined amount of silicon substrate using the sacrificial pattern as a mask
Source / drain is formed by introducing impurities into the region
Process and cover the lower gate electrode and the sacrificial pattern.
First layer of silicon oxide on a silicon substrate
The step of forming the inter-layer insulation film and removing the first interlayer insulation film.
Exposing the upper surface of the sacrificial pattern, and the sacrificial pattern
To selectively expose the upper surface of the lower gate electrode.
Form a groove above the lower gate electrode of the first interlayer insulating film
To cover the process and the upper surface of the lower gate electrode and the side surface of the groove.
The first barrier film and the conductive first barrier film that prevent the diffusion of copper.
And a step of forming a second barrier film, and
Made of copper through the barrier film and the second barrier film of
Forming a gate electrode on the bottom surface of the upper gate electrode and both
The side surface is covered with the first barrier film and the second barrier film
State and the upper surface where the upper gate electrode is exposed
A third barrier film that blocks the diffusion of copper so as to block the
And a lower gate electrode
After the upper surface is exposed and the groove is formed, a refractory metal film is formed
And a refractory metal nitride film on the refractory metal film.
Film forming step, copper film forming step, and regions other than the groove
Copper, refractory metal film, refractory metal nitride film removed, copper
Of the upper gate electrode and refractory metal film and refractory metal
The first barrier film and the second barrier film made of a nitride film
The process of forming and contacting the lower gate electrode
Step of forming film and heat treatment to contact lower gate electrode
The refractory metal film is silicided to form the lower gate electrode.
Contact with each other to form a refractory metal silicide film,
(A) At least the step of forming a part of the film.
It

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. First Embodiment First, a first embodiment of the present invention will be described.
FIG. 1 is a sectional view showing the structure of the field effect transistor according to the first embodiment. The field-effect transistor according to the first embodiment first includes a lower gate electrode 103 made of polysilicon on a silicon substrate 101 with a gate insulating film 102 interposed therebetween. Also, the lower gate electrode 1
On 03, an upper gate electrode 104 made of copper is provided. The upper gate electrode 104 has a barrier film (first and second barrier films) made of tantalum nitride so as to cover the lower surface and the side surface.
Barrier film) 105, and a barrier film (third barrier film) 106 made of silicon nitride is formed so as to cover the upper surface. Therefore, the upper gate electrode 104 is in a state of being covered with the barrier films 105 and 106 in a cylindrical shape. Then, the lower gate electrode 10
3 and the upper gate electrode 104 form the gate electrode of the transistor.

A side wall 107 made of silicon oxide is formed so as to cover the side surface of the gate electrode. Further, a low concentration impurity region 108 is formed in the silicon substrate 101 below the sidewall 107. A source 109 and a drain 110 are formed on the silicon substrate 101 so as to sandwich the low concentration impurity region 108. Then, the low-concentration impurity region 108, the source 109 and the drain 110, the gate insulating film 102, and the gate electrode composed of the lower gate electrode 103 and the upper gate electrode 104 constitute a field effect transistor having an LDD structure. With the LDD structure, the single channel effect can be suppressed.

As described above, in the field effect transistor according to the first embodiment, since the gate electrode has the laminated structure of polysilicon and copper, the resistance of the gate electrode is reduced. Further, in the first embodiment, the copper portion forming the gate electrode is covered not only with the upper and lower surfaces but also with the side surfaces, so that the diffusion of copper through the silicon oxide film can be suppressed. Become.
As a result, problems due to diffusion of copper, such as generation of junction leakage current and reduction of transistor on-current, are solved.

Next, a method of manufacturing the above-mentioned field effect transistor of the first embodiment will be described. First, FIG.
As shown in (a), an insulating film 202 having a film thickness of about 6 nm is formed on the silicon substrate 101 by dry oxidation. The insulating film 202 becomes a gate insulating film. Subsequently, a polysilicon film 203 having a film thickness of about 70 nm is formed on the insulating film 202 by a low pressure CVD method, and a low voltage CV is formed on the polysilicon film 203.
The silicon nitride film 204 having a thickness of about 100 nm is formed by the D method.
To form.

Next, as shown in FIG. 2B, the silicon nitride film 204 and the polysilicon film 203 are dry-etched by using the resist pattern 205 as a mask.
Are selectively removed to form the lower gate electrode 103 and the sacrificial pattern 204a. Next, after removing the resist pattern 205, as shown in FIG. 2C, the sacrificial pattern 204a and the lower gate electrode 103 are selectively ion-implanted to form a low-concentration impurity region (LDD) 108. To do. Here, As is ion-implanted with an implantation energy of 20 eV, and the implantation amount is 3 × 10 ^13.
It may be about cm ^-2 .

Next, as shown in FIG. 2D, a silicon oxide film 206 is formed on the entire surface. This may be performed by depositing silicon oxide by a low pressure CVD method using TEOS as a raw material. Then, the silicon oxide film 206 is etched back by reactive ion etching (RIE) having vertical anisotropy, so that the lower gate electrode 103 and the sacrificial pattern 20 are formed as shown in FIG.
Sidewalls 107 are formed on the side surfaces of 4a.

Next, as shown in FIG. 3F, the source 109 and the drain 110 are formed by selectively ion-implanting the sacrificial pattern 204a, the lower gate electrode 103, and the side wall 107 as a mask. . Here, As is ion-implanted with an implantation energy of 30 eV, and the implantation amount may be about 3 × 10 ¹⁵ cm ⁻² .
Next, boron phosphorus silicate glass is deposited by CVD using ozone and TEOS as raw materials to form a lower interlayer insulating film 209 with a film thickness of about 500 nm as shown in FIG.

Next, chemical mechanical polishing of the oxide film (CM
P), the lower interlayer insulating film 209 is planarized and polished, so that the sacrificial pattern 204a is formed as shown in FIG.
Expose the top. Next, the sacrificial pattern 204a is selectively removed by wet etching using a heated phosphoric acid aqueous solution, and as shown in FIG. 3I, the sidewall 107 and the lower interlayer insulating film 209 are formed on the lower gate electrode 103. Forming a groove 210 surrounded by. In this wet etching with hot phosphoric acid, since silicon and silicon oxide are not etched so much, the sacrificial pattern 204a made of silicon nitride can be selectively removed.

By the way, in the above-described first embodiment, C
Although the upper part of the sacrificial pattern 204a is exposed by removing the lower interlayer insulating film 209 by MP, the upper part of the sacrificial pattern 204a may be exposed by the following method. For example, in the case where flattening is possible by reflow like boron silicate glass, the upper part of the sacrificial pattern 204a may be exposed by removing it by dry etching or the like after the lower interlayer insulating film is reflowed and flattened. Good. At this time, in addition to boron silicate glass, silicate glass (BPSG) containing boron and phosphorus can be used as the lower interlayer insulating film.

Further, an SOG (spin-on-glass) material is used as the lower interlayer insulating film, and is flattened by applying the material, and then the flattened coating film is etched back by dry etching or the like to expose the upper portion of the sacrificial pattern 204a. It may be exposed. Here, when the CMP method or the method of flattening using an SOG material and then etching back is used, the lower interlayer insulating film is formed by the usual silicon oxide film by the CVD method or the like without using silicate glass. Or a silicon nitride film.

Next, as shown in FIG. 4 (j), a tantalum nitride film is deposited on the lower interlayer insulating film 209 including the bottom and side surfaces of the groove 210 by a sputtering method to have a film thickness of 10 nm.
The TaN film 211 is formed to a certain degree, and then the TaN film 21 is formed.
Copper is sputtered on the surface of 1 and C of about 200 nm
The u layer 212 is formed. Next, for example, CMP of a metal film
By removing the Cu layer 212 and the TaN film 211 by polishing, the groove 210 is removed as shown in FIG.
The barrier film 105 made of tantalum nitride has therein an upper gate electrode 104 made of copper whose lower and side surfaces are covered, and in addition, the surface of the lower interlayer insulating film 209 other than the upper part of the upper gate electrode 104 is exposed. .

Next, as shown in FIG. 4L, a barrier film 106 made of silicon nitride and having a thickness of about 10 nm is formed on the entire surface.
To form. This may be performed by depositing silicon nitride by the plasma CVD method. As described above, the field effect transistor including the gate electrode including the lower gate electrode 103 made of polysilicon and the upper gate electrode 104 made of copper covered with the barrier film 105 and the barrier film 106 was formed. It will be.

The barrier film 106 does not need to be formed so as to extend onto the lower interlayer insulating film 209. As shown in FIG. 1, the upper gate electrode 10 is formed by the barrier film 106.
The barrier film 106 may be formed in a region where only the upper surface of 4 is covered. In this case, since the barrier film 106 does not extend onto the lower interlayer insulating film 209, the barrier film 106 may be made of, for example, tantalum nitride having the same conductivity as the barrier film 105.

Thereafter, as shown in FIG. 4M, an interlayer insulating film 111 made of silicon oxide (BPSG) to which boron and phosphorus are added is formed on the barrier film 106 to a thickness of 500.
It is formed to have a thickness of about nm. This is, for example, oxygen gas and TE
It may be formed by a CVD method using OS as a raw material. Next, as shown in FIG.
And the through hole 113 is formed. This may be formed by anisotropic dry etching using a resist pattern formed by a known photolithography graph as a mask. The contact hole 112 has a bottom surface exposing the surface of the source 109 of the silicon substrate 101, and a bottom surface of the through hole 113 exposing the upper surface of the upper gate electrode 104.

Next, as shown in FIG. 5O, a barrier film 114 having a two-layer structure of titanium nitride and titanium is formed on the interlayer insulating film 111, including the side surfaces and bottom surfaces of the contact hole 112 and the through hole 113. Form. This is a CVD
The film thickness may be about 50 nm and about 10 nm, respectively. Subsequently, as shown in FIG. 5P, the W film 11 made of tungsten is formed on the barrier film 114.
5 is formed to have a film thickness of about 400 nm by, for example, a low pressure CVD method.

Next, the W film 1 is formed to the extent that the contact hole 112 and the through hole 113 are filled.
15 is removed by dry etching or the like. As a result, after the plugs 112a and 113a are formed (see FIG.
(Q)), an alloy film 115a made of an aluminum-copper alloy with copper of about 1% is formed to a film thickness of about 500 nm by a sputtering method. In addition, the barrier film 116 made of titanium nitride is formed to a thickness of about 30 nm by the sputtering method. Then, the alloy film 115a and the barrier films 114, 1
If 16 is patterned, as shown in FIG.
The source electrode wiring 117 and the gate electrode wiring 118 can be formed.

When manufactured as described above, after forming the source / drain, the upper gate electrode made of copper is formed. That is, since the upper gate electrode is formed after the high-temperature activation heat treatment for forming the source / drain, the upper gate electrode can be formed by using copper whose melting point is not so high. In the first embodiment, the barrier film (first and second barrier films) 105
Although tantalum nitride is used as the above, the present invention is not limited to this, and nitrides such as titanium nitride, tungsten nitride, tantalum nitride, molybdenum nitride, titanium nitride silicide, and tungsten nitride silicide (compounds of refractory metal and silicon and nitrogen) are used. ) Or a metal material such as tantalum or titanium tungsten may be used.

By the way, the above-mentioned barrier films (first to third)
The barrier film) may be made of a material having a function of preventing diffusion of copper that does not contain oxygen as a constituent element. Since the upper gate electrode is made of copper, the oxidation of copper can be suppressed without oxygen. Further, for example, silicon nitride may be used for the barrier film (first barrier film) arranged on the lower surface of the upper gate electrode. That is, since the barrier film needs to be conductive enough to inject a current sufficient for driving the channel portion into the lower gate electrode, silicon nitride may be used so that the film thickness is such that a tunnel current flows. In this case, if the surface of the lower gate electrode is nitrided by, for example, about 2 nm, the barrier film can be formed in this nitrided portion.

Further, a barrier film (first barrier film) arranged between the barrier film (second barrier film) arranged on the side surface of the above-mentioned copper upper gate electrode and the lower gate electrode.
May be a multi-layer film composed of two or more layers.
When diffusing in a solid, there is a high possibility that the diffusing species will be deposited at the interface or grain boundary of the solid material (when the film is polycrystalline). Therefore, by forming a multilayer film in which barrier films are laminated,
It is possible to capture a slight amount of diffused copper at the interface between the films and further prevent the diffusion of the diffused species. This multilayer film is preferably a high melting point metal or a composite film of high melting point metals. For example, a composite film of Ta and Ta nitride may be used.
Since metals such as copper are less likely to diffuse into thermally stable metal nitrides, the use of a refractory metal nitride film as a barrier film also reduces the amount of point defects, and copper diffusion via point defects is suppressed. It

Disposing the refractory metal silicide in contact with the lower gate electrode of silicon as a part of the first barrier film having a multilayer film structure is also effective for improving the operating performance of the field effect transistor. is there. This is because formation of the Schottky barrier is suppressed and contact resistance is reduced at the interface between the silicide and silicon. In the first barrier film of the multilayer film, it is also effective to improve the adhesiveness between the copper and the first barrier film by making the film in contact with copper a refractory metal. It is also effective for improving the device manufacturing yield that the compound of the refractory metal, silicon and nitrogen is arranged in contact with the lower electrode of silicon as a part of the first barrier film having a multilayer film structure. This is because the above compound has good adhesion to silicon. For example, tungsten nitride is CV
The above compound can be formed by forming a film in the groove by the D method or the reactive collimating sputtering method, and then performing a heat treatment at a temperature of about 500 ° C. At this time, since the above compound is formed by the reaction between silicon and the refractory metal nitride, the adhesion with silicon is improved.

Second Embodiment Next, a second embodiment of the present invention will be described. First, a method of manufacturing the field effect transistor according to the second embodiment will be described. First, as shown in FIG. 6A, a film thickness of 6 n is formed on the silicon substrate 601 by dry oxidation.
A gate insulating film 602 is formed with a thickness of about m. Then,
A film thickness of 50 n is formed on the gate insulating film 602 by the low pressure CVD method.
Polysilicon film 70 in which n-type impurities are introduced to about m
3 is formed, and a silicon oxide film 704 having a film thickness of about 10 nm is formed thereon by the CVD method. In addition, a film thickness of 100 to 100 is formed on the silicon oxide film 704 by the CVD method.
A polysilicon film 705 is formed to a thickness of about 300 nm.

Next, as shown in FIG. 6B, the polysilicon film 705, the silicon oxide film 704, and the polysilicon film 703 are selectively removed by dry etching using the resist pattern 706 as a mask, A lower gate electrode 603, an etching stopper layer 704a, and a sacrificial pattern 705a are formed. Next, after removing the resist pattern 706, as shown in FIG. 6C, the sacrificial pattern 705a and the lower gate electrode 60 are formed.
By selectively ion-implanting using 3 as a mask, a low concentration impurity region (LDD) 608 is formed. here,
As is ion-implanted with an implantation energy of 20 eV, and the implantation amount may be about 1 × 10 ¹³ cm ⁻² .

Next, as shown in FIG. 6D, a silicon oxide film 707 is formed on the entire surface. This may be performed by depositing silicon oxide by a low pressure CVD method using TEOS as a raw material. Then, by etching back the silicon oxide film 707 by reactive ion etching (RIE) having vertical anisotropy, as shown in FIG. 6E, the lower gate electrode 603 and the sacrificial pattern 70 are formed.
Sidewalls 607 are formed on the side surfaces of 5a. The sidewall 607 may be made of silicon nitride. Also in this case, it can be formed in the same manner as the case of forming from silicon oxide.

Next, the source 609 and the drain 610 are formed by selectively ion-implanting the sacrificial pattern 705a, the lower gate electrode 603, and the sidewall 607 as a mask. Here, As is ion-implanted with an implantation energy of 30 eV, and the implantation amount is 2 × 1.
It may be about 0 ¹⁵ cm ^-2 . The impurity introduction region formed by the ion implantation is, for example, 80 in a nitrogen atmosphere.
Heat treatment is performed at 0 ° C. for 10 minutes and 1000 ° C. for 10 seconds to reduce defects and activate impurities.

Next, CV using ozone and TEOS as raw materials
By depositing boron phosphorus silicate glass by D, heating and flowing them, as shown in FIG. 7G, the lower interlayer insulating film 7 is formed to a film thickness of about 400 to 600 nm.
09 is formed. Next, the lower interlayer insulating film 709 is removed by a predetermined film thickness by, for example, chemical mechanical polishing (CMP) of the oxide film, and as shown in FIG.
a) The upper part is exposed. Next, the sacrificial pattern 705a is selectively removed by reactive ion etching having high selectivity with respect to the oxide film, and as shown in FIG.
A trench 710 surrounded by a sidewall 607 and a lower interlayer insulating film 709 is formed on the lower gate electrode 603.

Subsequently, as shown in FIG. 7J, the etching stopper layer 704a is removed by an etching method having a selection ratio with silicon oxide, and the upper surface of the lower gate electrode 603 is exposed at the bottom of the groove 710. Next, as shown in FIG. 8K, a tantalum nitride film is deposited on the lower interlayer insulating film 709 including the bottom and side surfaces of the groove 710 by sputtering to form a TaN film 711 with a film thickness of about 10 nm. Subsequently, as shown in FIG. 8 (l), copper is deposited on the TaN film 711 by sputtering, and the deposited copper is heated and flowed to form a film having a flat surface of 100 to 500.
A Cu layer 712 having a thickness of about nm is formed.

Here, instead of the TaN film 711, a thin film of titanium nitride, tantalum, tungsten nitride, titanium tungsten, or the like may be used. Also, Cu
The layer 612 may be formed by an electroplating method or a CVD method, for example. Next, for example, CMP of a metal film
Thus, by removing the Cu layer 712 and the TaN film 711, an upper gate electrode 604 made of copper is formed, as shown in FIG. In addition, the lower interlayer insulating film 70 other than on the upper gate electrode 604 is formed.
9 expose the surface. Instead of the TaN film 711, a laminated film of high melting point gold and high melting point metal nitride such as TaN / Ta or Ta / TaN / Ta film may be used.

Further, by using the collimate sputtering method as the method for forming the above-mentioned laminated film, the layer resistance of the gate electrode is reduced and the layer resistance is suppressed from increasing when the width of the groove is reduced. According to the collimated sputtering method, the particles sputtered by the plasma from the raw material target, which are caused by the film formation, have an angle of incidence on the substrate which is almost vertical due to the collimator. Therefore, the film thickness formed on the sidewall of the groove is thinner than the film thickness formed on the bottom of the groove. When the resistivity of the material of the barrier film is higher than that of copper, if the film thickness on the side surface is large, the resistance increases in proportion to this film thickness. Also, when the width of the groove is reduced, the layer resistance is increased. Therefore, it is better to reduce the film thickness formed on the side wall in the groove by the above-mentioned collimating sputtering method. Similar effect,
It can also be obtained by a method called an ionization sputtering method. The ionization sputtering method is a method in which raw material particles ionized by a bias applied to the substrate are incident on the substrate at an angle close to vertical, and the incident particles are deposited to form a film, which is also formed on the sidewall in the groove. The film thickness can be reduced.

Next, as shown in FIG. 8 (n), a film thickness of 10 to 10 made of titanium oxide or silicon nitride is formed on the entire surface.
A barrier film 606 having a thickness of about 0 nm is formed. This may be formed by, for example, a reactive sputtering method. With the above, the lower gate electrode 60 made of polysilicon is formed.
3 and the gate electrode composed of the upper gate electrode 604 made of copper whose periphery is covered with the barrier film 605 and the barrier film 606 are formed. The barrier film 606 is the lower interlayer insulating film 70.
It is not necessary to extend and form over 9. Barrier film 60
The barrier film 606 may be formed in a region where only the upper surface of the upper gate electrode 604 is covered with 6. In this case, since the barrier film 606 does not extend onto the lower interlayer insulating film 709, the barrier film 606 may be made of, for example, the same tantalum nitride as the barrier film 605.

Thereafter, as shown in FIG. 8O, an interlayer insulating film 713 made of silicon oxide (BPSG) to which boron and phosphorus are added is formed on the barrier film 606 to a film thickness of 100.
The thickness is about 500 nm. This may be formed, for example, by a CVD method using oxygen gas and TEOS as raw materials. Next, as shown in FIG. 9P, contact holes 612 and 613 are formed. This may be formed by anisotropic dry etching using a resist pattern formed by a known photolithography graph as a mask. The contact hole 612 has a bottom surface exposing the surface of the source 609 of the silicon substrate 601, and the contact hole 613 has a bottom surface having the drain 6 of the silicon substrate 601.
10 exposed

Then, as shown in FIG. 9Q, the source electrode wiring 616 and the drain electrode wiring 6 made of aluminum or the like are provided through the contact holes 612 and 613.
17 may be formed. From the above, the second embodiment
Also in this case, since the gate electrode has a laminated structure of polysilicon and copper, the resistance of the gate electrode is reduced. Also in the second embodiment, the copper portion forming the gate electrode is not limited to the upper and lower surfaces of the body portion,
Since the side surface is covered with the barrier film, the diffusion of copper through the silicon oxide film can be suppressed. As a result, problems due to diffusion of copper, such as generation of junction leakage current and reduction of transistor on-current, are solved.

Also in the second embodiment, the source
After forming the drain, an upper gate electrode made of copper is formed. That is, since the upper gate electrode is formed after the high-temperature activation heat treatment for forming the source / drain, the upper gate electrode can be formed by using copper whose melting point is not so high.

By the way, the sidewall may be made of silicon nitride. When the sidewall is formed of a material that can prevent diffusion of copper such as silicon nitride, the sidewall can be used as a barrier film (second barrier film) arranged on the side surface of the upper gate electrode described above. In this case, it is not necessary to newly form a barrier film to be arranged on the side surface of the upper gate electrode. That is, for example, as shown in FIG. 4J, a tantalum nitride film is not deposited on the lower interlayer insulating film 209 including the bottom and side surfaces of the groove 210 by a sputtering method. It is nitrided to some extent to form a first barrier film. As described above, since tunneling current flows in the case of silicon nitride having a film thickness of about 2 nm, there is no problem in conduction with the upper gate electrode.

At this time, instead of nitriding the upper portion of the lower gate electrode 103, it is possible to form a material having other conductivity which can prevent the diffusion of copper on the upper portion of the lower gate electrode 103. Needless to say. Then, by forming the upper gate electrode 104 on the first barrier film, the lower surface and both side surfaces of the upper gate electrode 104 can be covered with silicon nitride that prevents diffusion of copper. After that, the field effect transistor according to the present invention can be obtained by performing the same process as that of FIG.

If the side wall is made of a material that is less likely to be etched under a predetermined etching condition than silicon oxide such as silicon nitride, it becomes easy to contact the wiring on the upper gate electrode. This depends on the following reasons. First, a contact hole is formed in the interlayer insulating film formed on the upper gate electrode, and a wiring is connected to the upper gate electrode through this contact hole. At the time of forming this contact hole, since the silicon nitride is hardly etched by etching the interlayer insulating film made of silicon oxide, even if the contact hole forming position is slightly shifted,
This is because the sidewall is not etched.

By the way, in the above, as shown in FIG. 6B, the lower layer is processed by using the resist pattern 706 as a mask. However, the present invention is not limited to this. You may make it process using a hard mask. In addition, by using the hard mask, silicide of refractory metal can be selectively formed in the source / drain regions.

First, as shown in FIG. 10A, a gate insulating film 602 having a film thickness of about 6 nm is formed on a silicon substrate 601 by dry oxidation. Then, a film having a thickness of about 50 nm is formed on the gate insulating film 602 by a low pressure CVD method.
Form a polysilicon film 703 into which impurities are introduced, and form a silicon oxide film 704 with a film thickness of about 10 nm on the polysilicon film 703 by the CVD method.
A polysilicon film 705 having a film thickness of about 100 to 300 nm is formed thereon by the CVD method. In addition, a silicon oxide film 1001 is formed on the polysilicon film 705a.
Note that this silicon oxide film may be a silicon nitride film.

Next, as shown in FIG. 10B, the polysilicon film 705, the silicon oxide film 704, the polysilicon film 703, and the silicon oxide film 1001 are formed.
The lower gate electrode 603, the etching stopper layer 704a, and the sacrificial pattern 70 are selectively removed by dry etching using the resist pattern 706 as a mask.
5a is formed, and a hard mask 1001a is formed. Next, after removing the resist pattern 706, as shown in FIG. 10C, the hard mask 1001 is removed.
a, sacrificial pattern 705a and lower gate electrode 603
Is selectively used as a mask to form a low-concentration impurity region (LDD) 608. LDD608
Is ion-implanted with an implantation energy of 20 eV, and the implantation amount may be about 1 × 10 ¹³ cm ⁻² .

Next, as shown in FIG. 10 (d), TEO
A silicon oxide film 707 is formed on the entire surface by depositing silicon oxide by a low pressure CVD method using S as a raw material. Then, by etching back the silicon oxide film 707 by reactive ion etching (RIE) having vertical anisotropy, as shown in FIG. 10E, the lower gate electrode 603 and the sacrificial pattern 705a are formed. Sidewalls 607 are formed on the side surfaces. At the same time, a region of the gate insulating film 602 which is not covered with the lower gate electrode 603 and the sidewall 607 is removed. The sidewall 607 may be made of silicon nitride. Also in this case, it can be formed in the same manner as the case of forming from silicon oxide.

Next, the source 609 and the drain 610 are formed by selectively ion-implanting the sacrifice pattern 705a, the lower gate electrode 603, and the sidewall 607 as well as the hard mask 1001a as a mask. Also here, As may be ion-implanted with an implantation energy of 30 eV, and the implantation amount may be about 2 × 10 ¹⁵ cm ⁻² . The impurity introduction region formed by ion implantation is, for example, 800 ° C. for 10 minutes and 10 minutes in a nitrogen atmosphere.
Heat treatment is performed at 00 ° C. for 10 seconds to reduce defects and activate impurities.

Since the hard mask 1001a is used, the sacrificial pattern 705 made of silicon is used.
It becomes possible to form silicide on the surface of the source / drain regions in a self-aligned manner without forming silicide on a. As shown in FIG. 11F, a refractory metal film 1002 is formed by depositing cobalt in a film thickness of 10 to 20 nm over the entire area by a sputtering method or the like, and RTA (Rapid
1 is heated by a thermal anneal method to react the underlying silicon (silicon substrate 601) with the refractory metal film 1002.
1 (g), the source 609 and the drain 610
A silicide 1003 is selectively formed thereover. The heating temperature for forming this silicide is 650 to 750 ° C.
The degree is good. The atmosphere for heating is preferably an inert atmosphere such as nitrogen or argon.

After forming the silicide, as shown in FIG. 11H, the underlying silicon and unreacted cobalt are selectively removed by wet etching using a mixed aqueous solution of hydrochloric acid: hydrogen peroxide: water. . When heated in a nitrogen atmosphere, nitrided cobalt is generated, so this nitrided cobalt is also selectively removed by wet etching using a mixed aqueous solution of hydrochloric acid: hydrogen peroxide: water. After that, the resistance of the silicide can be reduced by heating again at a temperature of about 750 to 850 ° C. by the RTA method. In addition to cobalt, titanium (1
0 to 30 nm) may be used. When titanium is used, wet etching with a mixed aqueous solution of ammonia: hydrogen peroxide water: water may be used to remove the excess titanium or titanium nitride immediately after the silicide processing.

After the silicide is selectively formed in the source / drain regions, the film thickness of 400 to 6 is obtained as in the case of FIG.
The lower interlayer insulating film 709 is formed to have a thickness of about 00 nm, and then the lower interlayer insulating film 709 is removed by a predetermined thickness by chemical mechanical polishing (CMP) of the oxide film, and at the same time, the hard mass is also removed to remove the sacrificial pattern 705a. Expose the top. Thereafter, by performing the same steps as shown in FIGS. 7H to 9Q, as shown in FIG.
In addition to the configuration shown in (q), a state in which the silicide 1003 is formed is obtained. Since the silicide 1003 is selectively formed on the source 609 and the drain 610, the source electrode wiring 616 and the drain electrode wiring 6 are formed.
The contact resistance of 17 can be reduced.

The formation of silicide may be applied to the field effect transistor of the first embodiment described above. For example, when the side wall 107 shown in FIG. 3E is formed, if the portions of the gate insulating film 102 on the regions to be the source / drain are simultaneously removed, the surface of the silicon substrate 101 to be the source / drain is exposed. . After this,
Similarly to (f), if the source 109 and the drain 110 are formed and a film of a refractory metal such as cobalt or titanium is formed over the entire area, the source. A silicide can be selectively formed on the drain. In the first embodiment, since the sacrificial pattern 204a is made of silicon nitride and the sidewall 107 is made of silicon oxide, silicide is not formed on these surfaces. Thus, if the sidewall surface or the sacrificial film surface is hard to react with the refractory metal, it is possible to easily form the silicide selectively on the source / drain.

Next, a method of manufacturing a field effect transistor when the above-mentioned wall is used again as the second barrier film will be described. First, as shown in FIG. 12A, a film thickness of 6 n is formed on the silicon substrate 101 by dry oxidation.
The insulating film 202 is formed to a thickness of about m. The insulating film 202 becomes a gate insulating film. Subsequently, a low voltage C is formed on the insulating film 202.
The polysilicon film 203 having a film thickness of about 70 nm is formed by the VD method.
Then, in this case, a tantalum nitride film is deposited on the polysilicon film 203 by a sputtering method to obtain a film thickness of 10
A TaN film 1201 is formed to a thickness of about nm. And Ta
A polysilicon film 705 having a film thickness of about 100 nm is formed on the N film 1201 by a low temperature CVD method of about 400 ° C. or a plasma CVD method.

Next, as shown in FIG. 12B, the polysilicon film 705, the TaN film 1201, and the polysilicon film 203 are selectively removed by dry etching using the resist pattern 205 as a mask, and the lower gate is formed. The barrier film (first barrier film) 12 sandwiched between the electrode 103 and the sacrificial pattern 705a is formed.
01a is formed. Next, after removing the resist pattern 205, as shown in FIG. 12C, by selectively implanting ions using the sacrificial pattern 705 and the lower gate electrode 103 as a mask, the low concentration impurity region (LD
D) 108 is formed. Also here, As is ion-implanted with an implantation energy of 20 eV and the implantation amount is 3 × 10 ¹³ cm ^-2.
It should be about.

Next, as shown in FIG. 12D, a silicon nitride film 206a is formed on the entire surface. Then, by etching back the silicon nitride film 206a by reactive ion etching (RIE) having vertical anisotropy, as shown in FIG.
3, barrier film 1201a, and sacrificial pattern 705a
A side wall 107a is formed on the side surface of the. Since the sidewall 107a is made of silicon nitride, it can be used as a second barrier film that suppresses the diffusion of copper. Next, as shown in FIG. 12F, the source 109 and the drain 110 are formed by selectively implanting ions by using the sacrificial pattern 705a, the lower gate electrode 103, and the sidewall 107a as a mask. The source 109 and the drain 110 are formed by ion-implanting As with an implantation energy of 30 eV and the implantation amount is 3 ×.
It may be about 10 ¹⁵ cm ^-2 .

Next, CV using ozone and TEOS as raw materials
According to D, boron phosphorus silicate glass is deposited, and FIG.
As shown in FIG. 3G, the lower interlayer insulating film 209 is formed to have a film thickness of about 500 nm. Next, the lower interlayer insulating film 209 is planarized and polished by chemical mechanical polishing (CMP) of the oxide film to expose the upper portion of the sacrificial pattern 705a as shown in FIG. Next, the sacrificial pattern 705a is formed under the condition that the polysilicon is selectively etched.
13I, the sidewalls 107a and the lower interlayer insulating film 20 are formed on the lower gate electrode 103 whose upper surface is covered with the barrier film 1201a, as shown in FIG.
A groove 210 surrounded by 9 is formed.

Next, as shown in FIG. 13J, copper is deposited on the lower interlayer insulating film 209 (barrier film 1201a) including the bottom and side surfaces of the groove 210 by sputtering to have a film thickness of about 200 nm. The Cu layer 212 is formed. After this,
For example, as shown in FIG. 13 (r), by performing the same processing as that of FIG. 4 (k) to FIG. 5 (q) such as removing the Cu layer 212 by polishing by CMP of the metal film. A field effect transistor having the sidewall 107a as a second barrier film can be formed.

A barrier film (first barrier film) 1201a is formed by forming a thin silicon oxide film after forming the TaN film 1201 and before forming the polysilicon film.
An etching stopper layer made of silicon oxide may be provided between the sacrificial pattern 705a and the sacrificial pattern 705a. By providing the etching stopper layer, the selective removal of the sacrificial pattern 705a becomes easier. The etching stopper layer can be selectively removed with respect to the barrier film and the sidewall by, for example, wet etching with a hydrofluoric acid solution. In this case, the lower interlayer insulating film 209
Is also etched to some extent. As described above, since the upper gate electrode can be formed to have the same width as the lower gate electrode, the width of the upper gate electrode becomes longer than that in the first embodiment, and the resistance of the upper gate electrode decreases.

[0071]

As described above, according to the present invention, a lower gate electrode made of silicon formed on a silicon substrate via a gate insulating film, and an upper gate made of copper formed on the lower gate electrode. An electrode, a first barrier film having conductivity that can inject a current sufficient to drive the channel portion into the lower gate electrode, and formed to cover the lower surface of the upper gate electrode to prevent the diffusion of copper; A second barrier film which is formed so as to contact the lower end of the first barrier film and covers both side surfaces of the upper gate electrode to prevent diffusion of copper;
A third barrier film formed to cover the upper surface of the upper gate electrode to prevent the diffusion of copper, which is in contact with the second barrier film at its end portion, and formed on the silicon substrate so as to sandwich the region under the lower gate electrode. The first barrier film of the first barrier film comprises a metal silicide layer or a layer composed of a refractory metal metal and a compound of silicon and nitrogen. The metal silicide layer or the refractory metal is formed. A layer of a refractory metal nitride was arranged on a layer of a compound of metal, silicon, and nitrogen, and the uppermost layer was a multilayer film composed of a refractory metal. Therefore, the upper gate electrode is connected to the other parts of the field effect transistor and the first gate electrode.
~ It is configured to be in contact with the third barrier film. That is, the diffusion of copper from the upper gate electrode can be blocked in all directions. As a result, the present invention provides a material for a gate electrode of a field effect transistor,
It has an extremely excellent effect that copper can be used without deteriorating the characteristics of the transistor.

Further, in the present invention, the step of forming a gate insulating film on the silicon substrate, the step of forming a lower gate electrode made of silicon on the gate insulating film, and the step of forming a sacrificial pattern on the lower gate electrode. And a step of forming a source / drain by introducing impurities into a predetermined amount region of the silicon substrate using the lower gate electrode and the sacrificial pattern as a mask, and silicon oxide on the silicon substrate so as to cover the lower gate electrode and the sacrificial pattern. The first consisting of
Forming an interlayer insulating film, removing the first interlayer insulating film to expose the upper surface of the sacrificial pattern, and selectively removing the sacrificial pattern to expose the upper surface of the lower gate electrode. A step of forming a groove above the lower gate electrode of the interlayer insulating film, and a step of forming conductive first and second barrier films that prevent diffusion of copper so as to cover the upper surface of the lower gate electrode and the side surface of the groove. A step of forming an upper gate electrode made of copper in the groove through the first and second barrier films so that the bottom surface and both side surfaces of the upper gate electrode are covered with the first and second barrier films. When at least a step of forming a third barrier film that prevents diffusion of copper so as to cover the exposed upper surface of the upper gate electrode, in addition, game
After the upper surface of the electrode is exposed and the groove is formed, the first high melting point
A step of forming a metal film, and forming a metal film on the first refractory metal film.
A step of forming a nitride film of a refractory metal and the refractory metal
Forming a second refractory metal film on the nitride film of
And the copper in the area other than the groove and the first high melting point gold
Removal of metal film, refractory metal nitride film, and second refractory metal film
And an upper gate electrode made of copper and a first refractory metal film,
A first refractory metal nitride film and a second refractory metal film
And the steps of forming the second barrier film and
Was equipped so that even without.

Further, in the present invention, a step of forming a gate insulating film on a silicon substrate, a step of forming a lower gate electrode made of silicon on the gate insulating film, and an etching stopper layer on the lower gate electrode. A step of forming a sacrificial pattern on the etching stopper layer, a step of forming a source / drain by introducing an impurity into a predetermined amount region of the silicon substrate using the lower gate electrode and the sacrificial pattern as a mask, a lower gate electrode And a step of forming a first interlayer insulating film made of silicon oxide on the silicon substrate so as to cover the sacrificial pattern;
Selectively removing the interlayer insulating film to expose the upper surface of the sacrificial pattern to form a groove above the lower gate electrode,
Selectively removing the sacrificial pattern to expose the upper surface of the etching stopper layer, removing the etching stopper layer to expose the upper surface of the lower gate electrode, and diffusing copper so as to cover the upper surface of the lower gate electrode and the side surface of the groove. Forming a first and a second barrier film having conductivity for preventing the above, and forming an upper gate electrode made of copper in the groove through the first and second barrier films to form a bottom surface of the upper gate electrode. And a step of making both side surfaces covered with the first and second barrier films, and a step of forming a third barrier film for blocking the diffusion of copper so as to cover the exposed upper surface of the upper gate electrode. And at least.

Since it is manufactured as described above, the upper gate electrode is manufactured in a state of being in contact with other portions constituting the field effect transistor through the first to third barrier films. That is, the diffusion of copper from the upper gate electrode can be blocked in all directions. As a result, the present invention has an extremely excellent effect that copper can be used as the material of the gate electrode of the field effect transistor without deteriorating the characteristics of the transistor. Also, since the upper gate electrode made of copper is formed after forming the source / drain, after the high temperature activation heat treatment for forming the source / drain,
The upper gate electrode will be formed. As a result, the upper gate electrode can be formed by using copper whose melting point is not so high.

Further, according to the present invention, a step of forming a gate insulating film on a silicon substrate, a step of forming a lower gate electrode made of silicon on the gate insulating film, and a step of forming a sacrificial pattern on the lower gate electrode. And a step of forming a source / drain by introducing impurities into a predetermined amount region of the silicon substrate using the lower gate electrode and the sacrificial pattern as a mask, and insulation for preventing diffusion of copper on both sides of the lower gate electrode and the sacrificial pattern. A step of forming a side wall made of a material, a step of forming a first interlayer insulating film made of silicon oxide on the silicon substrate so as to cover the lower gate electrode and the sacrificial pattern, and removing the first interlayer insulating film. Exposing the upper surface of the sacrificial pattern, selectively removing the sacrificial pattern to form a groove above the lower gate electrode, and Forming a first barrier film having conductivity so as to cover the upper surface of the gate electrode and prevent the diffusion of copper so that both ends contact the side wall; and an upper part made of copper through the first barrier film in the groove. The step of forming the gate electrode so that the bottom surface of the upper gate electrode is covered with the first barrier film and the both side surfaces are covered with the second barrier film having side walls, and the upper gate electrode is exposed. A step of forming a third barrier film for blocking the diffusion of copper so as to block the upper surface, and in addition, a film of a refractory metal in contact with the lower gate electrode
And a heat treatment to contact the lower gate electrode
The refractory metal film is silicided to contact the lower gate electrode.
To form a silicide film of a refractory metal to form a first barrier
Was so that comprising the step of the part of the film.

Further, in the present invention, a step of forming a gate insulating film on a silicon substrate, a step of forming a lower gate electrode made of silicon on the gate insulating film, and an etching stopper layer on the lower gate electrode. A step of forming a sacrificial pattern on the etching stopper layer, a step of forming a source / drain by introducing an impurity into a predetermined amount region of the silicon substrate using the lower gate electrode and the sacrificial pattern as a mask, a lower gate electrode , A step of forming sidewalls made of an insulating material that prevents diffusion of copper on both sides of the etching stopper layer and the sacrificial pattern, and on the silicon substrate so as to cover the lower gate electrode, the etching stopper layer, and the sacrificial pattern. A step of forming a first interlayer insulating film made of silicon oxide,
A step of removing the first interlayer insulating film to expose the upper surface of the sacrificial pattern; a step of selectively removing the sacrificial pattern to expose the upper surface of the etching stopper layer; A step of forming a groove in the groove, a step of forming a first barrier film having conductivity, which is in close contact with the lower gate electrode and covers the upper surface, and prevents the diffusion of copper so that both ends contact the side wall, A state in which an upper gate electrode made of copper is formed through the first barrier film, the bottom surface of the upper gate electrode is covered with the first barrier film, and both side surfaces are covered with the second barrier film having side walls And a step of forming a third barrier film that blocks the diffusion of copper so as to cover the exposed upper surface of the upper gate electrode.

Further, in the present invention, a step of forming a gate insulating film on a silicon substrate, a step of forming a lower gate electrode made of silicon on the gate insulating film, and forming an etching stopper layer on the lower gate electrode. A step of forming a sacrificial pattern on the etching stopper layer, a step of forming a source / drain by introducing an impurity into a predetermined amount region of the silicon substrate using the lower gate electrode and the sacrificial pattern as a mask, a lower gate electrode , A step of forming sidewalls made of an insulating material that prevents diffusion of copper on both sides of the etching stopper layer and the sacrificial pattern, and on the silicon substrate so as to cover the lower gate electrode, the etching stopper layer, and the sacrificial pattern. A step of forming a first interlayer insulating film made of silicon oxide,
A step of selectively removing the first interlayer insulating film to expose the upper surface of the sacrificial pattern to form a groove above the lower gate electrode; and a step of selectively removing the sacrificial pattern to expose the upper surface of the etching stopper layer. A step of removing the etching stopper layer, and a step of forming a conductive first barrier film that adheres to the lower gate electrode, covers the upper surface, and blocks the diffusion of copper so that both ends contact the sidewalls, An upper gate electrode made of copper is formed in the groove through a first barrier film, the bottom surface of the upper gate electrode is covered with the first barrier film, and both side surfaces are covered with the second barrier film having side walls. At least a step of forming a state and a step of forming a third barrier film that blocks the diffusion of copper so as to block the exposed upper surface of the upper gate electrode are provided.

Since it is manufactured as described above, the upper gate electrode is manufactured in a state of being in contact with many parts constituting the field effect transistor through the first to third barrier films. That is, the diffusion of copper from the upper gate electrode can be blocked in all directions. As a result, the present invention has an extremely excellent effect that copper can be used as the material of the gate electrode of the field effect transistor without deteriorating the characteristics of the transistor. Further, since the second barrier film is also used as the side wall, the process can be simplified. Further, since the upper gate electrode made of copper is formed after forming the source / drain, the upper gate electrode is formed after the high temperature activation heat treatment for forming the source / drain. As a result, the upper gate electrode can be formed by using copper whose melting point is not so high.

[Brief description of drawings]

FIG. 1 is a sectional view schematically showing a configuration of a field effect transistor according to a first embodiment of the present invention.

FIG. 2 is a process diagram for explaining the manufacturing method of the field-effect transistor in the first embodiment.

FIG. 3 is a process diagram for explaining the manufacturing method of the field effect transistor according to the first embodiment, which is subsequent to FIG. 2;

FIG. 4 is a process diagram following the process of FIG. 3 for explaining the method for manufacturing the field effect transistor according to the first embodiment.

FIG. 5 is a process diagram for explaining the method of manufacturing the field effect transistor according to the first embodiment, which is subsequent to FIG. 4;

FIG. 6 is a process chart for explaining the manufacturing method of the field-effect transistor in the second embodiment of the present invention.

FIG. 7 is a process chart for explaining the method for manufacturing the field effect transistor according to the second embodiment, which is subsequent to FIG. 6;

FIG. 8 is a process diagram following the process of FIG. 7 for explaining the method for manufacturing the field effect transistor according to the second embodiment.

FIG. 9 is a process diagram following the process in FIG. 8 for explaining the method for manufacturing the field effect transistor according to the second embodiment.

FIG. 10 is a process drawing for explaining a manufacturing method of a field effect transistor according to another embodiment of the present invention.

FIG. 11 is a process diagram that follows FIG. 10 and is for explaining a method for manufacturing a field effect transistor according to another embodiment of the present invention.

FIG. 12 is a process drawing for explaining a manufacturing method of a field effect transistor according to another embodiment of the present invention.

FIG. 13 is a process diagram for explaining the method for manufacturing the field effect transistor according to another embodiment of the present invention, which is subsequent to FIG.

FIG. 14 is a cross-sectional view showing the structure of a conventional field effect transistor.

[Explanation of symbols]

101 ... Silicon substrate, 102 ... Gate insulating film, 103
... Lower gate electrode, 104 ... Upper gate electrode, 105 ...
Barrier film (first and second barrier film), 106 ... Barrier film (third barrier film), 107 ... Side wall, 108
... low-concentration impurity region, 109 ... source, 110 ... drain.

─────────────────────────────────────────────────── --- Continuation of the front page (56) References JP-A-10-294462 (JP, A) JP-A-7-115196 (JP, A) JP-A-7-273326 (JP, A) JP-A-11- 87701 (JP, A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 29/78 H01L 21/336 H01L 21/28 H01L 21/44 H01L 29/40-29/43 H01L 29/872

Claims (31)

(57) [Claims] 1. A lower gate electrode made of silicon formed on a silicon substrate via a gate insulating film, an upper gate electrode made of copper formed on the lower gate electrode, and a channel portion on the lower gate electrode. A first barrier film which has conductivity so that a sufficient current can be injected to prevent the diffusion of copper and is formed so as to cover the lower surface of the upper gate electrode, and the lower end contacts the first barrier film. And a second barrier film formed to cover both side surfaces of the upper gate electrode to prevent diffusion of copper, and an end portion of the second barrier film contacts the upper surface of the upper gate electrode. Third to prevent the diffusion of copper formed on the surface
And a source / drain formed on the silicon substrate so as to sandwich the region under the lower gate electrode, the first barrier film has a lowermost layer of a metal silicide layer or a refractory metal metal and silicon. and is composed of a layer made of a compound of nitrogen, a layer of refractory metal nitride is disposed on a layer made of a compound of the layer or refractory metal metal, silicon and nitrogen of the metal silicide, is the top layer A field effect transistor, which is a multi-layer film composed of a refractory metal. 2. A lower gate electrode made of silicon formed on a silicon substrate via a gate insulating film, an upper gate electrode made of copper formed on the lower gate electrode, and a channel portion on the lower gate electrode. A first barrier film which has conductivity so that a sufficient current can be injected to prevent the diffusion of copper and is formed so as to cover the lower surface of the upper gate electrode, and a lower end contacts the first barrier film. And a second barrier film formed to cover both side surfaces of the upper gate electrode to prevent diffusion of copper, and an end portion of the second barrier film contacts the upper surface of the upper gate electrode. Third to prevent the diffusion of copper formed on the surface
And a source / drain formed on the silicon substrate so as to sandwich the region below the lower gate electrode, the first barrier film has a bottom layer of a metal silicide layer or a refractory metal metal and silicon. And a layer of a compound of nitrogen and a metal silicide layer or a layer of a compound of refractory metal metal and silicon and nitrogen, and a layer of a refractory metal nitride is disposed on the uppermost layer. A multi-layer film made of a refractory metal, which has sidewalls formed on the side surfaces of the lower gate electrode and the upper gate electrode, and a part of the sidewalls constitutes the second barrier film. A field-effect transistor characterized by being present. 3. A lower gate electrode made of silicon formed on a silicon substrate via a gate insulating film, an upper gate electrode made of copper formed on the lower gate electrode, and a channel portion on the lower gate electrode. A first barrier film which has conductivity so that a sufficient current can be injected to prevent the diffusion of copper and is formed so as to cover the lower surface of the upper gate electrode, and a lower end of the first barrier film contacts the first barrier film. And a second barrier film formed to cover both side surfaces of the upper gate electrode to prevent diffusion of copper, and an end portion of the second barrier film contacts the upper surface of the upper gate electrode. And a source / drain formed on the silicon substrate so as to interpose a region under the lower gate electrode, the third barrier film being formed of an insulating material that prevents copper from diffusing. In the barrier film No. 1, the lowermost layer is composed of a metal silicide layer or a layer made of a compound of refractory metal metal and silicon and nitrogen. This barrier film is made of a metal silicide layer or a compound of refractory metal metal, silicon and nitrogen. A field-effect transistor, wherein a layer of a refractory metal nitride is disposed on the layer , and the uppermost layer is a multilayer film made of a refractory metal. 4. A lower gate electrode made of silicon formed on a silicon substrate via a gate insulating film, an upper gate electrode made of copper formed on the lower gate electrode, and a channel portion on the lower gate electrode. A first barrier film which has conductivity so that a sufficient current can be injected to prevent the diffusion of copper and is formed so as to cover the lower surface of the upper gate electrode, and a lower end of the first barrier film contacts the first barrier film. And a second barrier film formed to cover both side surfaces of the upper gate electrode to prevent diffusion of copper, and an end portion of the second barrier film contacts the upper surface of the upper gate electrode. And a source / drain formed on the silicon substrate so as to interpose a region under the lower gate electrode, the third barrier film being formed of an insulating material that prevents copper from diffusing. In the barrier film No. 1, the lowermost layer is composed of a metal silicide layer or a layer made of a compound of refractory metal metal and silicon and nitrogen. This barrier film is made of a metal silicide layer or a compound of refractory metal metal, silicon and nitrogen. A layer of a refractory metal nitride is disposed on the layer , the uppermost layer is a multilayer film composed of a refractory metal, and the upper surface of the upper gate electrode is opened to form a layer on the silicon substrate. A field effect transistor comprising an insulating layer formed, wherein the third barrier film is formed to extend on the insulating layer. 5. A lower gate electrode made of silicon formed on a silicon substrate via a gate insulating film, an upper gate electrode made of copper formed on the lower gate electrode, and a channel portion on the lower gate electrode. A first barrier film which has conductivity so that a sufficient current can be injected to prevent the diffusion of copper and is formed so as to cover the lower surface of the upper gate electrode, and a lower end of the first barrier film contacts the first barrier film. And a second barrier film formed to cover both side surfaces of the upper gate electrode to prevent diffusion of copper, and an end portion of the second barrier film contacts the upper surface of the upper gate electrode. Third to prevent the diffusion of copper formed on the surface
And a source / drain formed on the silicon substrate so as to sandwich the region below the lower gate electrode, the first barrier film has a bottom layer of a metal silicide layer or a refractory metal metal and silicon. And a layer of a compound of nitrogen and a metal silicide layer or a layer of a compound of refractory metal metal and silicon and nitrogen, and a layer of a refractory metal nitride is disposed on the uppermost layer. An electric field, wherein the second barrier film and the third barrier film are multilayer films made of a refractory metal, and the second barrier film and the third barrier film are made of a refractory metal or a nitride of a refractory metal. Effect transistor. 6. A lower gate electrode made of silicon formed on a silicon substrate via a gate insulating film, an upper gate electrode made of copper formed on the lower gate electrode, and a channel portion on the lower gate electrode. A first barrier film which has conductivity so that a sufficient current can be injected to prevent the diffusion of copper and is formed so as to cover the lower surface of the upper gate electrode, and a lower end of the first barrier film contacts the first barrier film. And a second barrier film formed to cover both side surfaces of the upper gate electrode to prevent diffusion of copper, and an end portion of the second barrier film contacts the upper surface of the upper gate electrode. A third barrier film made of silicon nitride or boron nitride, which prevents the diffusion of copper formed on the silicon substrate, and formed on the silicon substrate so as to sandwich the region under the lower gate electrode. The first barrier film of the first barrier film is composed of a metal silicide layer or a layer made of a compound of refractory metal metal and silicon and nitrogen. The metal silicide layer or refractory metal a layer of refractory metal nitride is disposed on a layer made of a compound of metal and silicon and nitrogen, the field effect transistor, characterized in that the top layer is a multilayer film composed of a refractory metal. 7. A gate insulating film is formed on a silicon substrate.
And a lower gate electrode made of silicon on the gate insulating film
And a step of forming an etching stopper layer on the lower gate electrode
And a sacrificial pattern is formed on the etching stopper layer.
And a step of masking the lower gate electrode and the sacrificial pattern.
To introduce impurities into a predetermined amount region of the silicon substrate.
And a step of forming source / drain, and so as to cover the lower gate electrode and the sacrificial pattern.
A first layer of silicon oxide on the silicon substrate
A step of forming an interlayer insulating film, removing the first interlayer insulating film, and removing the sacrificial pattern;
Exposing the surface, and selectively removing the sacrificial pattern to remove the etching pattern.
Exposing the upper surface of the topper layer and removing the etching stopper layer to remove the lower gate
Exposing the upper surface of the electrode to form a groove above the lower gate electrode
A step of, so as to cover the side surfaces of the lower gate electrode upper surface and the groove
The first barrier film and the conductive first barrier film that prevent the diffusion of copper.
And a step of forming a second barrier film, and the step of forming the first barrier film and the second barrier film inside the groove.
Before forming the upper gate electrode made of copper through the rear film
The bottom surface and both side surfaces of the upper gate electrode are the first burrs.
(A) A step of covering with the film and the second barrier film
And copper to cover the exposed upper surface of the upper gate electrode.
And forming a third barrier film that prevents diffusion little of
Field effect transistor characterized by having at least
Manufacturing method . 8. A gate insulating film is formed on a silicon substrate.
And a lower gate electrode made of silicon on the gate insulating film
And a step of forming an etching stopper layer on the lower gate electrode
And a sacrificial pattern is formed on the etching stopper layer.
And a step of masking the lower gate electrode and the sacrificial pattern.
To introduce impurities into a predetermined amount region of the silicon substrate.
And a step of forming source / drain, and so as to cover the lower gate electrode and the sacrificial pattern.
A first layer of silicon oxide on the silicon substrate
A step of forming an interlayer insulating film, and the sacrificial pattern by selectively removing the first interlayer insulating film.
Exposing the upper surface of the gate to form a groove above the lower gate electrode.
And a step of selectively removing the sacrificial pattern to form the etching pattern.
Exposing a topper layer top surface, said lower gate and removing the etching stopper layer
Exposing the upper surface of the electrode, and covering the upper surface of the lower gate electrode and the side surface of the groove.
The first barrier film and the conductive first barrier film that prevent the diffusion of copper.
And a step of forming a second barrier film, and the step of forming the first barrier film and the second barrier film inside the groove.
Before forming the upper gate electrode made of copper through the rear film
The bottom surface and both side surfaces of the upper gate electrode are the first burrs.
(A) A step of covering with the film and the second barrier film
And copper to cover the exposed upper surface of the upper gate electrode.
And forming a third barrier film that prevents diffusion little of
Field effect transistor characterized by having at least
Manufacturing method . 9. The field effect transistor according to claim 7 or 8.
In the method of manufacturing a transistor, the sacrificial pattern is exposed to a predetermined etching treatment condition.
The material that etches faster than silicon oxide.
Of manufacturing a field effect transistor characterized by
Law . 10. The method according to any one of claims 7 to 9.
In the method for manufacturing a field effect transistor, the sacrificial pattern, the etching stopper layer, the lower gate, and the like.
Characterized in that the electrode is processed with a hard mask
Method for manufacturing field effect transistor . 11. The field effect transistor according to claim 7 or 8.
In the method of manufacturing a transistor, the sacrificial pattern, the etching stopper layer, the lower gate, and the like.
The cathode electrode is made of silicon oxide or silicon nitride.
Field effect transistor characterized by being processed by a mask
Method of manufacturing a register . 12. The method according to any one of claims 7 to 11.
In the method for manufacturing a field effect transistor of , after the upper surface of the lower gate electrode is exposed and a groove is formed,
A process of forming a refractory metal film and a process of forming a refractory metal nitride film on the refractory metal film.
The step of depositing copper , the copper in the region other than the groove, the refractory metal film, the high
The upper gate made of copper is formed by removing the nitride film of the melting point metal.
From the electrode, the refractory metal film and the nitride film of the refractory metal
For forming the first barrier film and the second barrier film
Field effect tiger, characterized in that a degree of at least
Method of manufacturing a register . 13. The method according to any one of claims 7 to 11.
In the method for manufacturing a field effect transistor of , after the upper surface of the lower gate electrode is exposed and a groove is formed,
Forming a first refractory metal film, and forming a refractory metal nitride film on the first refractory metal film
And the step of forming a second refractory metal film on the refractory metal nitride film.
The step of forming a copper film , the copper in the region other than the groove, the first refractory metal film,
The refractory metal nitride film and the second refractory metal film are removed.
And the upper gate electrode made of copper and the first high melting point
Point metal film, high melting point metal nitride film, second high melting point film
The first barrier film and the second barrier film made of a metal film
Electrodeposition, characterized in that the step comprising at least forming
Method for manufacturing field effect transistor . 14. The method according to any one of claims 7 to 11.
In the method for manufacturing a field effect transistor of , after the upper surface of the lower gate electrode is exposed and a groove is formed,
A compound composed of a refractory metal, a compound of silicon and nitrogen
Step of forming film and step of forming nitride film of refractory metal on this compound film
And a step of forming a copper film to be the upper gate electrode, the copper in the region other than the groove, the compound film, the high melting point
The upper gate electrode made of copper is formed by removing the metal nitride film.
And a compound film and a nitride film of the refractory metal
And a step less to form a barrier film and the second barrier film
Field effect transistor characterized by having at least
Manufacturing method . 15. The method according to any one of claims 7 to 11.
In field effect transistors manufacturing method, after the lower gate electrode upper surface is exposed, a groove is formed,
A compound composed of a refractory metal, a compound of silicon and nitrogen
Step of forming film and step of forming nitride film of refractory metal on this compound film
And a process of forming a refractory metal film on this refractory metal nitride film.
The step of depositing copper to be the upper gate electrode, the copper in the region other than the groove, the compound film, and the high melting point.
The metal nitride film and the refractory metal film are removed, and the copper is removed.
Of the upper gate electrode, the compound film, and the refractory metal
A nitride film, a first barrier film composed of the refractory metal film, and
And a step of forming a second barrier film, and a method of manufacturing a field effect transistor. 16. The method for manufacturing a field effect transistor according to claim 12 , wherein a refractory metal film is formed in contact with the lower gate electrode.
Process and heat treatment to form a refractory metal film in contact with the lower gate electrode
Is silicided to contact the lower gate electrode and has a high melting point.
A metal silicide film is formed to form one of the first barrier film.
Method of manufacturing a field effect transistor, characterized in that the step with at least a part. 17. A step of forming a gate insulating film on a silicon substrate, a step of forming a lower gate electrode made of silicon on the gate insulating film, and a step of forming a sacrificial pattern on the lower gate electrode.
When a step of forming the source and drain by introducing impurities into predetermined weight region of said silicon substrate to the lower gate electrode and the sacrificial pattern as a mask, on both side surfaces of the lower gate electrode and the sacrificial pattern
A step of forming a side wall made of an insulating material that prevents diffusion of copper, and a step of forming a first interlayer insulating film made of silicon oxide on the silicon substrate so as to cover the lower gate electrode and the sacrificial pattern. Removing the first interlayer insulating film to expose the upper surface of the sacrificial pattern, and selectively removing the sacrificial pattern to remove the lower gate electrode.
Forming a groove in the uppermost portion, and covering the upper surface of the lower gate electrode so that both ends are in contact with the sidewall.
Forming a first burr <br/> A film having conductivity that prevents the diffusion of copper so that the upper gate electrode made of copper through the first barrier film inside the groove formed a bottom surface of the upper gate electrode is covered with <br/> the first barrier film ne from both sides said side walls
That a step of the covered state to the second barrier film, comprising at least a step of forming a third barrier film that prevents diffusion of copper so as to close the exposed portion of the upper surface of the upper gate electrode, In addition, a film of refractory metal is formed in contact with the lower gate electrode.
Process and heat treatment to form a refractory metal film in contact with the lower gate electrode
Is silicided to contact the lower gate electrode and has a high melting point.
A metal silicide film is formed to form one of the first barrier film.
And a step of forming a part . 18. A step of forming a gate insulating film on a silicon substrate, a step of forming a lower gate electrode made of silicon on the gate insulating film, and a step of forming an etching stopper layer on the lower gate electrode. Forming a sacrificial pattern on the etching stopper layer; forming a source / drain by introducing an impurity into a predetermined amount region of the silicon substrate using the lower gate electrode and the sacrificial pattern as a mask; Lower gate electrode , the etching stopper layer,
And prevent copper diffusion on both sides of the sacrificial pattern
Forming a side wall made of an insulating material, the lower gate electrode, the etching stopper layer, and
And exposes a step of forming a first interlayer insulating film made of silicon oxide on the silicon substrate so as to cover the sacrificial pattern, the upper surface of the sacrificial pattern by removing the first interlayer insulating film and as that engineering, thereby exposing the etching stopper layer upper surface by selectively removing the sacrificial pattern, the steps that form a groove on the lower gate electrode upper and removing the etching stopper layer, the lower Adheres closely to the gate electrode and covers the upper surface, and both ends are on the above side.
Forming a step of forming a first barrier film having conductivity that prevents the diffusion of copper to contact the wall, an upper gate electrode made of copper through the first barrier film inside the groove sides the bottom surface of the upper gate electrode is covered with <br/> the first barrier film Te ne from said side wall
A step of the second barrier film covered state that, with at least a step of forming a third barrier film that prevents diffusion of copper so as to close the exposed portion of the upper surface of the upper gate electrode A method for manufacturing a field effect transistor, comprising: 19. A gate insulating film is formed on a silicon substrate.
And a lower gate electrode made of silicon on the gate insulating film
And a step of forming an etching stopper layer on the lower gate electrode
And a sacrificial pattern is formed on the etching stopper layer.
And a step of masking the lower gate electrode and the sacrificial pattern.
To introduce impurities into a predetermined amount region of the silicon substrate.
And a step of forming source / drain, the lower gate electrode, the etching stopper layer, and
And prevent copper diffusion on both sides of the sacrificial pattern
Forming a side wall made of an insulating material, the lower gate electrode, the etching stopper layer, and
And the silicon substrate so as to cover the sacrificial pattern
First interlayer insulating film made of silicon oxide is formed on
And the sacrificial pattern by selectively removing the first interlayer insulating film.
Exposing the upper surface of the gate to form a groove above the lower gate electrode.
And a step of selectively removing the sacrificial pattern to form the etching pattern.
Exposing a topper layer top surface, removing the etching stopper layer, both ends cover the upper surface in close contact with the lower gate electrode is the side
Has conductivity that prevents the diffusion of copper to contact the wall
Forming a first barrier film, and comprising copper inside the groove via the first barrier film
Forming a top gate electrode so that the bottom surface of the top gate electrode is
Both side surfaces are covered with the first barrier film and are not formed from the side walls.
Covering the exposed upper surface of the upper gate electrode with copper so as to cover the exposed upper surface of the upper gate electrode.
And forming a third barrier film that prevents diffusion little of
A method for manufacturing a field effect transistor, which is characterized by having at least one. 20. The method for manufacturing a field effect transistor according to claim 18 , wherein the sacrificial pattern, the etching stopper layer, and the lower gate.
A method of manufacturing a field-effect transistor, characterized in that the gate electrode is processed by a hard mask . 21. The method of manufacturing a field effect transistor according to claim 18 , wherein the sacrificial pattern, the etching stopper layer, and the lower gate electrode are processed by a hard mask made of silicon oxide or silicon nitride. Of manufacturing a field effect transistor having the same. 22. A manufacturing method of a field effect transistor according to any one of claims 1 8-21, forming a refractory metal film in contact with the lower gate electrode
Process and heat treatment to form a refractory metal film in contact with the lower gate electrode
Is silicided to contact the lower gate electrode and has a high melting point.
A metal silicide film is formed to form one of the first barrier film.
And a step of forming a part . 23. The method for manufacturing a field effect transistor according to claim 18 , wherein a refractory metal film is formed in contact with the lower gate electrode.
And extent, refractory metal nitride heat treatment to contact with the lower gate electrode
Reacting the film with silicon to contact the lower gate electrode
Form a compound film of refractory metal, silicon and nitrogen,
A step of forming a part of the first barrier film, and a method for manufacturing a field effect transistor. 24. Forming a gate insulating film on a silicon substrate
And a lower gate electrode made of silicon on the gate insulating film
And a step of forming a sacrificial pattern on the lower gate electrode
And a mask for the lower gate electrode and the sacrificial pattern.
To introduce impurities into a predetermined amount region of the silicon substrate.
And a step of forming source / drain, and so as to cover the lower gate electrode and the sacrificial pattern.
A first layer of silicon oxide on the silicon substrate
A step of forming an interlayer insulating film, removing the first interlayer insulating film, and removing the sacrificial pattern;
Exposing the surface and selectively removing the sacrificial pattern to remove the lower gate electrode.
The upper surface is exposed to expose the lower gate of the first interlayer insulating film.
Forming a groove above the gate electrode and covering the upper surface of the lower gate electrode and the side surface of the groove.
The first barrier film and the conductive first barrier film that prevent the diffusion of copper.
And a step of forming a second barrier film, and the step of forming the first barrier film and the second barrier film inside the groove.
Before forming the upper gate electrode made of copper through the rear film
The bottom surface and both side surfaces of the upper gate electrode are the first burrs.
(A) A step of covering with the film and the second barrier film
And copper to cover the exposed upper surface of the upper gate electrode.
And forming a third barrier film that prevents diffusion little of
In addition to the above , in addition to exposing the upper surface of the gate electrode and forming a groove,
And forming a refractory metal nitride film on the first refractory metal film.
And the step of forming a second refractory metal film on the refractory metal nitride film.
The step of forming a copper film , the copper in the region other than the groove, the first refractory metal film,
The refractory metal nitride film and the second refractory metal film are removed.
And the upper gate electrode made of copper and the first high melting point
Point metal film, high melting point metal nitride film, second high melting point film
The first barrier film and the second barrier film made of a metal film
And a step of forming the field effect transistor. 25. A gate insulating film is formed on a silicon substrate.
And a lower gate electrode made of silicon on the gate insulating film
And a step of forming a sacrificial pattern on the lower gate electrode
And a mask for the lower gate electrode and the sacrificial pattern.
To introduce impurities into a predetermined amount region of the silicon substrate.
And a step of forming source / drain, and so as to cover the lower gate electrode and the sacrificial pattern.
A first layer of silicon oxide on the silicon substrate
A step of forming an interlayer insulating film, removing the first interlayer insulating film, and removing the sacrificial pattern;
Exposing the surface and selectively removing the sacrificial pattern to remove the lower gate electrode.
The upper surface is exposed to expose the lower gate of the first interlayer insulating film.
Forming a groove above the gate electrode and covering the upper surface of the lower gate electrode and the side surface of the groove.
The first barrier film and the conductive first barrier film that prevent the diffusion of copper.
And a step of forming a second barrier film, and the step of forming the first barrier film and the second barrier film inside the groove.
Before forming the upper gate electrode made of copper through the rear film
The bottom surface and both side surfaces of the upper gate electrode are the first burrs.
(A) A step of covering with the film and the second barrier film
And copper to cover the exposed upper surface of the upper gate electrode.
And forming a third barrier film that prevents diffusion little of
In addition to the above , in addition, after the upper surface of the lower gate electrode is exposed and a groove is formed,
A compound composed of a refractory metal, a compound of silicon and nitrogen
Step of forming film and step of forming nitride film of refractory metal on this compound film
And a step of forming a copper film to be the upper gate electrode, the copper in the region other than the groove, the compound film, the high melting point
The upper gate electrode made of copper is formed by removing the metal nitride film.
And a compound film and a nitride film of the refractory metal
And at least a step of forming a barrier film and a second barrier film . 26. Forming a gate insulating film on a silicon substrate
And a lower gate electrode made of silicon on the gate insulating film
And a step of forming a sacrificial pattern on the lower gate electrode
And a mask for the lower gate electrode and the sacrificial pattern.
To introduce impurities into a predetermined amount region of the silicon substrate.
And a step of forming source / drain, and so as to cover the lower gate electrode and the sacrificial pattern.
A first layer of silicon oxide on the silicon substrate
A step of forming an interlayer insulating film, removing the first interlayer insulating film, and removing the sacrificial pattern;
Exposing the surface and selectively removing the sacrificial pattern to remove the lower gate electrode.
The upper surface is exposed to expose the lower gate of the first interlayer insulating film.
Forming a groove above the gate electrode and covering the upper surface of the lower gate electrode and the side surface of the groove.
The first barrier film and the conductive first barrier film that prevent the diffusion of copper.
And a step of forming a second barrier film, and the step of forming the first barrier film and the second barrier film inside the groove.
Before forming the upper gate electrode made of copper through the rear film
The bottom surface and both side surfaces of the upper gate electrode are the first burrs.
(A) A step of covering with the film and the second barrier film
And copper to cover the exposed upper surface of the upper gate electrode.
And forming a third barrier film that prevents diffusion little of
In addition to the above , in addition, after the upper surface of the lower gate electrode is exposed and a groove is formed,
A compound composed of a refractory metal, a compound of silicon and nitrogen
Step of forming film and step of forming nitride film of refractory metal on this compound film
And a process of forming a refractory metal film on this refractory metal nitride film.
The step of depositing copper to be the upper gate electrode, the copper in the region other than the groove, the compound film, and the high melting point.
The metal nitride film and the refractory metal film are removed, and the copper is removed.
Of the upper gate electrode, the compound film, and the refractory metal
A nitride film, a first barrier film composed of the refractory metal film, and
And a step of forming a second barrier film, and a method of manufacturing a field effect transistor. 27. A step of forming a gate insulating film on a silicon substrate, a step of forming a lower gate electrode made of silicon on the gate insulating film, and a step of forming a sacrificial pattern on the lower gate electrode. said silicon substrate so as to cover the step, the pre-Symbol lower gate electrode and the sacrificial pattern to form the source and drain by introducing impurities into predetermined weight region of said silicon substrate to the lower gate electrode and the sacrificial pattern as a mask Forming a first interlayer insulating film made of silicon oxide on the upper surface, removing the first interlayer insulating film to expose an upper surface of the sacrificial pattern, and selectively removing the sacrificial pattern. the lower gate of said exposed first interlayer insulating film using the lower gate electrode upper surface Te
Forming a groove in the upper portion over gate electrode, a first barrier film having conductivity that prevents the diffusion of copper sides of the covering Migihitsuji <br/> of the lower gate electrode upper surface and the groove Contact
And a step of forming a second barrier film, and the step of forming the first barrier film and the second barrier film inside the groove.
Forming an upper gate electrode made of copper via a rear film so that a bottom surface and both side surfaces of the upper gate electrode are covered with the first barrier film and the second barrier film; At least forming a third barrier film that blocks the diffusion of copper so as to cover the exposed upper surface of the electrode , and in addition, after the upper surface of the lower gate electrode is exposed and a groove is formed,
A process of forming a refractory metal film and a process of forming a refractory metal nitride film on the refractory metal film.
The step of depositing copper , the copper in the region other than the groove, the refractory metal film, the high
The upper gate made of copper is formed by removing the nitride film of the melting point metal.
From the electrode, the refractory metal film and the nitride film of the refractory metal
For forming the first barrier film and the second barrier film
Then, a film of refractory metal is formed in contact with the lower gate electrode.
Process and heat treatment to form a refractory metal film in contact with the lower gate electrode
Is silicided to contact the lower gate electrode and has a high melting point.
A metal silicide film is formed to form one of the first barrier film.
And a step of forming a part . 28. The method according to any one of claims 17 to 19.
2. The method for manufacturing a field effect transistor according to claim 1, wherein the sidewall is made of silicon nitride . 29. The battery according to any one of claims 7 to 11.
In the method of manufacturing a field effect transistor, the first barrier film is formed on the upper surface of the lower gate electrode by tunneling.
A field effect transistor is manufactured by nitriding to a thickness at which a current flows . 30. A method of manufacturing a field effect transistor according to any one of claims 7 to 29, the first or second barrier layer is vertical with respect to the bottom surface of the groove
Increase the number of particles that are incident at a normal or near-normal angle.
A method of manufacturing a field effect transistor, characterized in that the film is formed by the above method. 31. A manufacturing method of a field effect transistor according to any one of claims 7-30, before forming the upper gate electrode, the source-drain
A method of manufacturing a field effect transistor, characterized in that a refractory metal silicide is formed in a predetermined region of the in .