JP2000228523A - Field-effect transistor and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To use copper for the material of a gate electrode without deterioration in characteristics of a transistor, by providing a first, second and third barrier films for an upper gate electrode to prevent diffusion of copper formed to respectively cover the lower, both and upper sides of the gate electrode. SOLUTION: A lower gate electrode 103 comprising polysilicon is provided on a silicon substrate 101 via a gate insulating film 102. An upper gate electrode 104 made of copper is provided on the lower gate electrode 103. Moreover, a barrier film 105 (a first and second barrier films) made of tantalum nitride is formed so as to cover the lower and side faces on the upper gate electrode and a barrier film 106 (a third barrier film) made of silicon nitride is formed to cover the upper face on the upper gate electrode 104. Accordingly, the upper gate electrode 104 is in a state which is covered with the barrier films 105, 106 like a cylinder. Thus, a gate electrode of a transistor is constituted by the lower gate electrode 103 and the upper gate electrode 104.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor provided with a gate electrode having a structure in which silicon and copper are stacked, and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, research on further miniaturization of LSI has been promoted for higher performance and higher integration. Under such circumstances, with miniaturization, lowering the resistance of the gate electrode of the field effect transistor has become indispensable for higher performance. For this reason, the use of a two-layer structure of metal and polysilicon as a gate electrode material has been studied. Therefore, due to the low electrical resistance and the superior workability and chemical stability of gold and silver, etc.
It has been proposed to configure a gate electrode with a layer structure.

[0003] The above-mentioned conventional field-effect transistor will be described. As shown in FIG. 14, a lower gate electrode 1403 made of polysilicon is first provided on a silicon substrate 1401 with a gate insulating film 1402 interposed therebetween. An upper gate electrode 1405 made of copper is provided on the lower gate electrode 1403 with a barrier film 1404 made of titanium nitride or the like interposed therebetween. Further, a barrier film 1406 made of titanium nitride or the like is provided over the upper gate electrode 1405. Then, the lower gate electrode 14
03 and the upper gate electrode 1405 constitute a gate electrode of the transistor.

A sidewall 1407 made of silicon oxide is formed so as to cover the side surface of the gate electrode. Further, a low-concentration impurity region 1408 is formed in the silicon substrate 1401 below the sidewall 1407. Further, a source 1409 and a drain 1410 are formed on the silicon substrate 1401 so as to sandwich the low-concentration impurity region 1408. The gate electrode including the low-concentration impurity region 1408, the source 1409 and the drain 1410, the gate insulating film 1402, and the lower gate electrode 1403 and the upper gate electrode 1405 constitutes an LDD field effect transistor. With this LDD structure, the single channel effect can be suppressed.

[0005] The above transistor is covered with an interlayer insulating film 1411 made of silicon oxide, and a gate electrode wiring 1412 and a source electrode wiring 1413 made of aluminum or the like are formed on the interlayer insulating film 1411. The gate electrode wiring 1412 is connected to the upper gate electrode 1405 via a barrier film 1406 by a plug 1414 in a through hole formed in the interlayer insulating film 1411. The plug 1414 is made of tungsten, and a barrier film 1414a made of titanium nitride or the like is formed on side and bottom surfaces of the plug 1414.

The source electrode wiring 1413 is connected to the source 1409 by a plug 1415 in a contact hole formed in the interlayer insulating film 1411. The plug 1415 is also made of tungsten, and a barrier film 1415a made of titanium nitride or the like is formed on the side and bottom surfaces. Barrier films 1412a and 1413a made of titanium nitride or the like are also formed on the gate electrode wiring 1412 and the source electrode wiring 1413. In addition, the above-described gate electrode wiring 1412
A protective insulating film 1416 is formed over the interlayer insulating film 1411 so as to cover wiring such as the source electrode wiring 1413 and the like.

[0007]

As described above, when the gate electrode is constituted by a two-layer structure of polysilicon and copper for further lowering the resistance, the upper gate electrode 1405 made of copper has a lower surface and an upper surface. And barrier film 1404,1
406 is provided to suppress the diffusion of copper into the lower layer polysilicon and the upper layer wiring metal. However,
Since copper also diffuses in the silicon oxide film, as shown by the arrow line in FIG. 14, copper diffuses in the sidewalls 1407 and the interlayer insulating film 1411 which are silicon oxide.
Then, when copper diffuses in the direction of the silicon substrate 1401,
Problems such as generation of a junction leak current, reduction of the on-state current of the transistor, and fluctuation of the threshold voltage occur. In addition, if copper diffuses in the direction of the upper wiring layer, a problem of generation of a leak current between wirings occurs.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has been made in order to make it possible to use copper as a material of a gate electrode of a field effect transistor without deteriorating the characteristics of the transistor. The purpose is to do.

[0009]

A field effect transistor according to the present invention comprises a lower gate electrode made of silicon formed on a silicon substrate via a gate insulating film, and a copper formed on the lower gate electrode. An upper gate electrode;
A first barrier film for preventing diffusion of copper formed so as to cover the lower surface of the upper gate electrode and to have a conductivity capable of injecting a current sufficient to drive the channel portion into the lower gate electrode;
A second end for preventing diffusion of copper formed so that the lower end contacts the first barrier film and covers both side surfaces of the upper gate electrode.
And a third barrier film for preventing the diffusion of copper formed so as to cover the upper surface of the upper gate electrode by contacting the end with the second barrier film, and a region under the lower gate electrode. And a source / drain formed on the silicon substrate. According to the present invention, the upper gate electrode made of copper is configured so as to be in contact with other parts constituting the field effect transistor via the first, second, and first barrier films.

[0010] In the above invention, a side wall formed on the side surface of the lower gate electrode and the upper gate electrode is provided, and a second barrier film is constituted by a part of the side wall. In the above invention, the third barrier film is made of an insulating material. In the above invention, the semiconductor device includes an insulating layer formed on the silicon substrate by opening the upper surface of the upper gate electrode, and the third barrier film is formed to extend on the insulating layer. In the above invention, the first and second barrier films are made of a refractory metal or a refractory metal nitride. In the above invention, the first
Is composed of an insulating material formed to a thickness through which a tunnel current flows. In the above invention, the first, second, and third barrier films are made of a high melting point metal or a nitride of a high melting point metal. In the above invention,
The barrier film is made of a material not containing oxygen as a constituent. In the above invention, the insulating material is made of one of silicon nitride and boron nitride.

In the above invention, the first barrier film has a thickness of 2
It is a multilayer film composed of a plurality of layers. In the above invention, the first barrier film is made of a layer made of a high melting point metal, a layer made of a high melting point metal silicide, a layer made of a compound of a high melting point metal and silicon and nitrogen, or a nitride of a high melting point metal. A multilayer film in which any one of the layers is combined and a plurality of layers are stacked. In the above invention, the first barrier film is a multilayer film in which the lowermost layer is a metal silicide layer or a layer made of a compound of a refractory metal metal, silicon and nitrogen. In the above invention, the lowermost layer of the first barrier film is formed of a metal silicide layer or a layer made of a compound of a refractory metal metal, silicon, and nitrogen. This is a multilayer film in which a nitride layer of a high melting point metal is disposed on a layer made of a compound with nitrogen. In the above invention, the lowermost layer of the first barrier film is formed of a metal silicide layer or a layer made of a compound of a refractory metal metal, silicon, and nitrogen. A nitride layer of a high melting point metal is disposed on a layer made of a compound with nitrogen, and the uppermost layer is a multilayer film made of a high melting point metal. In the above invention, the refractory metal silicide film is formed in a predetermined region on the source / drain surface.

Further, the method of manufacturing a field effect transistor according to the present invention includes a step of forming a gate insulating film on a silicon substrate, a step of forming a lower gate electrode made of silicon on the gate insulating film, Forming a source / drain by introducing an impurity into a predetermined area of the silicon substrate using the lower gate electrode and the sacrificial pattern as a mask, and forming a sacrificial pattern so as to cover the lower gate electrode and the sacrificial pattern. Forming a first interlayer insulating film made of silicon oxide on the silicon substrate, removing the first interlayer insulating film to expose the upper surface of the sacrificial pattern, and selectively removing the sacrificial pattern Forming a groove above the lower gate electrode in the first interlayer insulating film by exposing the upper surface of the lower gate electrode; Forming a first and second barrier film having conductivity to prevent diffusion of copper so as to cover the side surface; and forming an upper gate electrode made of copper in the groove via the first and second barrier films. Forming a state in which the bottom surface and both side surfaces of the upper gate electrode are covered with the first and second barrier films, and a step of blocking diffusion of copper so as to cover the exposed upper surface of the upper gate electrode. 3) a step of forming a barrier film. According to the present invention, the upper gate electrode is manufactured in a state of being in contact with other parts constituting the field effect transistor via the first to third barrier films. In the above invention, the sacrificial pattern is made of a material that is etched faster than silicon and silicon oxide under predetermined etching processing conditions.

The method of manufacturing a field-effect transistor according to the present invention includes a step of forming a gate insulating film on a silicon substrate, a step of forming a lower gate electrode made of silicon on the gate insulating film, Forming an etching stopper layer, forming a sacrificial pattern on the etching stopper layer, and forming a source / drain by introducing impurities into a predetermined amount region of the silicon substrate using the lower gate electrode and the sacrificial pattern as a mask. Forming a first interlayer insulating film made of silicon oxide on the silicon substrate so as to cover the lower gate electrode and the sacrificial pattern; and removing the first interlayer insulating film to remove the upper surface of the sacrificial pattern. Exposing, exposing the etching stopper layer upper surface by selectively removing the sacrificial pattern, Removing the etching stopper layer and exposing the upper surface of the lower gate electrode to form a groove in the upper portion of the lower gate electrode; and a first conductive film for preventing diffusion of copper so as to cover the upper surface of the lower gate electrode and the groove side surface. And forming a second barrier film, and forming an upper gate electrode made of copper in the trench via the first and second barrier films so that the bottom surface and both side surfaces of the upper gate electrode are the first and second side surfaces. And a step of forming a third barrier film for preventing diffusion of copper so as to cover the exposed upper surface of the upper gate electrode. According to the present invention, the upper gate electrode is manufactured so as to be in contact with many parts constituting the field effect transistor via the first to third barrier films.

The method of manufacturing a field-effect transistor according to the present invention comprises the steps of: forming a gate insulating film on a silicon substrate; forming a lower gate electrode made of silicon on the gate insulating film; Forming an etching stopper layer, forming a sacrificial pattern on the etching stopper layer, and forming a source / drain by introducing impurities into a predetermined amount region of the silicon substrate using the lower gate electrode and the sacrificial pattern as a mask. Forming a first interlayer insulating film made of silicon oxide on the silicon substrate so as to cover the lower gate electrode and the sacrificial pattern; and selectively removing the first interlayer insulating film from the sacrificial pattern. Forming a groove above the lower gate electrode by exposing the upper surface of the substrate, and selectively removing the sacrificial pattern and etching. A step of exposing the upper surface of the stopper layer, a step of exposing the upper surface of the lower gate electrode by removing the etching stopper layer, and a first conductive film for preventing diffusion of copper so as to cover the upper surface of the lower gate electrode and the side surface of the groove. And forming a second barrier film, and forming an upper gate electrode made of copper in the trench via the first and second barrier films so that the bottom surface and both side surfaces of the upper gate electrode are the first and second side surfaces. And a step of forming a third barrier film for preventing diffusion of copper so as to cover the exposed upper surface of the upper gate electrode. According to the present invention, the upper gate electrode is made up of many parts constituting the field effect transistor and the first to first parts.
It is manufactured in a state of being in contact through the third barrier film. In the above invention, the sacrificial pattern is made of a material that is etched faster than silicon oxide under predetermined etching processing conditions.

Further, according to the method of manufacturing a field effect transistor of the present invention, a step of forming a gate insulating film on a silicon substrate; a step of forming a lower gate electrode made of silicon on the gate insulating film; Forming a source / drain by introducing impurities into a predetermined area of the silicon substrate using the lower gate electrode and the sacrificial pattern as a mask; and forming a source / drain on both sides of the lower gate electrode and the sacrificial pattern. Forming a side wall made of an insulating material for preventing diffusion of copper, forming a first interlayer insulating film made of silicon oxide on a silicon substrate so as to cover the lower gate electrode and the sacrificial pattern; Removing the upper surface of the sacrificial pattern by removing the interlayer insulating film, and selectively removing the sacrificial pattern to form the lower gate electrode. Forming a groove in the portion, forming a first barrier film having a conductivity that covers the upper surface of the lower gate electrode and prevents diffusion of copper so that both ends contact the side walls, and a first barrier film in the groove is formed. Forming an upper gate electrode made of copper through the barrier film so that the bottom surface of the upper gate electrode is covered with the first barrier film and both side surfaces are covered with the second barrier film composed of side walls; and Forming a third barrier film for preventing diffusion of copper so as to cover the exposed upper surface of the upper gate electrode. According to the present invention, the upper gate electrode is manufactured so as to be in contact with many parts constituting the field effect transistor via the first to third barrier films. The second barrier film is also used as a side wall.

Further, the method for manufacturing a field effect transistor according to the present invention comprises the steps of forming a gate insulating film on a silicon substrate, forming a lower gate electrode made of silicon on the gate insulating film, Forming an etching stopper layer on the substrate, forming a sacrificial pattern on the etching stopper layer, and forming a source / drain by introducing impurities into a predetermined area of the silicon substrate using the lower gate electrode and the sacrificial pattern as a mask. And a lower gate electrode, an etching stopper layer,
Forming a sidewall made of an insulating material for preventing diffusion of copper on both side surfaces of the sacrificial pattern; and forming a silicon oxide on the silicon substrate so as to cover the lower gate electrode, the etching stopper layer, and the sacrificial pattern. Forming a first interlayer insulating film, removing the first interlayer insulating film to expose the upper surface of the sacrificial pattern, and selectively removing the sacrificial pattern to expose the upper surface of the etching stopper layer. Forming a groove in the upper portion of the lower gate electrode by removing the etching stopper layer, and a first conductive film having a conductive property for preventing diffusion of copper so that the upper surface is covered in close contact with the lower gate electrode and both ends contact the side walls. Forming an upper gate electrode made of copper in the trench with the first barrier film interposed therebetween so that the bottom surface of the upper gate electrode becomes the first barrier film. Second that we have both side surfaces consisting of the side wall
And a step of forming a third barrier film for preventing diffusion of copper so as to cover the exposed upper surface of the upper gate electrode. According to the present invention, the upper gate electrode is manufactured so as to be in contact with many parts constituting the field effect transistor via the first to third barrier films. Also, the second
Barrier film is also used as a side wall.

Further, the method of manufacturing a field effect transistor according to the present invention comprises the steps of forming a gate insulating film on a silicon substrate, forming a lower gate electrode made of silicon on the gate insulating film, Forming an etching stopper layer, forming a sacrificial pattern on the etching stopper layer, and forming a source / drain by introducing impurities into a predetermined amount region of the silicon substrate using the lower gate electrode and the sacrificial pattern as a mask. And a lower gate electrode, an etching stopper layer,
Forming a sidewall made of an insulating material for preventing diffusion of copper on both side surfaces of the sacrificial pattern; and forming a silicon oxide on the silicon substrate so as to cover the lower gate electrode, the etching stopper layer, and the sacrificial pattern. Forming a first interlayer insulating film, selectively removing the first interlayer insulating film to expose the upper surface of the sacrificial pattern and forming a groove above the lower gate electrode, and selectively forming the sacrificial pattern. Removing the etching stopper layer, removing the etching stopper layer, and removing the etching stopper layer by contacting with the lower gate electrode to cover the upper surface and prevent the copper from diffusing so that both ends contact the side walls. First
Forming an upper gate electrode made of copper in the trench with the first barrier film interposed therebetween, the bottom surface of the upper gate electrode is covered with the first barrier film, and both side surfaces are formed from the side walls. And a step of forming a third barrier film for preventing diffusion of copper so as to cover the exposed upper surface of the upper gate electrode. is there. According to the present invention, the upper gate electrode is connected to the first and second parts of the field effect transistor.
To a state in which they are in contact with each other through a third barrier film.
The second barrier film is also used as a side wall.

In the above invention, the side wall is made of silicon nitride. In the above invention, the first barrier film is nitrided on the upper surface of the lower gate electrode to a thickness at which a tunnel current flows. In the above invention, the first or second barrier film is formed by a method in which the number of particles incident at an angle perpendicular or nearly perpendicular to the groove bottom surface is increased. In the above invention, after the upper surface of the lower gate electrode is exposed and the groove is formed, a step of forming a refractory metal film, and a step of forming a refractory metal nitride film on the refractory metal film , Removing the copper, refractory metal film, and refractory metal nitride film in regions other than the trenches, and removing the upper gate electrode made of copper, the refractory metal film, and the refractory metal nitride film. Forming first and second barrier films. In the above invention, after the upper surface of the lower gate electrode is exposed and the groove is formed, a step of forming a first refractory metal film, and a refractory metal nitride film on the first refractory metal film Forming a second layer on the nitride film of the refractory metal.
Forming a high-melting-point metal film, forming a copper film, and forming copper, a first high-melting-point metal film, a high-melting-point metal nitride film, and a second high-melting-point metal film in a region other than the groove. And removing at least a step of forming an upper gate electrode made of copper, a first refractory metal film, a nitride film of a refractory metal, and a second barrier film made of a second refractory metal film. .

In the above invention, a step of forming a high-melting-point metal film in contact with the lower gate electrode, and a step of performing heat treatment to silicide the high-melting-point metal film in contact with the lower gate electrode to form a high-melting-point metal in contact with the lower gate electrode. Forming a silicide film of a melting point metal to be a part of the first barrier film. In the above invention, the sacrificial layer, the etching stopper film, and the lower gate electrode are processed using a hard mask. In the above invention, the sacrificial layer, the etching stopper film, and the lower gate electrode are processed using a hard mask made of silicon oxide or silicon nitride. In the above invention, a refractory metal silicide is formed in a predetermined region of the source / drain before forming the upper gate electrode.

In the above invention, after the upper surface of the lower gate electrode is exposed and a groove is formed, a step of forming a compound of a refractory metal, silicon and nitrogen is performed. A step of forming a refractory metal nitride film on the compound film, a step of forming copper to be an upper gate electrode, and a copper, refractory metal film, refractory metal film nitride film in a region other than the trench And forming first and second barrier films made of an upper gate electrode made of copper, a refractory metal film, and a refractory metal nitride film. In the above invention, after the upper surface of the lower gate electrode is exposed and the groove is formed, a step of forming a compound of a refractory metal, silicon and nitrogen, and a film of the compound of the refractory metal, silicon and nitrogen A step of forming a high-melting-point metal nitride film thereon; a step of forming a high-melting-point metal film on the high-melting-point metal nitride film; a step of forming copper to be an upper gate electrode; Of the copper, the first refractory metal film, the nitride film of the refractory metal film, and the second refractory metal film are removed, and the upper gate electrode made of copper, the first refractory metal film, and the refractory metal are removed. Forming a first and a second barrier film made of a nitride film and a second refractory metal film. In the above invention, a step of forming a refractory metal film in contact with the lower gate electrode, and a step of heat-treating the silicon to react the refractory metal nitride film in contact with the lower gate electrode with the refractory metal in contact with the lower gate electrode Forming a compound film of silicon, nitrogen and
At least as a part of the barrier film.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. Embodiment 1 First, a first embodiment of the present invention will be described.
FIG. 1 is a cross-sectional view illustrating a configuration of the field-effect transistor according to the first embodiment. The field-effect transistor according to the first embodiment includes a lower gate electrode 103 made of polysilicon on a silicon substrate 101 with a gate insulating film 102 interposed therebetween. Also, the lower gate electrode 1
An upper gate electrode 104 made of copper is provided on the substrate 03. The upper gate electrode 104 is formed of a barrier film made of tantalum nitride (first and second
Is formed, and a barrier film (third barrier film) 106 made of silicon nitride is formed so as to cover the upper surface. Therefore, the upper gate electrode 104 is covered with the barrier films 105 and 106 in a tubular shape. Then, the lower gate electrode 10
3 and the upper gate electrode 104 constitute a gate electrode of the transistor.

A side wall (side wall) 107 made of silicon oxide is formed so as to cover the side surface of the gate electrode. Further, a low concentration impurity region 108 is formed in the silicon substrate 101 below the sidewall 107. A source 109 and a drain 110 are formed on the silicon substrate 101 so as to sandwich the low concentration impurity region 108. The low-concentration impurity region 108, the source 109 and the drain 110, the gate insulating film 102, and the gate electrode including the lower gate electrode 103 and the upper gate electrode 104 constitute a field effect transistor having an LDD structure. With the LDD structure, the single-channel effect can be suppressed.

As described above, in the field-effect transistor according to the first embodiment, the gate electrode has a laminated structure composed of polysilicon and copper, so that the resistance of the gate electrode is reduced. In the first embodiment, the copper portion forming the gate electrode is covered with the barrier film not only on the upper surface and the lower surface but also on the side surface. Become.
As a result, problems caused by copper diffusion, such as generation of junction leak current and reduction in on-state current of the transistor, can be solved.

Next, a method of manufacturing the field effect transistor of the first embodiment will be described. First, FIG.
As shown in FIG. 1A, an insulating film 202 is formed on a silicon substrate 101 to a thickness of about 6 nm by dry oxidation. The insulating film 202 becomes a gate insulating film. Subsequently, a polysilicon film 203 having a thickness of about 70 nm is formed on the insulating film 202 by a low-pressure CVD method.
A silicon nitride film 204 having a thickness of about 100 nm
To form

Next, as shown in FIG. 2B, the silicon nitride film 204 and the polysilicon film 203 are dry-etched using the resist pattern 205 as a mask.
Is selectively removed to form the lower gate electrode 103 and the sacrificial pattern 204a. Next, after removing the resist pattern 205, as shown in FIG. 2C, low-concentration impurity regions (LDD) 108 are formed by selective ion implantation using the sacrificial pattern 204a and the lower gate electrode 103 as a mask. I do. Here, As is ion-implanted at an implantation energy of 20 eV, and the implantation amount is 3 × 10 ^13.
cm ^-2 may be used.

Next, as shown in FIG. 2D, a silicon oxide film 206 is formed on the entire surface. This may be performed by depositing silicon oxide by a low-pressure CVD method using TEOS as a raw material. Then, the silicon oxide film 206 is etched back by reactive ion etching (RIE) having vertical anisotropy, thereby forming the lower gate electrode 103 and the sacrificial pattern 20 as shown in FIG.
A side wall 107 is formed on the side surface of 4a.

Next, as shown in FIG. 3F, the source 109 and the drain 110 are formed by selective ion implantation using the sacrificial pattern 204a, the lower gate electrode 103, and the sidewall 107 as a mask. . Here, As is ion-implanted at an implantation energy of 30 eV, and the implantation amount may be about 3 × 10 ¹⁵ cm ⁻² .
Next, boron phosphorus silicate glass is deposited by CVD using ozone and TEOS as raw materials, and a lower interlayer insulating film 209 is formed to a thickness of about 500 nm as shown in FIG.

Next, the chemical mechanical polishing of the oxide film (CM
P), the lower interlayer insulating film 209 is flattened and polished, so that the sacrificial pattern 204a is formed as shown in FIG.
Expose the top. Next, the sacrificial pattern 204a is selectively removed by wet etching using a heated phosphoric acid aqueous solution, and the sidewall 107 and the lower interlayer insulating film 209 are formed on the lower gate electrode 103 as shown in FIG. Is formed. In the wet etching using hot phosphoric acid, silicon and silicon oxide are not etched much, so that the sacrificial pattern 204a made of silicon nitride can be selectively removed.

By the way, in the first embodiment, C
Although the upper portion of the sacrificial pattern 204a is exposed by removing the lower interlayer insulating film 209 by MP, the upper portion of the sacrificial pattern 204a may be exposed by the following method. For example, when flattening can be performed by reflow as in the case of boron silicate glass, the lower interlayer insulating film is reflowed and flattened, and then removed by dry etching or the like to expose the upper portion of the sacrificial pattern 204a. Good. At this time, besides boron silicate glass, silicate glass (BPSG) containing boron and phosphorus can be used as the lower interlayer insulating film.

Further, an SOG (spin-on-glass) material is used as a lower interlayer insulating film, which is coated and flattened, and then the flattened coating film is etched back by dry etching or the like, so that the upper portion of the sacrificial pattern 204a is formed. It may be exposed. Here, when using a CMP method or a method of etching back after planarizing using an SOG material, a normal silicon oxide film in which a lower interlayer insulating film is formed by a CVD method or the like without using silicate glass in particular. Or a silicon nitride film.

Next, as shown in FIG. 4J, a tantalum nitride film is deposited on the lower interlayer insulating film 209 including the bottom and side surfaces of the groove 210 by a sputtering method to have a thickness of 10 nm.
A TaN film 211 is formed to the extent that the TaN film 21
1 is deposited on the substrate 1 by sputtering.
The u layer 212 is formed. Next, for example, CMP of a metal film
By removing the Cu layer 212 and the TaN film 211 by polishing, as shown in FIG.
The upper gate electrode 104 made of copper whose lower surface and side surfaces are covered with a barrier film 105 made of tantalum nitride is formed therein, and additionally, the surface of the lower interlayer insulating film 209 other than the upper portion of the upper gate electrode 104 is exposed. .

Next, as shown in FIG. 4 (l), a barrier film 106 of about 10 nm thick made of silicon nitride is formed on the entire surface.
To form This may be performed by depositing silicon nitride by a plasma CVD method. As described above, a field effect transistor including a gate electrode including the lower gate electrode 103 made of polysilicon and the upper gate electrode 104 made of copper whose periphery is covered with the barrier film 105 and the barrier film 106 was formed. Will be.

Note that the barrier film 106 does not need to be formed to extend over the lower interlayer insulating film 209. As shown in FIG. 1, the upper gate electrode 10 is
The barrier film 106 may be formed in a region where only the upper surface of the fourth substrate 4 is covered. In this case, since the barrier film 106 does not extend over the lower interlayer insulating film 209, the barrier film 106 may be made of, for example, tantalum nitride having the same conductivity as the barrier film 105.

Thereafter, as shown in FIG. 4M, an interlayer insulating film 111 made of silicon oxide (BPSG) doped with boron and phosphorus is formed on the barrier film 106 to a thickness of 500 nm.
It is formed to a thickness of about nm. This is, for example, oxygen gas and TE
It may be formed by a CVD method using OS as a raw material. Next, as shown in FIG.
And a through hole 113 is formed. This may be formed by anisotropic dry etching using a resist pattern formed by a known photolithography graph as a mask. In the contact hole 112, the source 109 surface of the silicon substrate 101 is exposed on the bottom surface, and the upper surface of the upper gate electrode 104 is exposed on the bottom surface of the through hole 113.

Next, as shown in FIG. 5 (o), a barrier film 114 having a two-layer structure of titanium nitride and titanium is formed on the interlayer insulating film 111 including the side and bottom surfaces of the contact hole 112 and the through hole 113. Form. This is CVD
The thickness may be about 50 nm and about 10 nm, respectively. Subsequently, as shown in FIG. 5 (p), the W film 11 made of tungsten is formed on the barrier film 114.
5 is formed to a thickness of about 400 nm by, for example, a low pressure CVD method.

Next, the W film 1 is reduced to such an extent that the contact hole 112 and the through hole 113 are buried.
15 is removed by dry etching or the like. As a result, after the plugs 112a and 113a are formed (FIG.
(Q)) An alloy film 115a made of an aluminum copper alloy containing about 1% of copper is formed to a thickness of about 500 nm by a sputtering method. In addition, a barrier film 116 made of titanium nitride is formed to a thickness of about 30 nm by a sputtering method. Then, the alloy film 115a and the barrier films 114, 1
By patterning No. 16, as shown in FIG.
A source electrode wiring 117 and a gate electrode wiring 118 can be formed.

According to the above-described manufacturing method, an upper gate electrode made of copper is formed after forming the source / drain. That is, since the upper gate electrode is formed after the high-temperature activation heat treatment for forming the source / drain, the upper gate electrode can be formed using copper whose melting point is not so high. In the first embodiment, the barrier film (first and second barrier films) 105
Although tantalum nitride is used as a material, the present invention is not limited to this, and nitrides such as titanium nitride, tungsten nitride, tantalum nitride, molybdenum nitride, titanium nitride silicide, and tungsten silicide (compounds of refractory metal, silicon, and nitrogen) ) Or a metal material such as tantalum or titanium tungsten.

By the way, the above-described barrier film (first to third barrier films)
For the barrier film), a material having a function of preventing diffusion of copper that does not include oxygen as a component may be used. Since the upper gate electrode is made of copper, the oxidation of copper can be suppressed without such oxygen. Further, for example, silicon nitride or the like may be used for the barrier film (first barrier film) disposed on the lower surface of the upper gate electrode. That is, the barrier film only needs to have conductivity enough to inject a current sufficient to drive the channel portion into the lower gate electrode. Therefore, even if silicon nitride is used, the film thickness may be set to such a value that a tunnel current flows. In this case, if the lower gate electrode surface is nitrided, for example, by about 2 nm, a barrier film can be formed at the nitrided portion.

A barrier film (first barrier film) disposed between the above-described barrier film (second barrier film) disposed on the side surface of the upper gate electrode and the lower gate electrode.
May be a multilayer film composed of two or more layers.
In diffusion in a solid, there is a high possibility that a diffusion species is precipitated at an interface or a grain boundary of the solid material (when the film is polycrystalline). Therefore, by forming a multilayer film in which barrier films are stacked,
A small amount of copper diffused at the interface between the films is captured, and the diffusion of the diffused species can be further prevented. This multilayer film is preferably a high melting point metal or a composite film of a high melting point metal. For example, a composite film of Ta and Ta nitride may be used.
Since metals such as copper do not easily diffuse into thermally stable metal nitrides, the amount of point defects is reduced by using a refractory metal nitride film as a barrier film, and the diffusion of copper via point defects is suppressed. You.

The fact that the refractory metal silicide is disposed in contact with the lower gate electrode of silicon as a part of the first barrier film having a multilayer structure is also effective in improving the operation performance of the field effect transistor. is there. This is because at the interface between silicide and silicon, Schottky barrier formation is suppressed and contact resistance is reduced. It is also effective to improve the adhesion between copper and the first barrier film by using a high-melting-point metal as the film in contact with copper in the first barrier film of the multilayer film. The arrangement of the compound of the refractory metal, silicon, and nitrogen as a part of the first barrier film having a multilayer structure in contact with the lower electrode of silicon is also effective in improving the device manufacturing yield. This is because the above compound has good adhesion to silicon. For example, tungsten nitride is converted to CV
The above compound can be formed by forming a film in the groove by the method D or the reactive collimating sputtering method and performing a heat treatment at a temperature of about 500 ° C. At this time, the above compound is formed by the reaction between silicon and the refractory metal nitride, so that the adhesion to silicon is improved.

Embodiment 2 Next, a second embodiment of the present invention will be described. First, a method for manufacturing the field effect transistor according to the second embodiment will be described. First, as shown in FIG. 6A, a 6-nm-thick film is formed on a silicon substrate 601 by dry oxidation.
A gate insulating film 602 is formed to a thickness of about m. Subsequently,
On the gate insulating film 602, a film thickness of 50 n is formed by a low pressure CVD method.
Polysilicon film 70 into which n-type impurity is introduced to about m
3, and a silicon oxide film 704 is formed thereon with a thickness of about 10 nm by a CVD method. In addition, a film thickness of 100 to 100
Form a polysilicon film 705 about 300 nm thick

Next, as shown in FIG. 6B, the polysilicon film 705, the silicon oxide film 704, and the polysilicon film 703 are selectively removed by dry etching using the resist pattern 706 as a mask. A lower gate electrode 603, an etching stopper layer 704a, and a sacrificial pattern 705a are formed. Next, after removing the resist pattern 706, as shown in FIG. 6C, the sacrificial pattern 705a and the lower gate electrode 60 are formed.
The low concentration impurity region (LDD) 608 is formed by selectively implanting ions using the mask 3 as a mask. here,
As is ion-implanted at an implantation energy of 20 eV, and the implantation amount may be about 1 × 10 ¹³ cm ⁻² .

Next, as shown in FIG. 6D, a silicon oxide film 707 is formed on the entire surface. This may be performed by depositing silicon oxide by a low-pressure CVD method using TEOS as a raw material. Then, the silicon oxide film 707 is etched back by reactive ion etching (RIE) having vertical anisotropy, thereby forming the lower gate electrode 603 and the sacrificial pattern 70 as shown in FIG.
A side wall 607 is formed on the side surface of 5a. Note that the sidewall 607 may be made of silicon nitride. Also in this case, it can be formed in the same manner as when it is formed from silicon oxide.

Next, a source 609 and a drain 610 are formed by selective ion implantation using the sacrificial pattern 705a, the lower gate electrode 603, and the sidewall 607 as a mask. Here, As is ion-implanted at an implantation energy of 30 eV, and the implantation amount is 2 × 1.
It may be about 0 ¹⁵ cm ^-2 . The impurity introduction region formed by ion implantation is, for example, 80% in a nitrogen atmosphere.
Heat treatment is performed at 0 ° C. for 10 minutes and at 1000 ° C. for 10 seconds to reduce defects and activate impurities.

Next, a CV using ozone and TEOS as raw materials
D, a boron phosphorus silicate glass is deposited, and these are heated and flown to form a lower interlayer insulating film 7 having a thickness of about 400 to 600 nm as shown in FIG.
09 is formed. Next, the lower interlayer insulating film 709 is removed by a predetermined thickness by, for example, chemical mechanical polishing (CMP) of an oxide film, and the sacrificial pattern 705 is formed as shown in FIG.
a Expose the upper part. Next, the sacrifice pattern 705a is selectively removed by reactive ion etching having high selectivity to an oxide film, and as shown in FIG.
A trench 710 surrounded by the sidewall 607 and the lower interlayer insulating film 709 is formed above the lower gate electrode 603.

Subsequently, as shown in FIG. 7J, the etching stopper layer 704a is removed by an etching method having a selective ratio with respect to silicon oxide, and the upper surface of the lower gate electrode 603 is exposed at the bottom of the groove 710. Next, as shown in FIG. 8K, a tantalum nitride film is deposited on the lower interlayer insulating film 709 including the bottom and side surfaces of the trench 710 by a sputtering method, and a TaN film 711 is formed to a thickness of about 10 nm. Subsequently, as shown in FIG. 8 (l), copper is deposited on the TaN film 711 by sputtering, and the deposited copper is heated and flown to form a film having a flat surface with a thickness of 100 to 500.
A Cu layer 712 having a thickness of about nm is formed.

Here, instead of the TaN film 711, a thin film of titanium nitride, tantalum, tungsten nitride, titanium tungsten or the like may be used. Also, Cu
The layer 612 may be formed by, for example, an electrolytic plating method or a CVD method. Next, for example, CMP of a metal film
By removing the Cu layer 712 and the TaN film 711, as shown in FIG. 8 (m), an upper gate electrode 604 made of copper, whose lower surface and side surfaces are covered with a barrier film 605 made of tantalum nitride, is formed. In addition, the lower interlayer insulating film 70 other than on the upper gate electrode 604
9 Expose the surface. Instead of the TaN film 711, a stacked film of a high melting point metal and a high melting point metal nitride such as a TaN / Ta or Ta / TaN / Ta film may be used.

Further, by using the collimated sputtering method as the method for forming the laminated film, a reduction in the layer resistance of the gate electrode and an increase in the layer resistance when the width of the groove is reduced are suppressed. According to the collimated sputtering method, particles sputtered by a plasma from a raw material target and subjected to film formation have an incident angle to the substrate closer to vertical by a collimator. For this reason, the film thickness formed on the side wall in the groove is smaller than the film thickness formed on the groove bottom. When the material of the barrier film has a higher resistivity than copper, if the thickness of the side surface is large, the resistance increases in proportion to the film thickness. Further, when the width of the groove is reduced, the layer resistance increases. Therefore, it is preferable to reduce the film thickness formed on the side wall in the groove by the above-mentioned collimated sputtering method. A similar effect,
It can also be obtained by a method called ionization sputtering. The ionization sputtering method is a method in which raw material particles ionized by a bias applied to a substrate are incident on the substrate at an almost perpendicular angle, and the incident particles are deposited to form a film. The film thickness to be formed can be reduced.

Next, as shown in FIG. 8 (n), a film thickness of 10 to 10 of titanium oxide or silicon nitride is formed on the entire surface.
A barrier film 606 of about 0 nm is formed. This may be performed, for example, by a reactive sputtering method. As described above, the lower gate electrode 60 made of polysilicon is formed.
Thus, a field-effect transistor including a gate electrode made of copper and an upper gate electrode 604 made of copper and covered with a barrier film 605 and a barrier film 606 is formed. Note that the barrier film 606 is formed of the lower interlayer insulating film 70.
9 does not need to be formed. Barrier film 60
The barrier film 606 may be formed in a region where only the upper surface of the upper gate electrode 604 is covered by the barrier film 6. In this case, since the barrier film 606 does not extend over the lower interlayer insulating film 709, the barrier film 606 may be made of, for example, the same tantalum nitride as the barrier film 605.

Thereafter, as shown in FIG. 8 (o), an interlayer insulating film 713 made of silicon oxide (BPSG) doped with boron and phosphorus is formed on the barrier film 606 to a thickness of 100.
It is formed to about 500 nm. This may be formed, for example, by a CVD method using oxygen gas and TEOS as raw materials. Next, as shown in FIG. 9 (p), contact holes 612 and 613 are formed. This may be formed by anisotropic dry etching using a resist pattern formed by a known photolithography graph as a mask. In the contact hole 612, the source 609 surface of the silicon substrate 601 is exposed at the bottom, and the contact hole 613 is formed at the bottom of the drain substrate 6 of the silicon substrate 601.
10 faces are exposed

Then, as shown in FIG. 9 (q), the source electrode wiring 616 and the drain electrode wiring 6 made of aluminum or the like are formed through the contact holes 612 and 613.
17 may be formed. As described above, Embodiment 2
Also, since the gate electrode has a laminated structure of polysilicon and copper, the resistance of the gate electrode is reduced. Also in the second embodiment, the copper portion forming the gate electrode is not limited to the upper and lower surfaces of the body portion,
Since the side surfaces are covered with the barrier film, the diffusion of copper through the silicon oxide film can be suppressed. As a result, problems caused by copper diffusion, such as generation of junction leak current and reduction in on-state current of the transistor, can be solved.

In the second embodiment, the source
After forming the drain, an upper gate electrode made of copper is formed. That is, since the upper gate electrode is formed after the high-temperature activation heat treatment for forming the source / drain, the upper gate electrode can be formed using copper whose melting point is not so high.

Incidentally, the side wall (side wall) may be made of silicon nitride. In the case where the sidewall is formed of a material such as silicon nitride which can prevent the diffusion of copper, the sidewall can be used as a barrier film (second barrier film) disposed on the side surface of the above-described upper gate electrode. In this case, it is not necessary to newly form a barrier film disposed on the side surface of the upper gate electrode. That is, for example, as shown in FIG. 4J, a tantalum nitride film is not deposited on the lower interlayer insulating film 209 including the bottom and side surfaces of the groove 210 by a sputtering method. The first barrier film is formed by nitriding to a degree. As described above, a tunnel current flows with silicon nitride having a thickness of about 2 nm, and there is no problem in conduction with the upper gate electrode.

At this time, instead of nitriding the upper part of the lower gate electrode 103, another conductive material capable of preventing the diffusion of copper may be formed on the lower gate electrode 103. Needless to say. When the upper gate electrode 104 is formed on the first barrier film, the upper gate electrode 104 can be in a state where the lower surface and both side surfaces are covered with silicon nitride for preventing copper diffusion. Thereafter, the field effect transistor according to the present invention can be obtained by performing the same steps as those in FIG.

Further, when the side walls are made to be harder to be etched under predetermined etching conditions than silicon oxide such as silicon nitride, the contact of the wiring on the upper gate electrode becomes easy. This is due to the following reasons. First, a contact hole is formed in an interlayer insulating film formed on the upper gate electrode, and a wiring is connected to the upper gate electrode through the contact hole. At the time of forming this contact hole, silicon nitride is hardly etched in the etching of the interlayer insulating film made of silicon oxide.
This is because the sidewall is not etched.

In the above description, as shown in FIG. 6B, the lower layer is processed using the resist pattern 706 as a mask. However, the present invention is not limited to this. The processing may be performed using a hard mask. In addition, by using a hard mask, silicide of a high melting point metal can be selectively formed in the source / drain regions.

First, as shown in FIG. 10A, a gate insulating film 602 having a thickness of about 6 nm is formed on a silicon substrate 601 by dry oxidation. Subsequently, the thickness of the gate insulating film 602 is reduced to about 50 nm by a low-pressure CVD method.
A polysilicon film 703 into which a shape impurity is introduced is formed, and a silicon oxide film 704 having a thickness of about 10 nm is formed thereon by the CVD method.
A polysilicon film 705 is formed thereon with a thickness of about 100 to 300 nm by a CVD method. In addition, a silicon oxide film 1001 is formed over the polysilicon film 705a.
Note that this silicon oxide film may be a silicon nitride film.

Next, the polysilicon film 705, the silicon oxide film 704, and the polysilicon film 703 and the silicon oxide film 1001, as shown in FIG.
It is selectively removed by dry etching using the resist pattern 706 as a mask, and the lower gate electrode 603, the etching stopper layer 704a, and the sacrificial pattern 70 are removed.
5a and a hard mask 1001a are formed. Next, after removing the resist pattern 706, as shown in FIG.
a, sacrificial pattern 705a and lower gate electrode 603
Is selectively implanted using the mask as a mask to form a low concentration impurity region (LDD) 608. LDD608
In this case, As is ion-implanted at an implantation energy of 20 eV, and the implantation amount may be about 1 × 10 ¹³ cm ⁻² .

Next, as shown in FIG.
A silicon oxide film 707 is formed on the entire surface by depositing silicon oxide by a low-pressure CVD method using S as a raw material. Then, the silicon oxide film 707 is etched back by reactive ion etching (RIE) having vertical anisotropy, thereby forming the lower gate electrode 603 and the sacrificial pattern 705a as shown in FIG. A sidewall 607 is formed on the side surface. At the same time, a region of the gate insulating film 602 which is not covered with the lower gate electrode 603 and the sidewall 607 is removed. Note that the sidewall 607 may be made of silicon nitride. Also in this case, it can be formed in the same manner as when it is formed from silicon oxide.

Next, the source 609 and the drain 610 are formed by selective ion implantation using the hard mask 1001a as a mask in addition to the sacrificial pattern 705a, the lower gate electrode 603, and the sidewall 607. Also here, As is ion-implanted at an implantation energy of 30 eV, and the implantation amount may be about 2 × 10 ¹⁵ cm ⁻² . The impurity-introduced region formed by ion implantation is, for example, at 800 ° C. for 10 minutes and 10 minutes in a nitrogen atmosphere.
A heat treatment at 00 ° C. for 10 seconds is performed to reduce defects and activate impurities.

Since the hard mask 1001a is used, the sacrificial pattern 705 made of silicon is used.
It is possible to form silicide on the surface of the source / drain region in a self-aligned manner without forming silicide on a. As shown in FIG. 11F, a high-melting-point metal film 1002 is formed by depositing cobalt to a film thickness of 10 to 20 nm over the entire region by sputtering or the like, and then RTA (Rapid).
Thermal Anneal) method to cause the underlying silicon (silicon substrate 601) and the refractory metal film 1002 to react with each other.
As shown in FIG. 1 (g), the source 609 and the drain 610
A silicide 1003 is selectively formed thereon. The heating temperature for forming this silicide is 650-750 ° C.
Good degree. Further, an atmosphere for heating is preferably an inert atmosphere such as nitrogen or argon.

After the silicide is formed, as shown in FIG. 11 (h), the base silicon and unreacted cobalt are selectively removed by wet etching using a mixed aqueous solution of hydrochloric acid: hydrogen peroxide solution: water. . When heated in a nitrogen atmosphere, nitrided cobalt is generated, and this nitrided cobalt is also selectively removed by wet etching using a mixed aqueous solution of hydrochloric acid: hydrogen peroxide solution: water. Thereafter, by heating again at a temperature of about 750 to 850 ° C. by the RTA method, the resistance of the silicide can be reduced. In addition, as a high melting point metal, in addition to cobalt, titanium (1
(0 to 30 nm). In the case of using titanium, wet etching with a mixed aqueous solution of ammonia: hydrogen peroxide water: water may be used to remove excess titanium or titanium nitride immediately after silicide processing.

After the silicide is selectively formed in the source / drain regions, a film thickness of 400 to 6 as in FIG.
A lower interlayer insulating film 709 is formed to a thickness of about 00 nm, and thereafter, the lower interlayer insulating film 709 is removed by a predetermined thickness by, for example, chemical mechanical polishing (CMP) of an oxide film, and at the same time, a hard mass is also removed to remove the sacrificial pattern 705a. Expose the top. Thereafter, by performing the same steps as those shown in FIGS. 7H to 9Q, as shown in FIG.
A state in which the silicide 1003 is formed in addition to the configuration shown in (q) is obtained. Since the silicide 1003 is selectively formed on the source 609 and the drain 610, the source electrode wiring 616 and the drain electrode wiring 6
17 can reduce the contact resistance.

The formation of silicide may be applied to the field effect transistor of the first embodiment. For example, when portions of the gate insulating film 102 on the regions serving as the source / drain are removed at the same time when the sidewall 107 shown in FIG. 3E is formed, the surfaces serving as the source / drain of the silicon substrate 101 are exposed. . After this, FIG.
If the source 109 and the drain 110 are formed as in (f) and a film of a high melting point metal such as cobalt or titanium is formed in the entire area, the source and drain are formed as in FIGS. 11 (f) to 11 (h). Silicide can be selectively formed on the drain. In the first embodiment, since the sacrificial pattern 204a is made of silicon nitride and the sidewall 107 is made of silicon oxide, no silicide is formed on these surfaces. As described above, if the side wall surface or the sacrificial film surface does not easily react with the high melting point metal, it is possible to easily form a silicide selectively on the source / drain.

Next, a method of manufacturing a field effect transistor in the case where the above-mentioned wall is used again as the second barrier film will be described. First, as shown in FIG. 12A, a 6-nm-thick film is formed on a silicon substrate 101 by dry oxidation.
An insulating film 202 is formed to a thickness of about m. The insulating film 202 becomes a gate insulating film. Subsequently, a low-pressure C
The polysilicon film 203 is formed to a thickness of about 70 nm by the VD method.
In this case, a tantalum nitride film is deposited on the polysilicon film 203 by a sputtering method to form a
A TaN film 1201 is formed to a thickness of about nm. And Ta
A polysilicon film 705 having a thickness of about 100 nm is formed on the N film 1201 by a low-temperature CVD method at about 400 ° C. or a plasma CVD method.

Next, as shown in FIG. 12B, the polysilicon film 705, the TaN film 1201, and the polysilicon film 203 are selectively removed by dry etching using the resist pattern 205 as a mask. An electrode 103 and a sacrificial pattern 705a are formed, and a barrier film (first barrier film) 12 sandwiched therebetween is formed.
01a is formed. Next, after the resist pattern 205 is removed, as shown in FIG. 12C, the low-concentration impurity regions (LD
D) Form 108. Here, As is ion-implanted at an implantation energy of 20 eV, and the implantation amount is 3 × 10 ¹³ cm ^−2.
It should be about the degree.

Next, as shown in FIG. 12D, a silicon nitride film 206a is formed on the entire surface. Then, the silicon nitride film 206a is etched back by reactive ion etching (RIE) having vertical anisotropy, thereby forming the lower gate electrode 10 as shown in FIG.
3, barrier film 1201a and sacrificial pattern 705a
Is formed on the side surface of the substrate. Since the sidewall 107a is made of silicon nitride, it can be used as a second barrier film for suppressing copper diffusion. Next, as shown in FIG. 12F, the source 109 and the drain 110 are formed by selective ion implantation using the sacrificial pattern 705a, the lower gate electrode 103, and the sidewall 107a as a mask. For the formation of the source 109 and the drain 110, As is ion-implanted at an implantation energy of 30 eV, and the implantation amount is 3 ×
It may be about 10 ¹⁵ cm ^-2 .

Next, a CV using ozone and TEOS as raw materials
D, a boron phosphorus silicate glass is deposited, and FIG.
As shown in FIG. 3 (g), a lower interlayer insulating film 209 is formed to a thickness of about 500 nm. Next, the lower interlayer insulating film 209 is planarized and polished by chemical mechanical polishing (CMP) of the oxide film, thereby exposing the upper portion of the sacrificial pattern 705a as shown in FIG. Next, the sacrificial pattern 705a is formed under the condition that the polysilicon is selectively etched.
13 (i), the sidewall 107a and the lower interlayer insulating film 20 are formed on the lower gate electrode 103 whose upper surface is covered with the barrier film 1201a, as shown in FIG.
A groove 210 surrounded by 9 is formed.

Next, as shown in FIG. 13 (j), copper is deposited on the lower interlayer insulating film 209 (barrier film 1201a) including the bottom and side surfaces of the groove 210 by sputtering, and has a thickness of about 200 nm. A Cu layer 212 is formed. After this,
For example, by performing the same processing as in FIGS. 4 (k) to 5 (q) described above, such as removing the Cu layer 212 by polishing by CMP of the metal film, as shown in FIG. A field effect transistor using the sidewall 107a as a second barrier film can be formed.

After the TaN film 1201 is formed and before the polysilicon film is formed, a thin silicon oxide film is formed to form a barrier film (first barrier film) 1201a.
An etching stopper layer made of silicon oxide may be provided between the gate electrode and the sacrificial pattern 705a. Providing the etching stopper layer makes it easier to selectively remove the sacrificial pattern 705a. The etching stopper layer can be selectively removed from the barrier film and the side wall by, for example, wet etching using a hydrofluoric acid solution. In this case, the lower interlayer insulating film 209
Is also etched to some extent. As described above, since the upper gate electrode can be formed to have the same width as the lower gate electrode, the width of the upper gate electrode is longer than that of the first embodiment, and the resistance of the upper gate electrode is reduced.

[0071]

As described above, according to the present invention, a lower gate electrode made of silicon formed on a silicon substrate via a gate insulating film, and an upper gate made of copper formed on the lower gate electrode are formed. An electrode, a first barrier film formed to cover the lower surface of the upper gate electrode and to prevent the diffusion of copper, the conductive film being capable of injecting a current sufficient to drive the channel portion into the lower gate electrode; A second barrier film formed so that the lower end contacts the first barrier film and covers both side surfaces of the upper gate electrode to prevent diffusion of copper;
A third barrier film formed so as to cover the upper surface of the upper gate electrode by contacting the second barrier film at its end to prevent diffusion of copper, and formed on the silicon substrate so as to sandwich a region under the lower gate electrode. The source and the drain are provided. Therefore, the upper gate electrode is configured so as to be in contact with many parts constituting the field effect transistor via the first to third barrier films. That is, diffusion of copper from the upper gate electrode can be prevented in all directions. As a result, the present invention has an extremely excellent effect that copper can be used as the material of the gate electrode of the field effect transistor without deteriorating the characteristics of the transistor.

Also, in the present invention, a step of forming a gate insulating film on a silicon substrate, a step of forming a lower gate electrode made of silicon on the gate insulating film, and a step of forming a sacrificial pattern on the lower gate electrode Forming a source / drain by introducing an impurity into a predetermined area of the silicon substrate using the lower gate electrode and the sacrificial pattern as a mask; and forming a silicon oxide on the silicon substrate so as to cover the lower gate electrode and the sacrificial pattern. The first consisting of
Forming the first interlayer insulating film, exposing the upper surface of the sacrificial pattern by removing the first interlayer insulating film, and selectively removing the sacrificial pattern to expose the upper surface of the lower gate electrode. Forming a groove above the lower gate electrode of the interlayer insulating film, and forming first and second conductive barrier films for preventing diffusion of copper so as to cover the upper surface of the lower gate electrode and the side surfaces of the groove; Forming an upper gate electrode made of copper in the trench via the first and second barrier films so that the bottom surface and both side surfaces of the upper gate electrode are covered with the first and second barrier films. And a step of forming a third barrier film for preventing diffusion of copper so as to cover the exposed upper surface of the upper gate electrode.

In the present invention, a step of forming a gate insulating film on a silicon substrate, a step of forming a lower gate electrode made of silicon on the gate insulating film, and a step of forming an etching stopper layer on the lower gate electrode Forming a sacrificial pattern on the etching stopper layer, forming a source / drain by introducing impurities into a predetermined area of the silicon substrate using the lower gate electrode and the sacrificial pattern as a mask, Forming a first interlayer insulating film made of silicon oxide on the silicon substrate so as to cover the sacrificial pattern;
Forming a groove above the lower gate electrode by selectively removing the interlayer insulating film to expose the upper surface of the sacrificial pattern;
Selectively removing the sacrificial pattern to expose the upper surface of the etching stopper layer, removing the etching stopper layer to expose the lower gate electrode upper surface, and diffusing copper so as to cover the lower gate electrode upper surface and the groove side surface. Forming first and second barrier films having conductivity to prevent the formation of the upper gate electrode, and forming an upper gate electrode made of copper in the trench via the first and second barrier films to form a bottom surface of the upper gate electrode And a step of making both side surfaces covered with the first and second barrier films, and a step of forming a third barrier film for preventing diffusion of copper so as to cover the exposed upper surface of the upper gate electrode At least.

Since the manufacturing is performed as described above, the upper gate electrode is manufactured in a state of being in contact with many parts constituting the field effect transistor via the first to third barrier films. That is, diffusion of copper from the upper gate electrode can be prevented in all directions. As a result, the present invention has an extremely excellent effect that copper can be used as the material of the gate electrode of the field effect transistor without deteriorating the characteristics of the transistor. Also, since the upper gate electrode made of copper is formed after the source / drain is formed, after the high-temperature activation heat treatment for forming the source / drain,
An upper gate electrode will be formed. As a result, the upper gate electrode can be formed using copper whose melting point is not so high.

Further, in the present invention, a step of forming a gate insulating film on a silicon substrate, a step of forming a lower gate electrode made of silicon on the gate insulating film, and a step of forming a sacrificial pattern on the lower gate electrode Forming a source / drain by introducing impurities into a predetermined area of the silicon substrate using the lower gate electrode and the sacrificial pattern as a mask; and insulating to prevent diffusion of copper on both side surfaces of the lower gate electrode and the sacrificial pattern. Forming a side wall made of a material, forming a first interlayer insulating film made of silicon oxide on the silicon substrate so as to cover the lower gate electrode and the sacrificial pattern, and removing the first interlayer insulating film Exposing the upper surface of the sacrificial pattern to form a groove on the lower gate electrode by selectively removing the sacrificial pattern; Forming a conductive first barrier film covering the upper surface of the gate electrode so as to prevent diffusion of copper so that both ends are in contact with the side walls, and an upper portion made of copper in the groove via the first barrier film. Forming a gate electrode so that the bottom surface of the upper gate electrode is covered with the first barrier film and both side surfaces are covered with the second barrier film having side walls; and the upper gate electrode is exposed. Forming a third barrier film for preventing diffusion of copper so as to cover the upper surface.

In the present invention, a step of forming a gate insulating film on a silicon substrate, a step of forming a lower gate electrode made of silicon on the gate insulating film, and a step of forming an etching stopper layer on the lower gate electrode Forming a sacrificial pattern on the etching stopper layer, forming a source / drain by introducing impurities into a predetermined amount region of the silicon substrate using the lower gate electrode and the sacrificial pattern as a mask, Forming side walls made of an insulating material for preventing diffusion of copper on both side surfaces of the etching stopper layer and the sacrificial pattern, and forming a sidewall on the silicon substrate so as to cover the lower gate electrode, the etching stopper layer, and the sacrificial pattern. Forming a first interlayer insulating film made of silicon oxide;
Removing the first interlayer insulating film to expose the upper surface of the sacrificial pattern, selectively removing the sacrificial pattern to expose the upper surface of the etching stopper layer, and removing the etching stopper layer to remove the upper surface of the lower gate electrode. Forming a first barrier film having conductivity that is in close contact with the lower gate electrode, covers the upper surface, and prevents copper diffusion so that both ends contact the side walls; A state in which an upper gate electrode made of copper is formed via a first barrier film, and a bottom surface of the upper gate electrode is covered with the first barrier film and both side surfaces are covered with a second barrier film composed of side walls; And a step of forming a third barrier film for preventing diffusion of copper so as to cover the exposed upper surface of the upper gate electrode.

In the present invention, a step of forming a gate insulating film on a silicon substrate, a step of forming a lower gate electrode made of silicon on the gate insulating film, and a step of forming an etching stopper layer on the lower gate electrode Forming a sacrificial pattern on the etching stopper layer, forming a source / drain by introducing impurities into a predetermined area of the silicon substrate using the lower gate electrode and the sacrificial pattern as a mask, Forming side walls made of an insulating material for preventing diffusion of copper on both sides of the etching stopper layer and the sacrificial pattern, and forming the sidewalls on the silicon substrate so as to cover the lower gate electrode, the etching stopper layer, and the sacrificial pattern. Forming a first interlayer insulating film made of silicon oxide;
Selectively removing the first interlayer insulating film to expose the upper surface of the sacrificial pattern to form a groove above the lower gate electrode; and selectively removing the sacrificial pattern to expose the upper surface of the etching stopper layer. Removing the etching stopper layer; forming a first barrier film having conductivity to prevent diffusion of copper so as to be in close contact with the lower gate electrode and cover the upper surface so that both ends are in contact with the side walls; An upper gate electrode made of copper is formed in the groove via a first barrier film, and the bottom surface of the upper gate electrode is covered with the first barrier film, and both side surfaces are covered with a second barrier film made of side walls. And a step of forming a third barrier film for preventing diffusion of copper so as to cover the exposed upper surface of the upper gate electrode.

Since the manufacturing is performed as described above, the upper gate electrode is manufactured in a state of being in contact with many parts constituting the field effect transistor via the first to third barrier films. That is, diffusion of copper from the upper gate electrode can be prevented in all directions. As a result, the present invention has an extremely excellent effect that copper can be used as the material of the gate electrode of the field effect transistor without deteriorating the characteristics of the transistor. Further, since the second barrier film is also used as the side wall, the process can be simplified. Further, since the upper gate electrode made of copper is formed after the source / drain is formed, the upper gate electrode is formed after the high-temperature activation heat treatment for forming the source / drain. As a result, the upper gate electrode can be formed using copper whose melting point is not so high.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view schematically illustrating a configuration of a field-effect transistor according to a first embodiment of the present invention.

FIG. 2 is a process chart for describing a method for manufacturing the field-effect transistor in the first embodiment.

FIG. 3 is a process drawing following FIG. 2 for explaining the method for manufacturing the field-effect transistor in the first embodiment.

FIG. 4 is a process drawing illustrating the method of manufacturing the field-effect transistor according to the first embodiment, following FIG. 3;

FIG. 5 is a process chart illustrating a method for manufacturing the field-effect transistor in the first embodiment, following FIG. 4;

FIG. 6 is a process chart illustrating a method for manufacturing a field effect transistor according to a second embodiment of the present invention.

FIG. 7 is a process drawing illustrating the method for manufacturing the field-effect transistor in the second embodiment, following FIG. 6;

FIG. 8 is a process drawing following FIG. 7 for illustrating the method for manufacturing the field-effect transistor in the second embodiment.

FIG. 9 is a process drawing illustrating the method for manufacturing the field-effect transistor in the second embodiment, following FIG. 8;

FIG. 10 is a process chart for describing a method of manufacturing a field-effect transistor according to another embodiment of the present invention.

FIG. 11 is a process drawing following FIG. 10 for explaining a method of manufacturing a field-effect transistor in another mode of the present invention.

FIG. 12 is a process chart for describing a method of manufacturing a field-effect transistor according to another embodiment of the present invention.

FIG. 13 is a process drawing following FIG. 12 for explaining a method of manufacturing a field-effect transistor in another mode of the present invention.

FIG. 14 is a cross-sectional view illustrating a configuration of a conventional field-effect transistor.

[Description of Signs] 101: silicon substrate, 102: gate insulating film, 103
... lower gate electrode, 104 ... upper gate electrode, 105 ...
Barrier film (first and second barrier films), 106 ... barrier film (third barrier film), 107 ... sidewall, 108
... low-concentration impurity region, 109 ... source, 110 ... drain.

Claims (37)

[Claims] A lower gate electrode made of silicon formed on a silicon substrate with a gate insulating film interposed therebetween; an upper gate electrode made of copper formed on the lower gate electrode; A first barrier film formed to cover the lower surface of the upper gate electrode and to prevent diffusion of copper, the first barrier film having conductivity sufficient to inject a current sufficient to drive the first barrier film; A second barrier film formed to cover both side surfaces of the upper gate electrode to prevent diffusion of copper; and an end contacting the second barrier film to cover an upper surface of the upper gate electrode. Third to prevent diffusion of copper formed in
And a source / drain formed on the silicon substrate so as to sandwich a region below the lower gate electrode. 2. The field effect transistor according to claim 1, further comprising: a side wall formed on a side surface of the lower gate electrode and the upper gate electrode, wherein the second barrier film is formed by a part of the side wall. Characteristic field effect transistor. 3. The field effect transistor according to claim 1, wherein the third barrier film is made of an insulating material. 4. The field effect transistor according to claim 3, further comprising an insulating layer formed on the silicon substrate by opening an upper surface of the upper gate electrode, wherein the third barrier film is formed on the insulating layer. A field-effect transistor formed to extend. 5. The field effect transistor according to claim 3, wherein the second and third barrier films are made of a high melting point metal or a high melting point metal nitride. 6. The field effect transistor according to claim 1, wherein said first barrier film is made of an insulating material formed to a thickness through which a tunnel current flows. Field effect transistor. 7. The field effect transistor according to claim 1, wherein the first, second, and first barrier films are made of a high melting point metal or a high melting point metal nitride. Field effect transistor. 8. The field effect transistor according to claim 2, wherein the insulating material is made of one of silicon nitride and boron nitride. 9. The field effect transistor according to claim 1, wherein the first barrier film is a multilayer film including two or more layers. 10. The field effect transistor according to claim 1, wherein the first barrier film is a layer made of a high melting point metal, a layer made of a high melting point metal silicide, or a high melting point metal and silicon. Field effect transistor, characterized in that the field effect transistor is a multilayer film formed by laminating a plurality of layers by combining any one of a layer made of a compound of nitrogen and nitrogen or a layer made of a nitride of a high melting point metal. 11. The field effect transistor according to claim 10, wherein the first barrier film has a lowermost layer formed of a metal silicide layer or a layer made of a compound of a refractory metal metal, silicon and nitrogen. A field-effect transistor, characterized in that: 12. The field effect transistor according to claim 11, wherein the lowermost layer of the first barrier film is formed of a metal silicide layer or a layer made of a compound of a refractory metal metal, silicon and nitrogen. A field effect transistor comprising a multilayer film in which a refractory metal nitride layer is disposed on a silicide layer. 13. The field effect transistor according to claim 11, wherein the lowermost layer of the first barrier film is formed of a metal silicide layer or a layer made of a compound of a refractory metal metal, silicon and nitrogen. A refractory metal nitride layer is disposed on a silicide layer or a layer composed of a compound of silicon and nitrogen with a refractory metal metal, and the uppermost layer is a multilayer film composed of the refractory metal. Field-effect transistor. 14. The field effect transistor according to claim 1, wherein a refractory metal silicide film is formed in a predetermined region on the surface of the source / drain. . 15. A step of forming a gate insulating film on a silicon substrate, a step of forming a lower gate electrode made of silicon on the gate insulating film, and a step of forming a sacrificial pattern on the lower gate electrode. Forming a source / drain by introducing an impurity into a predetermined area of the silicon substrate using the lower gate electrode and the sacrificial pattern as a mask; and forming the source / drain on the silicon substrate so as to cover the lower gate electrode and the sacrificial pattern. Forming a first interlayer insulating film made of silicon oxide, exposing the upper surface of the sacrificial pattern by removing the first interlayer insulating film, and selectively removing the sacrificial pattern. Forming a groove above the lower gate electrode in the first interlayer insulating film by exposing an upper surface of the lower gate electrode; Forming first and second barrier films having conductivity to prevent copper diffusion so as to cover the upper surface of the gate electrode and the side surfaces of the trench; and forming the first and second barrier films in the trench. Forming an upper gate electrode made of copper through the first gate electrode so that the bottom surface and both side surfaces of the upper gate electrode are covered with the first and second barrier films; and the upper gate electrode is exposed. Forming a third barrier film for preventing diffusion of copper so as to cover the upper surface. 16. The method according to claim 15, wherein the sacrificial pattern is made of a material that is etched faster than silicon and silicon oxide under a predetermined etching condition. A method for manufacturing a transistor. 17. A step of forming a gate insulating film on a silicon substrate, a step of forming a lower gate electrode made of silicon on the gate insulating film, and a step of forming an etching stopper layer on the lower gate electrode Forming a sacrificial pattern on the etching stopper layer; forming a source / drain by introducing impurities into a predetermined amount region of the silicon substrate using the lower gate electrode and the sacrificial pattern as a mask; Forming a first interlayer insulating film made of silicon oxide on the silicon substrate so as to cover the lower gate electrode and the sacrificial pattern; removing the first interlayer insulating film to remove an upper surface of the sacrificial pattern; Exposing, selectively removing the sacrificial pattern to expose the etching stopper layer upper surface. Removing the etching stopper layer, exposing the upper surface of the lower gate electrode to form a groove on the lower gate electrode, and diffusing copper so as to cover the upper surface of the lower gate electrode and the side surface of the groove. Forming a first and a second barrier film having a blocking conductivity; and forming an upper gate electrode made of copper in the groove via the first and second barrier films to form the upper gate electrode. Making the bottom and both sides of the upper gate electrode covered with the first and second barrier films, and blocking the diffusion of copper so as to cover the exposed upper surface of the upper gate electrode. Forming a field effect transistor. 18. A step of forming a gate insulating film on a silicon substrate, a step of forming a lower gate electrode made of silicon on the gate insulating film, and a step of forming an etching stopper layer on the lower gate electrode. Forming a sacrificial pattern on the etching stopper layer; forming a source / drain by introducing an impurity into a predetermined amount region of the silicon substrate using the lower gate electrode and the sacrificial pattern as a mask; Forming a first interlayer insulating film made of silicon oxide on the silicon substrate so as to cover a lower gate electrode and the sacrificial pattern; and selectively removing the first interlayer insulating film from the sacrificial pattern. Forming a groove above the lower gate electrode by exposing the upper surface of the substrate; and selectively removing the sacrificial pattern. Exposing the upper surface of the etching stopper layer, exposing the upper surface of the lower gate electrode by removing the etching stopper layer, and preventing diffusion of copper so as to cover the upper surface of the lower gate electrode and the side surface of the groove. Forming a first and a second barrier film having a conductive property, and forming an upper gate electrode made of copper in the groove via the first and second barrier films to form the upper gate electrode. Making the bottom surface and both side surfaces covered with the first and second barrier films; and forming a third barrier film for preventing diffusion of copper so as to cover an exposed upper surface of the upper gate electrode. Forming a field effect transistor. 19. The method according to claim 17, wherein the sacrificial pattern is made of a material that is etched faster than silicon oxide under predetermined etching processing conditions. A method for manufacturing a transistor. 20. The method for manufacturing a field effect transistor according to claim 17, wherein the sacrificial layer, the etching stopper layer, and the lower gate electrode are processed using a hard mask. A method for manufacturing a transistor. 21. The method for manufacturing a field effect transistor according to claim 17, wherein the sacrificial layer, the etching stopper layer, and the lower gate electrode are processed using a hard mask made of silicon oxide or silicon nitride. A method for manufacturing a field effect transistor. 22. The method of manufacturing a field-effect transistor according to claim 15, wherein after the upper surface of the lower gate electrode is exposed and a groove is formed,
A step of forming a high-melting-point metal film; a step of forming a high-melting-point metal nitride film on this high-melting-point metal film; a step of forming copper; Removing the melting point metal film and the refractory metal nitride film, and forming an upper gate electrode made of copper, and the first and second barrier films made of the refractory metal film and the refractory metal nitride film; And a method for manufacturing a field-effect transistor. 23. The method for manufacturing a field-effect transistor according to claim 15, wherein after the upper surface of the lower gate electrode is exposed and a groove is formed,
Forming a first refractory metal film; forming a refractory metal nitride film on the first refractory metal film; and forming a second refractory metal nitride film on the refractory metal nitride film. A step of forming a melting point metal film, a step of forming copper, the copper in the region other than the groove, the first high melting point metal film,
The nitride film of the refractory metal and the second refractory metal film are removed, and the upper gate electrode made of copper, the first refractory metal film, the refractory metal nitride film, and the second refractory metal film are removed. Forming a first and a second barrier film made of a melting point metal film. 24. The method of manufacturing a field-effect transistor according to claim 15, wherein after the upper surface of the lower gate electrode is exposed and a groove is formed,
Forming a compound of a refractory metal, silicon, and nitrogen; forming a nitride film of the refractory metal on the film of the compound of the refractory metal, silicon, and nitrogen; Forming a copper film, and removing the copper, the high-melting-point metal film, and the nitride film of the high-melting-point metal film in a region other than the groove, and forming an upper gate electrode made of copper and the high-melting-point metal film. Forming at least a first and a second barrier film made of a nitride film of the high melting point metal. 25. The method for manufacturing a field-effect transistor according to claim 15, wherein after the upper surface of the lower gate electrode is exposed and a groove is formed,
Forming a compound of a refractory metal, silicon, and nitrogen; forming a nitride film of the refractory metal on the film of the compound of the refractory metal, silicon, and nitrogen; Forming a refractory metal film on the nitride film, forming copper serving as the upper gate electrode, copper in a region other than the trench, the first refractory metal film,
The nitride film of the refractory metal film and the second refractory metal film are removed, and the upper gate electrode made of copper and the first refractory metal film, the refractory metal nitride film, and the second refractory metal film are removed. Forming a first and a second barrier film made of a refractory metal film. 26. The method for manufacturing a field effect transistor according to claim 22, wherein a step of forming a film of a refractory metal in contact with the lower gate electrode; Forming a high-melting-point metal silicide film in contact with the lower gate electrode by forming a silicide film of the high-melting-point metal into a part of the first barrier film. Manufacturing method. 27. A step of forming a gate insulating film on a silicon substrate; a step of forming a lower gate electrode made of silicon on the gate insulating film; and a step of forming a sacrificial pattern on the lower gate electrode. Forming a source / drain by introducing an impurity into a predetermined amount region of the silicon substrate using the lower gate electrode and the sacrificial pattern as a mask; Forming a side wall made of an insulating material to be blocked; forming a first interlayer insulating film made of silicon oxide on the silicon substrate so as to cover the lower gate electrode and the sacrificial pattern; Removing the interlayer insulating film to expose the upper surface of the sacrificial pattern; and selectively removing the sacrificial pattern to remove Forming a groove above the lower gate electrode; forming a first barrier film having a conductivity covering the upper surface of the lower gate electrode and preventing diffusion of copper so that both ends are in contact with the side walls; An upper gate electrode made of copper is formed in the trench with the first barrier film interposed therebetween, and a bottom surface of the upper gate electrode is covered with the first barrier film and both side surfaces are formed of the second barrier. A step of forming a third barrier film for preventing diffusion of copper so as to cover an exposed upper surface of the upper gate electrode; A method for manufacturing a field effect transistor. 28. A step of forming a gate insulating film on a silicon substrate; a step of forming a lower gate electrode made of silicon on the gate insulating film; and a step of forming an etching stopper layer on the lower gate electrode. Forming a sacrificial pattern on the etching stopper layer; forming a source / drain by introducing impurities into a predetermined amount region of the silicon substrate using the lower gate electrode and the sacrificial pattern as a mask; Forming a lower gate electrode, the etching stopper layer, and sidewalls made of an insulating material for preventing diffusion of copper on both side surfaces of the sacrificial pattern; and forming the lower gate electrode, the etching stopper layer, and the sacrificial pattern. A first interlayer made of silicon oxide on the silicon substrate so as to cover Forming an insulating film; removing the first interlayer insulating film to expose an upper surface of the sacrificial pattern; and selectively removing the sacrificial pattern to expose the upper surface of the etching stopper layer. Forming a groove on the lower gate electrode by removing the etching stopper layer; and conductively blocking copper diffusion so that the upper surface is covered in close contact with the lower gate electrode and both ends contact the side walls. Forming an upper gate electrode made of copper in the trench with the first barrier film interposed therebetween, and forming a bottom surface of the upper gate electrode on the first barrier film. A step in which both sides are covered with a second barrier film comprising the side wall, and a third barrier film for preventing diffusion of copper so as to cover an exposed upper surface of the upper gate electrode Method of manufacturing a field effect transistor, characterized in that the step comprising at least the formation. 29. A step of forming a gate insulating film on a silicon substrate; a step of forming a lower gate electrode made of silicon on the gate insulating film; and a step of forming an etching stopper layer on the lower gate electrode. Forming a sacrificial pattern on the etching stopper layer; forming a source / drain by introducing impurities into a predetermined amount region of the silicon substrate using the lower gate electrode and the sacrificial pattern as a mask; Forming a lower gate electrode, the etching stopper layer, and sidewalls made of an insulating material for preventing diffusion of copper on both side surfaces of the sacrificial pattern; and forming the lower gate electrode, the etching stopper layer, and the sacrificial pattern. A first interlayer made of silicon oxide on the silicon substrate so as to cover Forming an insulating film; selectively removing the first interlayer insulating film to expose an upper surface of the sacrificial pattern to form a groove above the lower gate electrode; Removing the etching stopper layer, removing the etching stopper layer, and blocking the diffusion of copper so that the upper surface is covered in close contact with the lower gate electrode and both ends contact the side walls. Forming a first barrier film having a conductive property, and forming an upper gate electrode made of copper in the groove via the first barrier film, wherein the bottom surface of the upper gate electrode is the first A step in which both side surfaces are covered with a barrier film and are covered with a second barrier film composed of the side wall; and a third step of preventing diffusion of copper so as to cover an exposed upper surface of the upper gate electrode. of Method of manufacturing a field effect transistor, characterized in that it comprises at least a step of forming a rear film. 30. The method for manufacturing a field-effect transistor according to claim 28, wherein the sacrificial layer, the etching stopper layer, and the lower gate electrode are processed using a hard mask. 31. The method for manufacturing a field effect transistor according to claim 28, wherein the sacrificial layer, the etching stopper layer, and the lower gate electrode are processed with a hard mask made of silicon oxide or silicon nitride. A method for manufacturing a field effect transistor. 32. The method for manufacturing a field-effect transistor according to claim 27, wherein a step of forming a high-melting-point metal film in contact with said lower gate electrode; Forming a high-melting-point metal film in contact with the lower gate electrode to form a high-melting-point metal silicide film in contact with the lower gate electrode, and forming the silicide film as a part of the first barrier film. Of manufacturing a field effect transistor. 33. The method for manufacturing a field-effect transistor according to claim 27, wherein a step of forming a refractory metal film in contact with the lower gate electrode; Reacting the refractory metal nitride film in contact with the electrode with silicon to form a compound film of the refractory metal, silicon and nitrogen in contact with the lower gate electrode, and forming a compound film of the first barrier film. A method for manufacturing a field effect transistor, comprising at least: 34. The method for manufacturing a field effect transistor according to claim 17, wherein said side wall is made of silicon nitride. 35. The method for manufacturing a field-effect transistor according to claim 15, wherein the first barrier film is formed by nitriding the upper surface of the lower gate electrode to a thickness through which a tunnel current flows. A method for manufacturing a field effect transistor, comprising: 36. The method for manufacturing a field effect transistor according to claim 15, wherein the first or second barrier film is formed at an angle perpendicular to or substantially perpendicular to the groove bottom surface. A method for manufacturing a field effect transistor, wherein a film is formed by a method in which incident particles are increased. 37. The method of manufacturing a field effect transistor according to claim 15, wherein a refractory metal silicide is formed in a predetermined region of the source / drain before forming the upper gate electrode. A method for manufacturing a field effect transistor, comprising: