JP3381447B2 - Semiconductor device - Google Patents

Abstract

PURPOSE: To obtain a package with which it is possible to prevent deformation of a base due to assembling and processing and to reduce the thickness inexpensively and, at the same time, to prevent occurrence of unfilling of a sealing material at the time of molding in regard to a semiconductor device wherein a plurality of IC chips are mounted in one package. CONSTITUTION: The rear sides of IC chips 1 and 2 are joined on each other by an adhesive tape such as a polyimide tape 6 or a bonding agent such as silver paste. Each IC chip is wired by gold wires 7 from electrodes 15 to leads 12 and 13 which are terminals for contact with the outside. It is allowable, besides, that positions of the IC chips to be joined at the rear sides are shifted relatively in the lateral direction, each of the chip being joined to the leads at one end the rear sides thereof being bonded to each other at the other end. It is also allowable that the leads are depressed in the vertical direction of the sections thereof at this time so that the IC chips may not be tilted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to an IC chip mounting structure and a lead structure in a semiconductor device when a plurality of IC chips are mounted in one package.

[0002]

2. Description of the Related Art A conventional semiconductor device of this type is shown in FIG.
The C chip (two IC chips in FIG. 8, namely, IC chip A.1, IC chip B.2) is I on the substrate 4.
It is bonded to the die pad 8 which is a bonding pattern of C by the adhesive 9, and is electrically contacted to the wiring pattern 5 on the substrate 4 by the gold wire 7 which is one of the conductive bonding means. After electrical contact is made from the pattern 5 to the lead A12 which is an electrical contact terminal with the outside by the gold wire 7 which is one of the conductive joining means, the encapsulant 10 shown by the dotted line in FIG. It was supposed to be sealed with. In some cases, the lead A12, which is an electrical contact terminal with the outside, is shaped with a desired shape after the portion outside the sealing material 10 is sealed with the sealing material 10.

[0003]

In an example of the above-mentioned conventional semiconductor device, the thickness of the substrate is set to 0.000 as a measure against the deformation of the substrate in the manufacturing process such as die bonding, wire bonding, or molding. About 4 mm or more is required.

However, when the substrate has a thickness of 0.4 mm or more, the substrate having a large volume interferes with the molding process of the encapsulating material to impede the flow of the encapsulating material, resulting in unfilling. There is. Further, since a thick substrate of 0.4 mm is built in the package, it is difficult to make the package thin.

Normally, the thickness of the substrate is the thinnest in the case of a resin substrate, for example, and it can be manufactured up to about 0.1 mm. However, if the thickness of the substrate is about 0.1 mm, it will be too thin to assemble the product. The substrate may be deformed during processing.

The object of the present invention is to provide a plurality of I as described above.
An object of the present invention is to provide a semiconductor device in which unfilling does not occur when a C chip is mounted in one package and which can be made thin at low cost. It is an object of the present invention to provide a semiconductor device that can realize a thin package at low cost while preventing it. Further, in addition to the above-mentioned object, it is another object of the present invention to provide a semiconductor device in which an IC chip can be more stably fixed (not suspended). Further, the IC chip can be more stably fixed, and at the same time, the man-hour for mounting the spacer and the cost of the spacer can be reduced to provide the IC chip at a lower cost.
In addition to stabilizing the fixing of the chip, I to the lead
An object of the present invention is to provide a semiconductor device of higher quality by stabilizing the height of the joint portion of the C chip.

[0007]

The above object is achieved by bonding the back surfaces of the IC chips to each other with a bonding means such as an adhesive or an adhesive tape. At the same time, the positions of the IC chips for connecting the back surfaces to each other are relatively shifted in the direction of the bonding surface, and the side opposite to the bonding portion is connected to the external connection terminal via a spacer by a bonding means such as an adhesive or an adhesive tape. This can be achieved more stably by bonding the IC chip so that it does not tilt. Further, the position of the connection terminal with the outside is relatively shifted (that is, depressed) in the direction perpendicular to the joint surface in the vertical direction of the cross section so that the IC chip does not tilt.
As a result, it is more stable, and a spacer is not required, so that it can be achieved at a lower cost. Further, the IC chip can be stably fixed and the lead depressing amount can be reduced by the amount of the spacer by depressing the connection terminal to the outside and interposing the spacer on the adhesive portion on the back surface of the IC chip. There is no variation in the amount of depressing that occurs when the amount becomes large, and the height of the bonding portion of the IC chip to the lead can be stabilized and higher quality can be achieved. The semiconductor device of the present invention according to claim 1
Is a lead having an external output terminal and a first IC electrically connected to the lead by wire bonding.
A chip, a second IC chip, and a resin that seals at least a part of the lead and the first and second IC chips, and the first and second IC chips have inactive surfaces on each other. Bonded by a first joining means , said first I
The C chip is attached to the lead by the second joining means.
And the second IC chip is fronted by the third bonding means.
In the semiconductor device bonded to the lead, the first and second IC chips are arranged at positions overlapping with each other with a relative displacement in the direction of the bonding surface, and are directly bonded by the bonding means. Is t2, the thickness of the first joining means is t3, and the thicknesses of the second and third joining means are t4, the equation of t3 = t2 + 2 × t4 is substantially satisfied. It is characterized by the fact that it holds. In addition, claim 2
According to another aspect of the semiconductor device of the present invention, a lead having an external output terminal, a first IC chip and a second IC chip electrically connected to the lead by wire bonding, and at least a part of the lead. The first and second
And a resin for sealing the IC chip, the first and second IC chips are adhered to each other at their inactive surfaces by a first joining means , and the first IC chip is made into a second joining means.
Is attached to the lead by the second IC chip
In the semiconductor device in which the third bonding means adheres to the lead, the first and second IC chips are
It is placed at a position where it is relatively displaced in the direction of the joint surface and overlaps,
The spacers are adhered to each other via a spacer, the thickness of the spacer is t1, and the thickness of the lead is t.
2, the thickness of the first joining means is t3, the second and
When the thickness of the third joining means is t4, 2 × t3
It is characterized in that the equation of + t1 = t2 + 2 × t4 substantially holds.

[0008]

[Function] A plurality of IC chips are fixed with an adhesive, and this IC
In a semiconductor device in which a chip and an external output terminal are electrically joined by a conductive joining means such as a gold wire and sealed with a sealing material such as a resin, the back surfaces of IC chips are joined together with an adhesive or a joining tape. By bonding by means of means, the thickness required for bonding and fixing can be made smaller than the case where a substrate is used for bonding and fixing the IC chip, so that the volume of the bonding member in the package can be made small and thin. Unfilling is unlikely to occur when stopping, and it is possible to reduce the package thickness while preventing the gold wire and IC chip from being exposed.

Further, the positions of the IC chips to be bonded are relatively shifted in the direction of the bonding surface, one end is bonded to the lead, and the bonding surfaces of the ICs are balanced with a spacer so that the ICs do not tilt. By joining while
The C chip can be fixed more stably (it does not become suspended). Also, by depressing the leads for joining the shifted ICs in the directions perpendicular to the joining surface so that the joined ICs do not tilt, the IC chip can be more stably fixed and a spacer is not used. Although depressing man-hours are required, man-hours for mounting the spacers and spacer parts cost can be reduced, and cost can be reduced. Further, by mounting the spacer on the IC chip joint surface and sharing the lead depressurization, the IC chip can be stably fixed, and the depressurization can be reduced by the amount of the spacer. It is possible to reduce the variation in the depressing depth that occurs in the.

[0010]

EXAMPLES Examples of the present invention will be described below.

FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention. According to FIG. 1, a plurality of IC chips (in FIG. 1, IC chip A.1, IC chip B
In 2), the back surface is joined by the polyimide tape 6, and each IC chip is a lead A. 12 which is a terminal for contact with the outside and a lead B. 13 provided adjacent to the lead A. The gold wire 7 makes electrical contact with the electrode 15. For further explanation, FIG. 2 is a perspective view of the internal structure of the first embodiment of the semiconductor device of the present invention. In FIG. 2, the gold wire 7 is an IC for the leads A and 12 and the leads B and 13.
From the chip A.1, the IC chip B.2, to the corresponding lead A.12 and lead B.13, wiring is provided from above and below each lead. That is, the IC chip A.1 is wired above the corresponding lead B.13 in FIG. 2, and the IC chip B.2 is wired below the corresponding lead A.12. If necessary, there may be leads that are not joined, or wiring may be provided from the IC chip A.1, IC chip B.2 to the same lead from above and below. Also Lead A
The leads 12 and the leads B and 13 do not have to alternate every other one as shown in the figure. The IC chip joining means may be an adhesive tape such as a polyimide tape, an aluminum foil, or a polyethylene tape, or a liquid adhesive such as a silver paste or an epoxy resin as long as it can bond the IC chips. Even when a material is used, it is desirable that the material has heat resistance equal to or higher than the temperature (at least 120 ° C.) applied in the manufacturing process.

As for the manufacturing method, FIGS.
(G) is a sectional view of each main manufacturing step relating to an example of the manufacturing method of the first embodiment of the semiconductor device of the present invention. Figure 3
Explaining with reference to (a) to FIG. 3 (g), first, referring to FIG.
(A) is sectional drawing at the time of the die attach in an example of the manufacturing method of the 1st Example of the semiconductor device of this invention.
The back surfaces of the C chip A.1 and the IC chip B.2 are adhered to each other with a polyimide tape 6. At this time, IC chip A
1, the IC chip B.2 is supported by the support pin 18. Next, FIG. 3B is a cross-sectional view at the time of wire bonding in an example of the manufacturing method of the first embodiment of the semiconductor device of the present invention. The IC chip B2 on the lower surface side is supported by the support pins A18 from below. It is supported, and in this state, the upper IC chip A1 is wire-bonded to the lead A12 or the lead B13 by the gold wire 7. Next, in order to wire bond the lower IC chip B2 to the IC
The chip must be flipped, which is shown in Figure 3.
(C) is a cross-sectional view immediately before IC chip inversion in an example of the manufacturing method of the first embodiment of the semiconductor device of the present invention.
IC chip A.1 and IC chip B.2 are support pins A.1
The lower surface of the IC chip 8 is supported by 8 and the upper surface of the support pin B is supported by the support pins B and 19.
・ The positions of IC chip B and IC chip B are reversed and IC chip B
・ 2 is the top surface. After the inversion is completed, the support pin A · 18 is removed. The support pins A, 18 and B and 19 have flat shapes at the portions which come into contact with the IC chips A and B, and have other shapes as long as they do not come into contact with the gold wire 7. The dimensions may be determined according to the mounting relationship with the machine. Further, considering the balance when supporting the IC chips A.1, B.2 by the support pins A.18, B.19, the central portion of each IC chip is the best. Next, FIG. 3D shows a cross-sectional view after completion of wire bonding in an example of the manufacturing method of the first embodiment of the semiconductor device of the present invention. According to FIG. 3D, wire bonding is performed first. With the IC chip A.1 on the back surface being supported by the support pins B.19, IC chip B.2
Is wire-bonded by the gold wire 7. Next in FIG.
FIG. 3E is a cross-sectional view of the carrying state after wire bonding in the example of the manufacturing method of the first embodiment of the semiconductor device of the present invention. According to FIG. 3E, the IC chip A after wire bonding 1, IC chip B ・ 2 is suction nozzle 2
Adsorbed by 1, and lead A ・ 12, lead B ・
The sheet 13 is supported and conveyed by the conveying claw 22. Further, FIG. 3 (f) shows a cross-sectional view at the time of molding in the example of the manufacturing method of the first embodiment of the semiconductor device of the present invention. The conveyed IC chip A.1, IC chip B.2
The leads A and 12 and the leads B and 13 are sealed from the lower side by the sealing material 10 in the mold 24 while being supported by the support pins D23 which are made of resin and can be cut. Finally, Figure 3
FIG. 3G shows a cross-sectional view of the finished state after molding in the example of the manufacturing method of the first embodiment of the semiconductor device of the present invention. According to FIG. 3G, the molded semiconductor device is The support pins D · 23 and the support pins D · 23 are removed from the mold 24, and the support pins D · 23 are cut to a desired dimension (along the surface of the sealing material in FIG. 3G). If necessary, the leads protruding from the sealing material are cut into a desired shape and shaped.

Since there may be three or more IC chips, as an example of mounting a large number of IC chips in FIG. 4, the first embodiment of the semiconductor device of the present invention is applied and four IC chips are applied. The perspective view of one Example at the time of joining a chip is shown. In the case of the present embodiment, instead of the IC chip A.1 of the embodiment shown in FIG. 2, three ICs, that is, IC chip C.25, IC chip D.3, IC chip E.9, It is joined to the IC chip B.2 on the side by joining means (polyimide tape 6 in this embodiment). Lead A ・ 12
Is connected to the IC chip B.2 via the gold wire 7, and the leads B.13 are connected to the IC chip C25 and the IC chip D.
・ 3, IC chip E ・ 9 is wired by gold wire 7.
Other reference numerals are the same as in FIG.

Next, FIGS. 5A to 5C are sectional views showing a second embodiment of the semiconductor device of the present invention.

For the sake of explanation, the following symbols are used.

Thickness of spacer = t ₁ Thickness of lead = t ₂ Thickness of joining means on IC chip side = t ₃ (In this embodiment, thickness of polyimide tape 6 at joining portion between IC chips) Thickness of joining means on lead side = t ₄ (thickness of polyimide tape 6 at the joining portion between the lead and the IC chip in the case of the present embodiment) Here, FIG. 5A shows the semiconductor device of the present invention. FIG. 5B is a cross-sectional view of the second embodiment in which the thickness t ₄ of the joining means on the lead side = the thickness t ₃ of the joining means on the IC chip side.
Relates to a second embodiment of the semiconductor device of the present invention, and is a cross-sectional view in the case where the thickness t ₄ of the joining means on the lead side> the thickness t ₃ of the joining means on the IC chip side, FIG. A second embodiment of the semiconductor device of the present invention is shown in a sectional view in the case where the thickness t ₄ of the joining means on the lead side is smaller than the thickness t ₃ of the joining means on the IC chip side. First, according to FIG. 5A, the IC chip A.1,
The IC chip B.2 is bonded on the back surface by the polyimide tape 6 in a positional relationship shifted from each other in the left-right direction in FIG.
One end of the C chip is joined to the space 16 created by the displacement of the IC chips by the polyimide tape 6. Further, the ends of the IC chip A.1 and IC chip B.2 opposite to the joints of the leads A.12 and leads B.13 (that is, the back surface joint portion of the IC chip) are polyimide tape on the back surface. 6 is attached,
Furthermore, the spacers 17 are balanced and fixed so as not to tilt. Here, the thickness t of the spacer 17
₁ is the thickness t ₃ of the adhesive on the IC chip side = the thickness t ₄ of the adhesive on the lead side, so that the thickness t _{1 of the} spacer = the thickness t _{2 of the} lead prevents the IC chip from tilting. For example, wire bonding and resin sealing do not cause a problem due to the inclination of the IC chip. Further, as in the example of FIG. 5B, the thickness t ₄ of the adhesive on the lead side> the thickness t ₃ of the adhesive on the IC chip side.
If the thickness of the adhesive on the lead side is t ₄ <the thickness of the adhesive on the IC chip side is t ₃ , as in the example of FIG. 5C, the thickness of the spacer 17 may be increased. (→ Figure 5
(B)), thinning (→ FIG.5 (c)). The thickness t ₁ of the spacer 17 at this time is t ₁ = t ₂ −2 × (t ₄ −t ₃ ). The spacer 17 is made of a silicon plate, 42a.
It is preferable to use a material that does not easily deform such as an alloy, a copper plate, or an epoxy substrate. However, in consideration of thermal expansion due to heating during wire bonding or molding, the same material as the IC chip is preferable. (For example, a silicon plate.) When it is desired to insulate the IC chips from each other, an epoxy resin or a phenolic insulating potting resin is used as an adhesive instead of using an insulating polyimide tape as in this embodiment. Sometimes. In this case, for the spacer 17, it is preferable not to use a conductive spacer in which a conductive material such as metal or metal powder is mixed for reliable insulation. In this embodiment, IC
Since the chip is fixed to the lead, the position of the IC chip is more stable as compared with the first embodiment.

6A to 6D are sectional views showing a third embodiment of the semiconductor device of the present invention according to claim 3.

In the case of the embodiment shown in FIG. 6, the IC chip A.1,
The tip of each of the IC chips B and 2 is bonded to the leads A and 12 and the leads B and 13 which are depressed in the direction perpendicular to the bonding surface of the IC chip and on the side opposite to the back surface of the bonding IC chip with a polyimide tape. ing. As for the depressing method, the depressed portion may be formed by press-molding with a die that shapes the leads of the semiconductor device after sealing or by etching the leads, but in terms of cost, the shaping method applies. It is better to pressure-form. The dimensional relationship between the depressing depth and the joining means (polyimide tape in this embodiment) will be described below. If the depressing depth of the lead = t _D1 is used and the symbol of the second embodiment is used, 6 (a) is the thickness t of the joining means on the lead side.
₄ > Sectional view when the thickness t ₃ of the joining means on the IC chip side is> 0, FIG. 6B shows t ₂ + 2 × t ₄ > Thickness t ₃ of the joining means on the IC chip side> joining of the lead side 6C is a sectional view when the thickness of the joining means is t ₄ , FIG. 6C is a sectional view when the thickness of the joining means on the IC chip side is t ₃ = t ₂ + 2 × t ₃ , and FIG. The cross-sectional view in the case where the thickness t ₃ > t ₂ + 2 × t ₄ of the side joining means is shown. FIG. 6A shows a case where the thickness t ₄ of the joining means on the IC chip side is smaller than the thickness t ₄ of the joining means on the lead side. In FIG. 6C, the thickness t ₄ of the adhesive on the lead side is a thickness that does not require depressing.
In the case of (b), the depressing amount is between the cases of FIGS. 6 (a) and 6 (c). Further, FIG. 6D shows an example in which the thickness t ₄ of the joining means on the lead side is made thicker than that in the case of FIG. 6C. In the case of the present embodiment, the IC chip is not inclined by setting the depressing depth t _D1 to be t _D1 = t ₂ / 2- (t ₃ -2 × t ₄ ) / 2.

In the case of the present embodiment, since the fixing of the IC chip is stable and neither spacer is used, the mounting cost of the spacer and the parts cost of the spacer are unnecessary, and the cost is reduced accordingly. Will be possible. It is not desirable to make the dimensions as shown in FIG. 6 (d) because the dimension in the vertical direction in the figure becomes large and the thickness becomes large when the resin is sealed. 6C is most desirable because depressing is not required and processing man-hours and die costs can be saved. Then, since the depressing amount can be reduced in the order of (b) and (a), the depressing depth variation of the lead at the time of depressing varies. This is desirable because it reduces the number of wire bonding positions on the lead side and stabilizes the quality.

Next, FIG. 7 is a sectional view showing a fourth embodiment of the semiconductor device of the present invention. In the case where the thickness of the joining means is limited and the lead depressing amount must be reduced. The lead A shown in the third embodiment is
12, the method of using the spacer 17 for preventing the inclination of the IC chip as shown in the second embodiment is shared by depressing the leads B and 13, and the leads A and 12 and the leads B and 12 facing each other are used.
The tips of 13 are mutually depressed in a direction perpendicular to the bonding surface of the IC chip, and the IC chip A.1, IC
The tip B of the chip B.2 is fixed to the tips of the leads A.12 and the lead B.13 by a polyimide tape 6 at one end, and the other end is fixed at the back surface by the polyimide tape 6 via a spacer 17. Depuresu depth t _D2 of this case _{leads, t D2 = t 2/2} + (t 3 -t 4) is a _{+ t 4/2-t 1} /2.

Meanwhile, Depuresu amount t _D1 of the case of not using the spacer are as indicated in the foregoing _{description, t D1 = t 2/2} + t 4/2 + (t 3 -t 4). At this time, in order to reduce the depressing amount by the spacer, t _D2 <t _{D1, and} therefore the equation is solved: −t ₃ <t ₁ <2 × t ₂ −3 × t ₃ + 4 × t ₄ but 0 <t ₁ Since 0 <by the _{t 1 <2 × t 2 -3} × t 3 + 4 × t 4, it is possible to reduce the Depuresu weight compared to Depuresu amount t _D1 of the case of not using a spacer.

[0022]

EFFECTS OF THE INVENTION A plurality of IC chips are fixed with an adhesive, and the IC chips and external output terminals are electrically joined by a conductive joining means such as a gold wire and sealed with a sealing material such as resin. In the semiconductor device, the back surfaces of the IC chips are adhered to each other by a bonding means such as an adhesive or a bonding tape so that the IC chips can be bonded and fixed as compared to the case where a substrate is used for bonding and fixing the IC chips. Because the required thickness can be reduced,
Since the volume of the bonding member occupying inside the package can be made small and thin, there is an effect that unfilling is unlikely to occur at the time of sealing and the package can be made thin while preventing the exposure of the gold wire and the IC chip.

Further, the positions of the IC chips to be bonded are shifted, one end is bonded to the lead, and the bonding surfaces of the ICs are bonded through spacers while balancing the ICs so that the ICs do not incline. Can be fixed more stably (does not become suspended). In addition, the IC chip can be more stably fixed by depressing the IC that joins the shifted ICs so that the IC to which the leads are joined does not tilt, and at the same time the spacers are not used, so the depressing man-hour is high, but the man-hours for mounting the spacer And the parts cost of the spacer can be reduced, and the cost can be reduced. Further, by mounting the spacer on the IC chip bonding surface and sharing the lead depressurization, in addition to the above-described IC chip fixing and stabilization, the depressurization can be reduced by the amount of the spacer, which occurs when the lead depressing becomes deep. This has the effect that variations in the depth of depression can be reduced.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the invention.

FIG. 2 is a perspective view of the internal structure of the first embodiment of the semiconductor device of the present invention.

FIG. 3 is a cross-sectional view for each main manufacturing process relating to an example of the manufacturing method of the first example of the semiconductor device of the present invention.

FIG. 4 is a diagram showing an application of the first embodiment of the semiconductor device of the present invention,
The perspective view of one Example at the time of joining four IC chips.

FIG. 5 is a sectional view of a semiconductor device according to a second embodiment of the present invention.

FIG. 6 is a sectional view of a semiconductor device according to a third embodiment of the invention.

FIG. 7 is a sectional view of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 8 is a sectional view of an example of a conventional semiconductor device.

[Explanation of symbols]

1. IC chip A 2. IC chip B 3. IC chip D 4. substrate 5. Wiring pattern 6. Polyimide tape 7. Gold wire 8. Die pad 9. IC chip E 10. Sealing material 11. Thick polyimide tape 12. Lead A 13. Lead B 14. Gap 15. electrode 16. space 17. Spacer 18. Support pin A 19. Support pin B 20. Support pin C 21. Suction nozzle 22. Transport claw 23. Support pin D 24. Mold 25. IC chip C

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/60

Claims (2)

(57) [Claims] 1. A lead having an external output terminal, a first IC chip and a second IC chip electrically connected to the lead by wire bonding, at least a part of the lead and the first and second IC chips. Second I
A resin for encapsulating a C chip, wherein the first and second IC chips have first and second inactive surfaces .
Is bonded by a bonding means, said Li said first IC chip by a second joining means
It is bonded to the over-de, the Li by the second IC chip third joining means
In the semiconductor device bonded to a card, the first and second IC chips are arranged at positions where they are relatively displaced and overlapped in the direction of the bonding surface, and are directly bonded by the bonding means. Is t2, the thickness of the first joining means is t3, and the thicknesses of the second and third joining means are t4.
The semiconductor device is characterized in that the equation t3 = t2 + 2 × t4 substantially holds. 2. A lead having an external output terminal, a first IC chip and a second IC chip electrically connected to the lead by wire bonding, at least a part of the lead and the first and second IC chips. Second I
A resin for encapsulating a C chip, wherein the first and second IC chips have first and second inactive surfaces .
Is bonded by a bonding means, said Li said first IC chip by a second joining means
It is bonded to the over-de, the Li by the second IC chip third joining means
In the semiconductor device bonded to a card, the first and second IC chips are arranged at positions overlapping with each other with a relative displacement in the direction of the bonding surface, and bonded by the bonding means via a spacer, the thickness of the spacer t1, the lead thickness t2, before
The thickness of the first joining means is t3, the second and
The semiconductor device is characterized in that the equation 2 × t3 + t1 = t2 + 2 × t4 substantially holds, where t4 is the thickness of the joining means of 3 .