JP3374923B2 - Logic module and data processing device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic module having error detecting means, and more particularly, when outputting data on the bus from the inside of the logic module to the outside, by outputting the data excluding the check bit. A logic module that reduces the number of output pins and error-checks this with a check bit in the logic module.
The present invention relates to a data processing device .

[0002]

2. Description of the Related Art In a data processing device, the address information and the data information are transferred in units of a group of a plurality of signal lines which are usually called a bus. In order to check whether the information transferred by this bus is normal or not, a check bit is often added and transferred.

Therefore, when transferring information between logical modules such as a CPU, a memory, and a DMA (direct memory access) controller, a check bit, which is a redundant bit, is often transferred together with a data part. This is effective in increasing the reliability of the transfer information, but the cost is increased because the number of signal lines to be transferred is increased by the amount corresponding to the check bit.

An example of a conventional error detection method will be described with reference to FIG. In FIG. 3, reference numeral 11 is a first logic module such as a one-chip processor that outputs address information and inputs and outputs data information, and may be a combination circuit of logic elements such as MPU or DMA controller. Hereinafter, the CPU 11 will be representatively described.

Reference numeral 12 is a second logic module such as a memory which inputs address information and outputs and inputs data information, which may be a combination circuit of a processor, an MPU and a logic element. Hereinafter, the memory 12 will be representatively described.

Reference numeral 13 denotes an internal address register of the CPU 11, which holds address information to be output to an address bus 18 which will be described later, and which corresponds to the address bus 18.
For example, the size is 18 bits. An output buffer 14 drives the output of the address register 13.

A status register 15 holds an error signal. Reference numeral 16 is an internal address bus output from the address register 13. Reference numeral 17 denotes a parity check unit for checking the normality of address information, for example, for checking odd parity. Reference numeral 18 is an address bus for transferring address information. Reference numeral 19 is a data bus.

The address bus 18 includes 16 signal lines AB00 to AB1 for transferring 16-bit address information body.
5 (not shown) and a parity bit signal line ABP for transferring the odd parity of eight signal lines AB00 to AB07.
0 (not shown), and two signal lines of the odd parity bit signal line ABP1 (not shown) of eight signal lines of AB08 to AB15, a total of 18 signal lines.

All the 18 signals of the address bus 18 are input to the parity check unit 17, and the signal lines AB00 to AB07 and the parity bit signal line ABP are input.
It is checked whether the number of logic "1" of each of the nine signal lines of 0 is an odd number, and the logic of each of the nine signal lines of the signal lines AB08 to AB15 and the parity bit signal line ABP1 is "1". Check if the number of is odd.

If all of these check results are odd, it is judged as a normal state. However, if at least one of the checks is even, it is recognized as an abnormal state, a parity error signal is output, this is reported to the CPU 11, and the error signal is held in the status register 15. When an error is detected in the address information in this way, the data information output from the memory 12 based on the address information is unexpected data, and therefore the CPU 11 operates so as not to receive and process this data. .

[0011]

As described above, in the conventional case, even in the case of a unidirectional bus such as the address bus 18, in order to guarantee the normality of the data corresponding to the address, a parity bit is used. Such a check bit is added to the CPU 11 and output to the outside of the CPU 11 to perform normality check such as parity check.

For this reason, the number of signal lines output from the CPU 11 increases by the amount of check bits, and this first logic module typified by the CPU 11 can be used as an LSI or LSI in which the number of external input / output pins is severely limited. When the printed circuit board is used, the LSI or the printed circuit board may have to be one size larger, resulting in an increase in cost.

Further, it is necessary to dispose a check element such as the parity check section 17 outside the first logic module. Therefore, not only does the cost of the check element itself increase, but if space for placing the check element is not available, a board of one size larger type must be used, and in this case also the total cost increases. It was

Moreover, the error signal detected by a check element such as the parity check section 17 arranged outside is converted into C
A pin for inputting to the first logic element such as the PU 11 is required, and especially in the case of an LSI or a printed board in which the number of external input / output pins is severely limited, a type one size larger must be used. Sometimes it doesn't
I was trying to increase costs.

Therefore, it is an object of the present invention to provide an error detecting method which does not have an external check pin in order to improve the problem caused by the increase in the number of pins.

[0016]

In order to achieve the above-mentioned object, in the present invention, as shown in FIG. 1, a first logic module typified by a CPU 1 includes an address register 3, a buffer 4 and a parity check. The buffer 5 is provided with an output buffer 4-1 and an input buffer 4-2.
To provide. The output of the address register 3 is sent to the internal bus 6-1 which is the signal lines AB00 to AB15 (not shown) of the main body of the address information and the parity signal lines ABP0 and AB.
It is divided into check bit lines 6-2 which are P1 (not shown).

[0017]

The address information output from the output buffer 4-1 is input to the input buffer 4-2. Then, the address information transmitted from the input buffer 4-2 and the check bit output from the address register 3 are transmitted to the parity check unit 5, and for example, odd parity check is performed by these.

As described above, whether or not the address information on the address bus 7 of the second logic module typified by the memory 2 is normal can be checked by the parity check section 5 provided inside the CPU 1. So C
The error can be detected without increasing the number of pins in the first logic module exemplified by PU1.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described with reference to FIG. 2, the same symbols as in FIG. 1 indicate the same parts, 8 is a data bus, and 9 is a status register.

Reference numeral 1 denotes a first logic module such as a one-chip processor which outputs address information and inputs and outputs data information, and may be a combination circuit of logic elements such as MPU or DMA controller. Corresponding to the CPU 11 in. Here, the CPU 1 will be representatively described.

Reference numeral 2 is a second logic module such as a memory which inputs address information and outputs and inputs data information, which may be a combination circuit of a processor, an MPU and a logic element, and corresponds to the memory 2 in FIG. Is.
Here, the memory 2 will be representatively described. Therefore
The CPU 1 and the memory 2 constitute a data processing device.
It

Reference numeral 3 is an address register, and only the address information body not including the check bit is transferred to the internal address signal lines IAB00 to IAB07 and IAB08 to IA.
B15 (both not shown) is output to the internal address bus 6-1 and the check bus 6 of the internal address bus is formed by internal parity bit signal lines IABP0 and IABP1 (both not shown) of the check bit portion. Output to -2. The internal parity bit signal line IABP0 is the internal address signal lines IAB00-IAA.
The check bit for B07 is transmitted,
The internal parity bit signal line IABP1 sends the check bit to the internal address signal lines IAB08 to IAB15.

A buffer 4 has an output buffer 4-1 and an input buffer 4-2. The output buffer 4-1 is
The address information body not including the check bit transmitted from the internal address bus 6-1 is input,
It is converted to a voltage level external to 1 and output to the address bus 7. Further, the input buffer 4-2 converts the output of the output buffer 4-1 having the external voltage level into the internal voltage level of the CPU 1 and outputs it.

Reference numeral 5 denotes a parity check unit, which is a CPU 1
Of the internal address signal lines IAB00 to IAB07 and the internal parity bit signal line IABP0, for example, odd parity check is performed, and the internal address signal lines IAB08 to IAB are checked.
For example, an odd parity check of 15 and the internal parity bit signal line IABP1 is performed, and an error signal is sent to the status register 9 if at least one check is not normal.

Reference numeral 7 denotes an address bus, which transfers only the address information body not including the check bit. Reference numeral 8 is a data bus for transferring data information between the CPU 1 and the memory 2. Reference numeral 9 is a status register for holding an error signal, which corresponds to the status register 15 in FIG.

According to the present invention, as shown in FIG. 2, when the internal address bus 6-1 is output from the CPU 1 to the outside, the address information main body portion other than the parity bit among the bits of the address register 3 is output to the output buffer. An internal address which is output to the address bus 7 outside the CPU 1 via 4-1 and is also input via the input buffer 4-2, and the input address information is not output outside the CPU 1. The parity check unit 5 checks the parity bit transmitted from the bus check bus 6-2.

If an error is detected by this check, the parity check unit 5 will check the status register 9
On the other hand, an error signal is output and error information is set therein, and the CPU 1 determines that the transferred data information from the memory 2 is data output from an undesired address and invalidates it.

Even if the check bit is not output to the address bus 7, there is no problem at all in the case of an element which does not originally have the check bit as an input terminal, such as the memory 2. If only the information of the address main body is output, it is looped back and input through the input buffer 4-2, so that the internal address bus 6-1 fails, the buffer 4 fails, the address bus 7 shorts, etc. Can be detected by the parity check unit 5. In this way, the same reliability as the conventional example shown in FIG.
It can be secured with a small number of pins.

Moreover, the memory 2 originally is an element that does not need a check bit and only needs to input the address main body. Therefore, it is useless to output the check bit of the address as in the prior art, and the check bit is not necessary. If it fails, a parity error will occur due to this unnecessary bit, and the address body will be normal, but
Although an adverse effect such as invalidation of processing has occurred, the present invention can solve such a problem.

In the above description, 1 is set as the address bit.
Although an example of the odd parity check has been described for the case of 6 bits, the present invention is not limited to these.

[0031]

As described above, according to the present invention, it is not necessary to output the check bit of the signal line of the address information output from the logic module, and particularly, the LSI in which the number of external input / output pins is severely restricted. Alternatively, in the case of a printed board or the like, it is possible to avoid having to use a type that is one size larger, resulting in a large cost reduction effect.

Address information outside the logic module
That since the parity may not put the check element such as a check section not only the cost down of the check device itself, if the space for the check element can not be taken by the conventional need to adopt a substrate of one size larger type On the other hand, since it is not necessary to use a substrate of such a size, an overall cost reduction effect can be expected from this aspect as well.

Since the pin required for inputting the error signal of the address information detected by the check element such as the parity check unit outside the logic module to the first logic module is unnecessary, Particularly in the case of an LSI or a printed board in which the number of external input / output pins is severely limited, the cost reduction effect is great because the number of pins is reduced.

In the case of an element such as a memory that does not need a check bit and only needs to input the address body, outputting the check bit as in the prior art is not only wasteful, but also when the check bit itself fails. In addition, it is possible to effectively solve the problem that a parity error occurs due to the unnecessary bits and the processing is invalid even though the address body is normal. Address holding means such as an address register
From the address line of the memory to the address line input of the memory
Increase the output signal and input signal of the LSI chip
Without confusing with data error,
Address errors can be accurately detected with Further check
Check bit from the address holding means with bit
Output only the address part excluding
Output of LSI chip by inputting inside the chip
Signal and input signal are not increased, and memory address
Due to the "0" stack of the address line on the route to the line input
Obstacle, "1" stack failure, short-circuit failure with adjacent signal, etc.
Will be reflected in the wrap-around input, so those error
Check with the check signal together with the reply signal.
The address error can be reliably detected from the result. Only
Also from the address holding means to the address line input of the memory
The error of the address line in the route to the output signal of the LSI chip
And confuse with data error without increasing input signal
Accurately detects address errors with less hardware
Not only possible, but also output signal and input signal of LSI chip
No increase in the number of signals and input to the memory address line
“0” stack failure of the address line of the route, “1” stack
Error address signal such as a failure or short circuit with an adjacent signal
Check result with the original check bit together with the issue
Data processing device that can reliably detect address errors
Can be provided.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a configuration diagram of an embodiment of the present invention.

FIG. 3 is a conventional example.

[Explanation of symbols]

1 First logic module 2 Second logic module 3 Address register 4 buffers 5 Parity check section

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tatsuya Yamaguchi 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa within Fujitsu Limited (72) Inventor Yasutoshi Sakurai 1015 Kamedota, Nakahara-ku, Kawasaki, Kanagawa Within Fujitsu Limited ( 72) Inventor Koichi Odawara, 1015 Kamiodanaka, Nakahara-ku, Kawasaki, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Takumi Nonaka, 1015, Uedotachu, Nakahara-ku, Kawasaki, Kanagawa, Kanagawa Prefecture (72) Inventor Kenji Hoshi, Kanagawa Prefecture 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Fujitsu Limited (72) Inventor Eiji Kanaya 1015, Kamikodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (56) Reference JP-A-1-33649 (JP, A) ( 58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 11/10

Claims (2)

(57) [Claims] 1. A logic module for outputting address information for accessing an external device and inputting / outputting data information, which holds the address information and additional information for detecting an error in the address information. an address holding means for the address information issued read from said address holding means
An output buffer for outputting to the external device, a means for returning address information output from the output buffer to the external device in the logical module, and an input buffer for inputting the returned address information in the logical module. ) Based on the address information output from the input buffer, and additional information corresponding to the address information output from the input buffer read from the address holding means. An error check unit for detecting an error in the address information, and a logic module. 2. A data processing device comprising at least an external device and a logic module for outputting address information for accessing the external device and inputting data information from the external device, wherein the logic module comprises: and said address information, an address holding means for holding and additional information for error detection of the address information, the address information issued read from said address holding means
An output buffer for outputting to the external device, a means for returning address information output from the output buffer to the external device in the logical module, and an input buffer for inputting the returned address information in the logical module. ) Based on the address information output from the input buffer, and additional information corresponding to the address information output from the input buffer read from the address holding means. A data processing device comprising: an error check unit that detects an error in the address information.