JP3370315B2 - Pattern inspection method and apparatus - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a pattern inspection technique,
That is, pattern defect inspection on semiconductor wafers, photomasks, magnetic disks, optical disks, etc., especially V
The present invention relates to a technique effectively applied to a pattern or defect inspection of an integrated circuit device or the like having a periodic pattern and a random pattern in one chip area such as an LSI memory and a CCD (Charge Coupled Device).

[0002]

2. Description of the Related Art Conventionally, as a pattern inspection method, a method of comparing two adjacent chips has been widely used as a photomask or wafer appearance inspection apparatus. Further, as a method of detecting defects on a wafer having a complicated multilayer pattern, a method of performing repeated pattern comparison has been proposed as described in JP-A-59-192943.

In the two-chip comparison inspection, patterns of two adjacent chips are compared with each other. Therefore, in the case of a semiconductor wafer having a multi-layer pattern, fine defects are detected due to differences in the pattern size of the chips and the pattern overlay accuracy. Is difficult. On the other hand, the method of comparing repeated patterns is to compare patterns in the immediate vicinity,
The difference between the patterns to be compared is small, and even fine defects can be detected, but there is a problem that only the repeated pattern portion can be inspected.

By the way, in the case of a wafer pattern to be inspected, the size of the defective defect differs between the fine pattern portion and the relatively thick pattern portion, and therefore the required detection sensitivity also differs.

Therefore, the inventors of the present invention have disclosed in Japanese Patent Laid-Open No. 63-5.
As disclosed in Japanese Patent No. 2434, a method has been proposed in which the detection sensitivity is switched depending on the pattern to be inspected.

Further, as an inspection apparatus for performing both 2-chip comparison and repeated pattern comparison, repeated patterns and random patterns are used.
Wafer visual inspection equipment that can inspect patterns separately is proposed
Has been.

[0007]

However, since the technique disclosed in Japanese Patent Laid-Open No. 63-52434 is premised on the two-chip comparative inspection, the detection sensitivity on a wafer having a multilayer pattern is a problem.

On the other hand, the above-mentioned repeating pattern and random
Wafer visual inspection system that can inspect each pattern separately is iTV
This is to compare images captured by (industrial television), and there is one problem that the inspection speed is slow because the movement of the stage is repeatedly stopped. In addition, since the repeated pattern area and the random pattern area are inspected separately, if there is a non-repetitive pattern in a very small area within the repeated pattern area, even if the area is very small, only that portion is separated into two chips. There is the problem of having to compare.

Therefore, in the above-mentioned prior art, it is not considered to solve the improvement of the detection sensitivity and the improvement of the inspection speed at the same time.

An object of the present invention is to provide a pattern defect inspection technique capable of simultaneously improving detection sensitivity and inspection speed.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0012]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

[0013] That is, pattern detection査方method and apparatus of the present invention, generally in the memory cell area of the fine memory patterns or, CCD, MiD (Mos Image Device ) such repeated pattern portion including the light receiving region of the light sensing element ,
By inspecting the peripheral circuit section with separate circuits, the repetitive pattern section can be applied to the repetitive pattern comparison inspection with relatively high detection sensitivity, and the effective stage is continuously scanned for high-speed inspection. While inspecting, the defect outputs of chip comparison and repeated pattern comparison do not overlap based on each inspection area data created based on the pattern arrangement information in the chip, and high-speed inspection is also possible. It is supposed to be. Further, Pa <br/> terpolymers emissions test査方method of the present invention compares the chip comparison test for comparing the pattern of 2 adjacent chips on the object to be inspected, the same pattern with each other in the same repetitive pattern portion in the chip a repetitive pattern comparison inspection, while continuously reading an image, the chip comparison inspection, a repetitive pattern comparison inspection, it
The chips are run in parallel using different thresholds.
The outputs of the comparison inspection and the repeated pattern comparison inspection are separately calculated.
Taken into a computer and obtained by both comparison tests in the computer
Compare the inspection result with the preset inspection condition,
Only the inspection results that exceed the preset inspection conditions
It is what is left as a fruit . Further, pattern inspection <br/>査apparatus of the present invention includes a first comparator circuit for comparing two chip pattern of adjacent on the object to be inspected, a comparison result of the comparison circuit of the first the first If the threshold value is equal to or more than the threshold value, the first thresholding circuit that outputs the defect candidate, the second comparison circuit that compares the same patterns of the same repeated pattern portion in the chip, and the comparison result of the second comparison circuit are A second thresholding circuit that outputs a defect candidate if the threshold value is equal to or greater than 2 and enables both comparison circuits to operate in parallel while continuously reading an image . Comparison of 1
The circuit outputs the defect, and the repeated pattern part
It is controlled to output the defect of the second comparison circuit . Further, another pattern inspection apparatus of the present invention is
The first to compare the patterns of two adjacent chips on a specimen
The comparison result of the comparison circuit and the first comparison circuit is a first threshold value.
First thresholding circuit for outputting as a defect candidate if the above
When, etc. identical patterns of the same repetitive pattern portion in the chip
A second comparison circuit for comparing cattle and a second comparison circuit
Output as a defect candidate if the comparison result is greater than or equal to the second threshold
Second thresholding circuit for continuously reading images
While operating both comparison circuits in parallel,
The pattern of two adjacent chips above and the same repetition within the chip
One-dimensional optical line scanning the same pattern in the pattern
Has a sensor to detect defects while continuously scanning the stage
Is to do. Furthermore, another pattern inspection of the present invention
The device compares the patterns of two adjacent chips on the inspection object.
First comparison circuit to be compared and comparison result of the first comparison circuit
Is greater than or equal to the first threshold, the first candidate is output as a defect candidate.
Threshold circuit and the same repeating pattern part in the chip
A second comparison circuit for comparing one pattern with each other;
If the comparison result of the comparison circuit is equal to or more than the second threshold
And a second thresholding circuit for outputting as a complement,
It is possible to operate both comparison circuits in parallel while reading the image.
If the detected defect is a defect in the two-chip comparison inspection,
It may be displayed by distinguishing whether it is a defect in the return pattern comparison inspection.
Is what is output.

According to the above-mentioned means, a portion such as a memory cell in a wafer where a fine pattern is formed, which requires a high-sensitivity inspection, can be inspected with a high sensitivity, and is relatively large like the periphery of the chip. The pattern portion can be inspected with relatively low sensitivity, the defect can be detected with the detection sensitivity according to the fineness of the pattern in the chip, and the above-described object of providing a pattern defect inspection apparatus capable of high-speed inspection can be achieved. It is a thing.

[0015]

1 is an explanatory diagram showing an example in which a pattern defect inspection apparatus of the present invention is applied to a wafer appearance inspection.

In this pattern defect inspection apparatus, a semiconductor wafer 3 fixed on a wafer mounting table 2 on a stage 1 composed of an XY table is sequentially moved in the X and Y directions by the stage 1, and a pattern defect on the wafer 3 is detected. Is configured to inspect.

The light from the illumination light source 4 located above the wafer 3 is irradiated through the half mirror 5 and the objective lens 6, and the reflected light from the wafer 3 is magnified by the objective lens 6 so that the one-dimensional optical element is formed. The light is focused on (a line sensor such as a one-dimensional CCD) 7. The electrical output of the one-dimensional optical element 7 is passed through a signal processing circuit 8 that amplifies the signal or adjusts the signal level, and then AD (analog / digital).
The converter 9 converts the multi-gradation grayscale signal.

This multi-grayscale grayscale signal is stored in a chip delay memory 10 which stores an image signal for one chip.
A comparator 12 calculates a difference between a signal output by the chip delay memory 10 with a delay of one chip and a signal that is not delayed, and a threshold value register circuit 13 stores a predetermined density difference threshold value in a threshold value register 18. When compared with the set value, if there is a gray level difference equal to or greater than the threshold value, it is output as a defect candidate signal from the thresholding circuit 13.

This signal is supplied to the chip comparison inspection output control circuit 1
The defect size determination circuit 15 stores defects in a predetermined size or larger in the inspection result memory 16 only when the defect output is possible by 4. The defect information stored in the inspection result memory 16 can be read by the computer 23. The above is the flow up to the defect output of the chip comparison inspection.

Next, the flow up to the defect output of the repeated pattern comparison inspection will be described. The process up to the output of the AD converter 9 in FIG. 1 is the same as the chip comparison inspection. One of the outputs of the AD converter 9 is stored in the repetitive pattern delay memory 11 (or the unit cell delay memory) which stores the image data for the repetitive pitch of the pattern. A comparator 12 'takes a difference between a signal output with a delay of one repetition of the pattern by the repetitive pattern delay memory and a signal which is not delayed, and a thresholding circuit 13' sets a predetermined gray level difference threshold to a threshold value. It is compared with the set value of the circuit 13 ', and if there is a gray level difference equal to or more than the threshold value, the defect candidate signal is output from the thresholding circuit 13'.

This signal is output only when a defect output is possible by the repetitive pattern comparison inspection output control circuit 14 ', and the defect size judgment circuit 15' stores defects having a certain size or more in the inspection result memory 16 '. It The defect information stored in the inspection result memory 16 'can be read by the computer 23.

Since data can be independently set from the computer 23 in the density difference threshold registers 18 and 18 'for judging the defect detection, it is possible to use different thresholds for chip comparison and repeated pattern comparison. .

Since the defect size setting registers 17 and 17 'for setting the threshold of the defect size can independently set the data from the computer 23, the defect detection sizes of the chip comparison and the repeated pattern comparison can be made different. It is possible.

Reference numeral 21 is a line sensor position counter for calculating the number of bits in the scanning direction of the line sensor which is the one-dimensional optical element 7, and 19 is a line for storing whether each bit of the line sensor is inspectable or not in the chip comparison inspection. A sensor inspection enable / disable bit memory, and 19 'is a line sensor inspection enable / disable bit memory that stores whether each bit of the line sensor is inspectable or not in repeated pattern comparison. Data can be written from the computer 23 to these line sensor inspection availability bit memories 19 and 19 '.

Reference numeral 22 is a coordinate counter in the scanning direction of the stage. Reference numerals 20 and 20 'denote in-chip inspection availability region data memories that store inspection availability regions in the stage scanning direction for chip comparison and repeated pattern comparison, respectively. Data can be written from the computer 23 to these in-chip inspection availability region data memories 20 and 20 '. The output of each of the data memories 19, 19 ', 20, 20' is sent to the inspection output control circuit 14, 14 ', and the defect output for chip comparison and the defect output for repeated pattern comparison are distinguished.

Next, the concept of the division between the chip comparison area and the repeated pattern comparison area will be described with reference to FIGS. 2, 3 and 4.

FIG. 2 shows an example of a semiconductor memory chip. Areas 1 to 4 in FIG. 2 are repetitive pattern portions, that is, memory cell portions, and the other portions are random pattern portions, that is, peripheral circuit portions.

When a chip as shown in FIG. 2 is inspected by a line sensor, as shown in FIG. 3, the inside of the chip is divided into regions 1 to 8 in the figure with an effective inspection width (W in the figure) of the line sensor. Split into. That is, when performing the inspection, first, the comparison inspection of only the region 1 of each chip in the wafer is performed, and after the comparison inspection of the region 1 is completed, the comparison inspection of regions 2 to 8 is sequentially performed.

In this case, as an example, if an image is captured at 0.25 μm / bit using a 1024-bit one-dimensional line sensor, W will be about 250 μm.

As an example, FIG. 4 will be used to explain the inspection enable / disable area for chip comparison and repeated pattern comparison when inspecting the area 1 in FIG. In FIG. 4, the shaded area is the repeated pattern area. Further, in the area where the chip comparison inspection is performed in FIG. 4, CPXS1 ≦ X ≦ CPPXE1 and Y is C in the drawing.
The area is marked with the shaded area. The region where repeated pattern comparison is performed is CLXS1 ≦ X ≦ CLXE1 or CLX
In S2 ≦ X ≦ CLXE2, Y is the area B in the figure.

An embodiment for realizing this area control will be described with reference to FIGS.

FIG. 5 is a diagram showing a circuit configuration for controlling the inspection enable / disable bit in the scanning direction (Y) of the line sensor. A line sensor position counter 21, which indicates the number of the bit of the line sensor that performs continuous scanning, stores an inspection possibility bit memory 19, 1 in which each bit of the line sensor stores inspection possibility.
9 '(19 is for chip, 19' is for repeating pattern) is designated, and whether the output (signal A, signal B in FIG. 5) of each memory of the bit memories 19 and 19 'is 1 or 0. Determine whether the inspection is possible.

Next, FIG. 6 is a diagram showing a portion of the inspection area data control circuit in the scanning direction of the stage.

In FIG. 6, reference numerals 22 and 22 'are coordinate counters in the scanning direction of the stage, but since the inspection area is in units of chips, it is assumed that the coordinates within the chip are counted, and depending on the scanning direction of the stage. It is reversible. Reference numerals 20-1 to 20-6 and 20'-1 to 20'-6 in FIG. 6 denote in-chip inspectable area data memories 20 and 20 'in FIG.
This is a detailed illustration of the part.

Numerals 20-1 and 20'-1 are counters indicating the inspection areas, which are reversible depending on the stage scanning direction, and an initial value can be written from the computer 23. 20-2 is the start coordinate of the X inspection area for chip comparison,
That is, in the example of FIG. 4, the memory stores CPXS1. Reference numeral 20-3 is a memory that stores the end coordinates of the chip comparison X inspection area, that is, CPXE1 in the example of FIG. In this example, the X inspection area is only one area, but a plurality of areas can be set to increase versatility.

The memory addresses of 20-2 and 20-3 are
The read address is designated by the counter 20-1 indicating the number of the inspection area. Reference numerals 20-4 and 20-5 are comparators, which are a coordinate counter 22 and an inspection area start coordinate (20
-2) and the inspection area end coordinates (output of 20-3) are respectively compared. 20-6 is a flip-flop,
For example, the output of the comparator 20-4, that is, the output of the comparator 20-5, which is set depending on whether or not the inspection area is entered,
In other words, the output signal C is reset depending on whether the inspection area is finished or not, and this output signal C becomes a control signal.

In FIG. 6, elements 22 ', 20'-1 to 22'-
The configuration and function of 20'-6 are the elements 22, 20-1 and 20-2 described above.
Same as 0-6, and for comparison of repeated patterns. Two
In the example of FIG. 4, CLXS1 and CLXS2 are stored in 0'-2. At the end coordinate 20'-3, CL is used in the example of FIG.
XE1 and CLXE2 are stored. Flip flop 2
The output signal D of 0'-6 becomes a control signal in the stage scanning direction for comparison of repeated patterns.

Next, what kind of logic is used for the signals A, B, C and D shown in FIGS.
4, 14 'will be described.

[0039] Then, the repetitive pattern comparison inspection output control circuit 14 '
In the case of, It should be so.

In the case of the chip comparison inspection output control circuit 14,

[0041]

[Equation 1] It should be so.

FIG. 7 shows the comparator 12 of the chip comparison inspection circuit.
It is a circuit block diagram which shows the detail of the internal process of (FIG. 1). In the figure, reference numerals 24 and 25 denote differentiators that perform digital second-order differentiation to emphasize a step portion and the like, and 26 and 27.
Is a comparator that outputs only a differential signal having a certain threshold value or more as a binary signal “1” and the other signals as “0”, and 91 is a differential threshold value setting circuit that sets a threshold value for them.
Or 33 are 4-bit shift registers, 3 respectively
Reference numeral 4 or 37 is an X-direction signal delay circuit for delaying one line of the line sensor 7, 28 is the same timing as the two delay circuits 34 and 35 and the shift registers 30, 31 for timing adjustment. Timing matching circuit in which bit shift registers are connected in series, 38 or 42 is a coincidence detecting circuit which outputs "1" only when two input binary signals coincide, 43 or 47 counts the number of coincidences, and the data , 48 is a position adjusting circuit (or timing shift circuit) for shifting the current detection image signal based on the coincidence data so that the coincidence rate becomes the highest, and 49 is a circuit for detecting the current detection image signal and the chip delay image signal. Subtractors for taking the difference, 92 and 93 hold the image data until the alignment is completed A buffer memory.

FIG. 9 is a circuit block diagram showing details of the internal processing of the comparator 12 '(FIG. 1) of the repeated pattern comparison / inspection circuit. In the figure, reference numerals 24 'and 25' denote differentiators for executing digital second-order differentiation and emphasizing step portions and the like.
6'and 27 'are certain thresholds (the threshold is 2
(Compatible independently of 7) Comparator that outputs only the above signals as a binary signal "1" and the other signals as "0", 91 '
Is a differential threshold value setting circuit for setting a threshold value for them, 2
9'or 33 'is a 4-bit shift register, 34' or 37 'is an X-direction signal delay circuit for delaying one line of the line sensor 7, 28' is a timing register of 34 'and 35' for timing adjustment. A timing matching circuit in which two delay circuits and shift registers 30 ', 31, etc. are connected in series with 2-bit shift registers operating at the same timing, and 38' or 42 'is "only when two input binary signals match". 1'outputs a coincidence detection circuit, 43 'or 47' counts the number of coincidences and outputs the data, 48 'makes the current detection image signal have the highest coincidence rate based on the coincidence data. An alignment circuit for shifting, 49 'is a subtracter for obtaining the difference between the present detection image signal and the cell delay image signal, and 92' and 93 'are for the alignment. It is a buffer memory that holds image data until completion.

FIG. 8 is a wafer top view for explaining the defect inspection of the semiconductor memory wafer. In the figure, 7
2 is a scribe line, 71E is a previously scanned memory chip area, 71F is the currently scanned chip area, 71G is the next scanned chip area, 51
Reference numerals 52 and 52 are memory cell mat areas having a repeating pattern, 55 and 56 are peripheral circuit portions having a random pattern, 57 is an Al power supply trunk wiring band having a width of about 50 μm to 100 μm, and 61, 63 and 68 are shown in FIG. The same scanning bands as the areas 1 to 8, 61Q, 63H to 6
3K and 68Q are alignment unit areas of the respective scanning bands. The size of this alignment unit area is about 0.25 μm for the pixel size, and 256 μm for the Y axis direction (extending direction of the line sensor) and about 64 μm for the X direction when the line sensor is 1024 bits.

Next, the alignment operation will be described with reference to FIGS. 7 and 8. Here, an Al wiring pattern will be described as an example. For example, in the case of a 4-Mbit DRAM, the fatal defect size is generally different between the cell part and the peripheral part, so that the minimum defect size in the defect size setting registers 17 and 17 'must be different from each other.

Further, the size of the hillock which becomes noise for defect detection is generally different between the thin Al wiring in the cell region and the wide wiring such as the peripheral Al main wiring 57 in many cases. Therefore, the previous 4M bit DR
In the case of AM, the minimum defect size for chip comparison is 0.75μ
m, the minimum defect size for repeated pattern comparison is set to 0.5 μm.

As described above, the present apparatus performs the defect determination in real time while continuously reading the image so that the wafer is filled with the scanning band having a width of 256 μm. In this continuous image reading and defect determination, it is necessary to perform alignment of the reference read image and the inspected read image in real time at many points on the scan path. Therefore, for example, taking the scanning band 63 as an example, the scanning band is subdivided into unit alignment regions 63H to 63K and the alignment is performed for each region. On the other hand, in the cell comparison, the length of the alignment unit area in the X direction is the repeat unit length or an integral multiple thereof. Other than that, the differential threshold, threshold circuit 13 ', defect size setting register 17'
The parameters are completely the same except that each parameter can be set independently of the chip comparison circuit. That is, in the image data of each registration unit area, the pattern step is emphasized by the differential operation, and the same step emphasis pattern as the reference is digitally compared, and they are best matched in each registration unit area. As described above, the alignment circuit (or timing shift circuit) 48, 48 'shifts or aligns on the memory, and outputs the difference signal to the subtractor or subtractor 49, 49' in that state, and outputs the difference signal. It

As described above, since the image reading, the chip comparison and the cell comparison, and the judgments thereof are always executed in parallel and the comparison specifications to be output are selected depending on the inspection area, any pattern can be selected. However, accurate alignment can be achieved.

Further, since various parameters of a plurality of inspection circuits can be set independently, it is possible to perform high-speed inspection of a complicated pattern such as a semiconductor memory having different defect parameters in each area.

The invention made by the present inventor has been described above based on the embodiments, but the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, in the above embodiment, the output of each comparison inspection is controlled by hardware, but the detected defect is divided into a repeated pattern portion and a random pattern portion based on the coordinates within the chip, It is processed by software so that defective data does not overlap. Alternatively, the threshold of the defect size can also be determined by software using coordinates.

Further, when the inspection conditions for the two-chip comparison and the inspection conditions for the repeated pattern comparison are different, the computer 23
It is also possible to discriminate which comparison circuit the output is from by a software process inside and add this discrimination result data to the inspection result data. This makes it possible to determine that the inspection results have different inspection conditions. For example, a large amount of inspection result data for a large number of wafers can be collected and statistically analyzed by other computers such as the distribution of defect sizes. In case of processing, it can be processed separately.

The above-mentioned invention has been described in the case where the invention made by the present inventor is applied to the wafer appearance inspection apparatus which is the field of application which is the background of the invention. However, the invention is not limited thereto and, for example, a photomask, It can also be applied to appearance inspection devices for liquid crystals and disks. Further, it can also be applied to a foreign matter inspection device that performs a comparison inspection.

[0054]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
It is as follows.

That is, in visual inspection of a wafer or the like, the detection sensitivity can be appropriately set depending on the position in the chip,
In addition to optimizing the defect detection sensitivity, chip comparison and repeated pattern comparison can be inspected at the same time, so the inspection can be speeded up. In other words, according to the present invention, it is possible to improve the detection sensitivity and the inspection speed in the pattern defect inspection.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing an embodiment in which the present invention is applied to a wafer visual inspection.

FIG. 2 is a diagram showing an example of a chip.

FIG. 3 is an explanatory diagram of dividing a chip into scanning width units of a line sensor.

FIG. 4 is an explanatory diagram showing a region of each comparative inspection by removing one region of FIG.

FIG. 5 is an example of a circuit configuration that controls an inspection possibility bit in the scanning direction of the line sensor.

FIG. 6 is a circuit configuration diagram for controlling an inspection area in a stage scanning direction.

FIG. 7 is a circuit block diagram showing details of internal processing of a comparator (chip comparison side).

FIG. 8 is a wafer top view showing a layout of an upper main surface of a semiconductor memory device wafer to be inspected.

FIG. 9 is a circuit block diagram showing details of internal processing of a comparator (repeating pattern comparison or cell comparison side).

[Explanation of symbols]

1 ... Stage, 2 ... Wafer mounting table, 3 ... Wafer, 4 ... Illumination light source, 5 ... Half mirror, 6 ...
..Objective lens, 7 ... One-dimensional optical element (line sensor), 8 ... Signal processing circuit, 9 ... AD converter, 1
0 ... Chip delay memory, 11 ... Repeat pattern delay memory, 12, 12 '... Comparator, 13, 13'
... Thresholding circuit, 14 ... Chip comparison inspection output control circuit, 14 '... Repeated pattern comparison inspection output control circuit, 15 ... Chip comparison defect size determination circuit, 15'
... Repeated pattern comparison defect size judgment circuit, 16.
.... Chip comparison inspection result memory, 16 '... Repeated pattern comparison inspection result memory, 17 ... Chip comparison defect size setting register, 17' ... Repeated pattern comparison defect size setting register, 18 ... Chip comparison Grayscale difference threshold register, 18 '... Repeat pattern comparison grayscale threshold register, 19 ... Chip comparison line sensor inspection enable / disable bit memory, 19' ... Repeat pattern comparison line sensor inspection enable / disable bit memory, 20 ... In-chip inspection availability area data memory for chip comparison, 20 '...
In-chip inspection availability area data memory for repeated pattern comparison, 20-1 ... Chip comparison inspection area counter, 20'-1 ... Repeated pattern comparison inspection area counter, 20-2 ... Chip comparison X inspection area start coordinates, 20'-2 ... Repeated pattern comparison X inspection area start coordinates, 20-3 ... Chip comparison X inspection area end coordinates, 20'-3 ... Repeated pattern comparison X inspection area end coordinates, 20-4 ... Coordinate comparator, 20'-4.
..Coordinate comparison, 20-5 ... Coordinate comparator, 20'-5
... Coordinate comparator, 20-6 ... Flip-flop,
20'-6 ... Flip-flop, 21 ... Line sensor position counter, 22, 22 '... Stage scanning direction coordinate counter, 23 ... Calculator, 24, 24',
25,25 '... Differentiator, 26,26'27,27'
... Comparator, 28, 28 '... Timing matching circuit,
29, 29 'to 33, 33' ... Shift register, 3
4, 34'-37, 37 '... X-direction signal delay circuit,
38, 38 'to 42, 42' ... Match detection circuit, 4
3,43 'to 47,47' ... Counter, 48, 4
8 '... alignment circuit (timing shift circuit),
49, 49 '... Subtractors (differential devices) 51, 52 ...
Memory cell mat area, 55, 56 ... Peripheral circuit section, 57 ... Al trunk wiring, 61, 63, 68 ... Scanning band, 61Q, 63H, 63I, 63J, 6
3K, 68Q ... Alignment unit area, 71E ...
Memory chip area, 71F, 71G ... Chip area,
72 ... scribe line, 91, 91 '... differential threshold value setting circuit, 92, 92', 93, 93 '... buffer memory.

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yoshikazu Hori 3-3 Fujibashi, Ome, Tokyo 2-3 Hitachi Tokyo Electronics Co., Ltd. (72) Takahiro Kamagata 3-3 Fujibashi, Ome, Tokyo 2 Hitachi Tokyo Electronics (56) References JP 63-126242 (JP, A) JP 1-202607 (JP, A) JP 63-134940 (JP, A) JP 3187827 (JP, B2) (58) ) Fields surveyed (Int.Cl. ⁷ , DB name) G01N 21/84-21/958 H01L 21/64-21/66

Claims (7)

(57) [Claims] 1. A chip comparison inspection for comparing patterns of two adjacent chips on an object to be inspected and a repeated pattern comparison inspection for comparing the same patterns of the same repeated pattern portion in a chip are continuously read as images. While doing
Chip comparison inspection, a repetitive pattern comparison inspection, respectively
The chip comparison performed in parallel using different thresholds
Separate output of inspection and repeated pattern comparison inspection
Obtained by the above two comparison tests in the computer.
Compare the inspection results and the preset inspection conditions,
Only those that exceed the preset inspection conditions are considered as inspection results
A pattern inspection method, which is characterized by leaving it. 2. A first comparison circuit for comparing patterns of two adjacent chips on an object to be inspected, and a comparison result of the first comparison circuit is output as a defect candidate if the comparison result is equal to or more than a first threshold value. A thresholding circuit of No. 1 and a second comparing circuit for comparing the same patterns of the same repeating pattern section in the chip;
If the comparison result of the second comparison circuit is greater than or equal to the second threshold value, the second comparison circuit has a second thresholding circuit that outputs a defect candidate, and both comparison circuits can operate in parallel while continuously reading an image. And the random pattern portion in the chip is the first
Defects are output by the comparison circuit, and the repeated pattern part
The pattern inspection apparatus is controlled so as to output a defect of the second comparison circuit . 3. The pattern inspection apparatus according to claim 2 , wherein the detected defect is displayed or output by distinguishing between a defect in the two-chip comparison inspection and a defect in the repeated pattern comparison inspection. . 4. An adjacent two-chip putter on an object to be inspected.
And a ratio of the first comparison circuit for comparing
If the comparison result is greater than or equal to the first threshold value, it is output as a defect candidate.
The same thresholding circuit as the first thresholding circuit in the chip
A second comparison circuit for comparing the same patterns of the parts,
If the comparison result of the second comparison circuit is greater than or equal to the second threshold,
A second thresholding circuit for outputting as a defect candidate,
Operate both comparison circuits in parallel while continuously reading images.
It is possible to have a one-dimensional optical line sensor that scans the pattern of two adjacent chips on the object to be inspected and the same pattern of the same repeated pattern portion in the chip, and perform defect detection while continuously scanning the stage. It features and be Rupa turn inspection apparatus. 5. Based on the pattern arrangement information in the chip,
Each of the scanning direction of the one-dimensional optical line sensor and the scanning direction of the stage from the start point of the chip has a storage unit that stores the data of the chip comparison inspection area and the repeated pattern comparison inspection area. 5. The pattern inspection apparatus according to claim 4, wherein the output of the defect output of the two-chip comparison inspection or the defect output of the repeated pattern comparison inspection is controlled in synchronization with each other. 6. The pattern inspection apparatus according to claim 4 , wherein the detected defect is displayed or output by distinguishing between a defect in the two-chip comparative inspection and a defect in the repeated pattern comparative inspection. . 7. A putter of two adjacent chips on an object to be inspected.
And a ratio of the first comparison circuit for comparing
If the comparison result is greater than or equal to the first threshold value, it is output as a defect candidate.
The same thresholding circuit as the first thresholding circuit in the chip
A second comparison circuit for comparing the same patterns of the parts,
If the comparison result of the second comparison circuit is greater than or equal to the second threshold,
A second thresholding circuit for outputting as a defect candidate,
Operate both comparison circuits in parallel while continuously reading images.
Possible and then the detected defect, 2 or defects in the chip comparison test, the repetitive pattern comparison inspection characteristics and to Rupa turn inspection apparatus that was set to be displayed or output by distinguishing whether defects in the.