JP3351217B2 - Digital signal processing device and digital signal processing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

Relates to an apparatus and method of the present invention records the signals of different signal format BACKGROUND OF THE INVENTION The digital signal processing apparatus and for recording processes in particular compressed signal
About the method .

[0002]

2. Description of the Related Art A recording / reproducing apparatus for transmitting a bit-compressed signal and recording the received compressed signal as it is is described in, for example, JP-A-4-79588. For advanced compression technology, see MPEG (Moving Picture Expert Gr.
A method called ope) is known. The MPEG system is a system for transmitting a difference signal with respect to a reference frame using correlation between frames. For this reason, the data amount (the number of bits) differs for each frame.

[0003] Transport streams and program streams are also known as systems for transmitting data signals compressed by the MPEG system. The transport stream is mainly used when digitally broadcasting a signal compressed by the MPEG method. On the other hand, the program stream is used when recording and reproducing a signal compressed by the MPEG method on a storage device such as an optical disk.

[0004]

However, a method for recording and reproducing a program stream signal reproduced on an optical disk, a hard disk device, or the like with a video tape recorder has not yet been disclosed.

[0005] An object of the present invention is to represent MPEG or the like.
An object of the present invention is to provide a device capable of expanding a signal which is a signal compressed by a variable rate compression method but has a different signal format. Furthermore, when a signal compressed by a variable rate compression method typified by MPEG or the like is reproduced from a storage device such as a disk device whose reproduction speed can be controlled, a device capable of efficiently recording with a video tape recorder is provided. That's right. Furthermore, compressed signals reproduced by a VTR or compressed signals digitally broadcast can be stored on a hard disk,
An object of the present invention is to provide a device that can efficiently record data on an optical disk or the like.

[0006]

According to the present invention, a video signal or the like is provided.
Or a digital compressed signal obtained by compressing an audio signal , a transport stream including a reference signal synchronized with the video signal or the audio signal, and a video signal or an audio signal which is compressed.
And a clock signal generating means for generating a first clock signal synchronized with a video signal based on the reference signal, and a clock for generating a stable second clock signal. Signal generating means, switching means for switching and selecting between the first clock signal and the second clock signal, and switching
Digital compression based on clock signal selected by means
Provided a decompression means for decompressing the signals, uses the first clock signal when decompressing the compressed digital signal included in the transport stream, when decompressing the compressed digital signal included in the program stream of the second A clock signal is used.

Further, in a digital signal processing device for processing a digital compressed signal reproduced from the storage means and generating a signal for recording on a bit stream recording medium, the signal reproduced from the storage means is a digital compressed signal.
A program stream containing items, converting means for converting the program stream into a transport stream packet format, to packet signals constituting the converted transport stream, time relative time information to be transmitted in the packet signal And a packet to which relative time information is added by the adding unit.
The signal is a recording signal to be recorded on a bit stream recording medium.

Furthermore also the compressed digital signal and the video signal or audio signal compressed video signal or audio signal
It consists of a packet format signal containing a reference signal synchronized with
The inputted transport stream, the digital pressure
A digital signal processor for recording a compressed signal in a storage unit , a clock signal generation unit for generating a clock signal synchronized with a video signal based on a reference signal, and a conversion unit for converting a transport stream into a program stream Means, and buffer means for temporarily storing the converted program stream, and outputting the output signal of the buffer means.
And to record in the storage means.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described with reference to FIG. 1, 10 is a storage device, 20 is an interface circuit, 30 is a memory, 40 is a decoder, 50
Is an interface circuit, 60 is a receiver, 70 is a bit stream recording / reproducing device, 80 is a bus, 90 is an antenna,
100 system controller and 110 are digital signal processing devices. FIG. 2 is an embodiment showing details of the decoder 40 and the interface circuit 50. In FIG.
410 is a buffer circuit, 420 is a decompression circuit, 430 is a display control circuit, 440 is a crystal oscillator, 450 and 46
0 is a switching circuit, 510 is a tuner circuit, 520 is a demodulation circuit, 530 is an error correction circuit, 540 is a selection circuit,
50 is a clock generation circuit, 560 is a conversion circuit between a program stream and a transport stream, 570 is a time stamp addition / removal circuit, and 580 is a switching circuit.

In this embodiment, it is assumed that the storage device 10 is, for example, an optical disk drive device that can reproduce at least a video signal and an audio signal compressed by the MPEG system in a program stream. The storage device 10 may have a function of recording a video signal and an audio signal compressed by MPEG. Further, a hard disk drive (magnetic disk drive) may be used instead of the optical disk drive.

First, a case where a signal reproduced from the storage device 10 is expanded by the decoder 40 and viewed by the image receiver 60 will be described. The signal reproduced from the storage device 10 is input to the interface circuit 20. The interface circuit 20 converts the reproduced signal into a predetermined packet length, and
0 to the memory 30. The decoder 40 includes at least the buffer circuit 410 and the crystal oscillator 44
In this case, the switching circuit 450 is connected to the terminal A and the switching circuit 460 is connected to the terminal B, and the expansion circuit 420 expands the compressed signal using the oscillation clock of the crystal oscillator 440 as a reference clock. Upon expansion, the signal from the memory 30 is stored in the buffer circuit 410 of the decoder 40 via the bus 80 as necessary, and the signal from the buffer circuit 410 is expanded by the expansion circuit 420. When the amount of data stored in the buffer circuit 410 in the decoder 40 exceeds a predetermined value, the input of data from the memory 30 is suspended, and conversely, the buffer circuit 410
If the amount of data in the memory falls below a predetermined value, the memory 30
Input data from. In this way, the data from the storage device 10 can be expanded without excess or deficiency based on the clock signal from the crystal oscillator 440. With the above operation, the system controller 100 performs control of the bus 80, writing and reading control to the memory 30 and the buffer circuit 410, switching control of the switching circuits 450 and 460, and the like.

The video and audio signals expanded as described above are display-controlled by the display control circuit 430, and
0 is input and the user can appreciate it.

Next, a description will be given of a case where a program received while the signal received by the antenna 90 is expanded by the decoder 40. Although not shown in FIG. 1, it is assumed that the program includes at least a video signal and an audio signal, and the program is compressed and transmitted (broadcast) from a broadcasting station, and is received by the antenna 90. In transmission, it is assumed that a so-called transport stream of the MPEG system is being transmitted.

The signal received by the antenna 90 is input to the interface circuit 50. Interface circuit 50
2 shows a tuner circuit 510 and a demodulation circuit 5 as shown in FIG.
20 and an error correction circuit 530. Tuner circuit 5
At 10, the reception band is adjusted so as to receive a signal including the program to be viewed. The demodulation circuit 520 demodulates the received signal, and the error correction circuit 530 corrects an error generated during transmission. The error-corrected signal is a so-called transport stream signal. The transport stream signal corrected by the error correction circuit 530 can include a plurality of programs. If necessary, the video signal, the audio signal, the program guide information, the conditional access information, and the like of the program to be viewed. Is selected by the selection circuit 540. Further, the interface circuit 50 generates a reference clock signal based on clock reference information called a program clock reference (PCR) or a system clock reference (SCR) which is obligated to be added to the transport stream. It has a clock signal generation circuit 550. Since the reference information is synchronized with the program selected for reception, the packet signal of the program selected by the selection circuit 540 is transmitted to the clock generation circuit 5.
By inputting to 50, a clock signal synchronized with the program selected for reception can be obtained. The clock signal generated by the clock signal generation circuit 550 and synchronized with the program selected for reception is input to the decoder 40. In this case, the switching circuit 580 is connected to the terminal A, the switching circuit 460 is connected to the terminal B, and the switching circuit 450 is connected to the terminal B.

The transport stream packet of the program selected by the selection circuit 540 is converted into a program stream packet by the conversion circuit 560, and the bus 80 is transmitted in the same packet signal format as when reproduced from the storage device 10.
Is input to the decoder 40 via the.

In the decoder 40, the switching circuit 450 is connected to the terminal B, and the switching circuit 460 is connected to the terminal B. The clock signal input from the interface circuit 50 is selected and input from the bus 80 via the buffer circuit 410. The video signal and the audio signal are expanded by the expansion circuit 430. Since the clock signal used here is synchronized with the selected program, even if the video signal and the audio signal packet of the program are unilaterally input from the antenna 90, there is no excess or deficiency of data. The demodulated video signal and audio signal are display-controlled by the display control circuit 430 and input to the receiver 60.

Next, a case where a signal input from the antenna 90 is recorded by the bit stream recording / reproducing apparatus 70 will be described. Also in this case, the received program is expanded by the same operation as described above, and can be viewed on the receiver 60. In the interface circuit 50, relative time information (time stamp) indicating the arrival time of the packet is added to each packet of the bit stream of the program selected by the selection circuit 540 by the time stamp addition / removal circuit 570. The packet to which the time information is added is input to the bit stream recording / reproducing device 70. The bit stream recording / reproducing device 70 records the packet to which the time stamp is added as one lump on the recording medium.
The bit stream recording / reproducing device is, for example, a video tape recorder.

At the time of reproduction, a packet signal to which time information is added is reproduced from the recording medium of the bit stream recording / reproducing device 70. Then, the reproduced packet signal is set to the same packet interval as when the packet interval is received according to the added time information, and the bit stream recording / reproducing device 70
And output to the interface circuit 50. The signal input from the bit stream recording / reproducing device 70 to the interface circuit 50 during reproduction is the same signal as the signal input from the interface circuit 50 to the bit stream recording / reproducing device 70 during recording, and the packet interval is the same. , The time stamp is removed by the time stamp adding / removing circuit 570, and a clock signal synchronized with the program reproduced by the clock generating circuit 550 can be obtained using the clock reference information included in the bit stream. After that, by operating similarly to the case where the signal input from the antenna 90 is expanded and viewed, the signal from the bit stream recording / reproducing apparatus 70 can be expanded without excess and deficiency, and the image is viewed by the receiver 60. be able to.

Next, the operation of recording a signal from the storage device 10 in the bit stream recording / reproducing device 70 will be described. In this case, the program stream signal reproduced from the storage device 10 is input to the memory 30 via the interface circuit 20 and the bus 80 as described above. Further, the data is input from the memory 30 to the decoder 40 via the bus 80 and decompressed. At the same time, the program stream signal from the memory 30 is transmitted to the interface circuit 5
Input to 0. When recording the signal from the storage device 10 in the bit stream recording / reproducing device 70, the clock signal is input from the decoder 40 to the interface circuit 50. In this case, the switching circuit 450 is connected to the terminal A, the switching circuit 460 is connected to the terminal A, and the switching circuit 580 is connected to the terminal B. In the interface circuit 50, the program stream input from the bus 80 is converted into a transport stream by the conversion circuit 560. The converted transport stream is used to record the signal received from the antenna 90 in the same manner as the time stamp adding circuit 57.
At 0, a time stamp is added, and input to the bit stream recording / reproducing device 70. As described above, the reproduction signal from the storage device 10 can be recorded in the bit stream recording / reproduction device 70.

The operation for reproducing the signal from the storage device 10 recorded as described above is the same as the operation for reproducing the signal from the antenna 90 described above.

Next, an embodiment in which a signal received by the antenna 90 or a program reproduced by the bit stream recording / reproducing device 70 is recorded by the storage device 10 when the storage device 10 has a recording function will be described. Also in this case, the program received by the antenna 90 or the program reproduced by the bit stream recording / reproducing device 70 can be recorded in the storage device 10 while being watched by the receiver 60 as described above. As for the program received by the antenna 90, a transport stream packet signal of the program selected by the selection circuit 540 is input to the conversion circuit 560. Bit stream recording / reproducing device 7
Similarly, in the case of reproduction at 0, the transport stream packet signal from which the time stamp has been removed is input to the conversion circuit 560. The conversion circuit 560 converts the transport stream packet into a program stream packet. The converted program stream packet is temporarily stored in the memory 30 via the bus 80. The program stream packet temporarily stored in the memory 30 is input to the interface circuit 20 via the bus 80. The interface circuit 20 has a buffer circuit (not shown), and after a predetermined amount of data is accumulated in the buffer circuit, the data is written to the storage device 10. The average write data rate of the storage device 10 needs to be higher than the average data rate of the received or reproduced program. That is, when the predetermined amount of data is not stored in the buffer circuit in the interface circuit 20, the storage device 10 stops writing and stopping, and the storage device 10 continues the portion already recorded when the predetermined amount of data is stored. Write data at high speed.

With the above operation, the received or reproduced signal can be efficiently written into the storage device 10.

In the above description, the reproduction signal from the storage device 10 and the bit stream recording / reproduction device 70 has been described as a program. However, the present invention is not limited to a program consisting of a video signal and an audio signal. It may be a signal or an information signal.

In the embodiment shown in FIGS. 1 and 2, the antenna 90 is shown using a diagram such as a parabolic antenna for receiving satellite broadcasts. However, the present invention is not limited to this. It can be applied to a case where a signal is input through an optical cable, a coaxial cable, or a telephone line.

Next, an embodiment relating to a technique related to time stamp addition will be described.

FIG. 3 shows the embodiment shown in FIG.
FIG. 3 is a schematic diagram showing an example of a signal received by the control unit. The embodiment shown in FIG. 3 shows a case where four programs are transmitted on one transmission channel. The transmission channels are (1) to
The case of n transmission channels up to (n) will be described. In FIG. 3, V1, V2, V3, and V4 are video signals of four programs, A1, A2, A3, and A4 are audio signals of four programs, respectively.
PG is a signal indicating program guide information, and VECM and AECM are control signals indicating a viewing right relationship. Each of them represents a signal of one packet.

The above four programs generally have different transmission rates. In addition, when viewed instantaneously, the data amount increases or decreases. To efficiently control this, each piece of information is packetized and time-division multiplexed as shown in FIG. The details of the signal in the packet shall conform to the MPEG transmission standard. Although not shown in detail in the schematic diagram shown in FIG. 3, the signal in each packet is encrypted as necessary, and header information such as an error correction code and a synchronization signal is added.

In the embodiment shown in FIGS. 1 and 2, the antenna 9
3 (1)... (N) are input from 0, and the tuner 510 selects one of the transmission channel signals. Here, it is assumed that FIG. 3A has been selected. The selected signal shown in FIG.
Are demodulated, and the error is corrected by the error correction circuit 530 and input to the selection circuit 540. In the selection circuit 540, it is assumed that the program indicated by appendix 1 has been selected from the four time-division multiplexed programs. At this time, video signal V1, audio signal
Simultaneously with A1, program guide information PG, viewing right control signal VEC
M and AECM are also separated and output. FIG. 4B shows the signal obtained by dividing the program. FIG. 4A rewrites FIG. 3A.

The case where the signal from the tuner 510 is expanded by the expansion circuit 420 in the embodiment shown in FIG. 2 will be described first. As described above, the program-selected signal shown in FIG. 4B is converted into a program stream by the conversion circuit 560 and input to the decompression circuit 420 via the bus 80 and the buffer circuit 410. In the case of an encrypted signal, although not shown, the signal is decrypted by a decryption circuit in the decompression circuit 420. This is performed based on the viewing right control signals VECM and AECM signals shown in FIG. That is, if the subscribing household has the right to view the currently selected program, the encryption is decrypted. If the subscriber does not have the right to view, the decryption is not performed. Is output to the receiver 60. The output of this information is what is called an OSD.

The decryption of the encryption can be performed after the error is corrected by the error correction circuit 530 and before the program is selected by the selection circuit 540. In that case, the present invention can be similarly applied.

The decrypted signal is expanded by an expansion circuit 420 according to, for example, the MPEG standard. When decompressing a signal compressed according to the MPEG standard, it is necessary to synchronize the transmitted signal with the data to be decoded. For example, if the transmitted signal is not synchronized with the data to be expanded, and if the expansion speed is higher than the transmission speed, the data is insufficient and expansion cannot be performed. For this reason, in the MPEG standard, clock reference information called PCR or SCR is added to a packet as described above. At the time of decompression, the clock generation circuit 550 is based on this clock reference information.
And restores the clock signal for expansion, and inputs the clock signal to the expansion circuit 420 for expansion.

FIG.
In order to record the selected signal shown in (2), it is necessary to add a time stamp as described above and to make it possible to reproduce it while maintaining the time interval of the input packet.

As shown in FIG. 4 (2), there are portions where packets are continuously present, and portions where packets are present at intervals of several packets. In order to record the signal in the bit stream recording / reproducing device 70 while keeping the time interval of the signal, recording at a rate higher than the rate of the input signal is required.
As shown in FIG. 4 (2), there is a period during which no packet is transmitted, so that if the packet can be packed and recorded and returned to the original time interval at the time of reproduction, the recording rate will be smaller than the rate of the input signal. it can. FIG. 4 (3) shows a case where a time stamp is added / packed so that packets can be packed and recorded at the time of recording, and can be returned to the original time interval at the time of reproduction.
From the removal circuit 570 to the bit stream recording / reproducing device 70
Shows the signals that are output.

The time stamp addition / removal circuit 570 adds information (time stamp) indicating the time when a packet arrives to the input signal as header information. Information other than the time stamp may be further added as needed as header information. Further, in order to add header information such as a time stamp to the input signal of the time stamp adding / removing circuit 570 shown in FIG. 4B, it is necessary to increase the packet transmission rate. FIG.
(3) schematically shows this. That is, FIG.
In (3), one packet is transmitted in a short time with respect to the transmission time of one packet shown in (1).

FIG. 5 shows an embodiment of a circuit for adding a time stamp. Reference numeral 600 denotes a clock signal input terminal for counting time stamps, 601 denotes a packet signal input terminal shown in FIG. 4B, 602 denotes a time stamp added signal output terminal, 610 denotes a counting circuit, and 611 denotes a latch. Circuit, 620 is a memory, 630 is a packet head detection circuit, 631 is a memory control circuit, 640 is a multiplex circuit,
650 is a delay circuit.

A packet signal shown in FIG. 4B is input from the terminal 601 and input to the memory 620 and the packet head detection circuit 630. The packet head detection circuit 630 detects the head of the packet of the input signal, and the detection signal is input to the latch circuit 611, the control circuit 631, and the delay circuit 650. On the other hand, the clock signal input from the terminal 600 is input to the counting circuit 610 and counts the clock signal continuously. The output signal of the counting circuit is input to the latch circuit 611. The latch circuit 611 latches the input count value with the packet head signal from the packet head detection circuit 630. The latched count value is input to the multiplexing circuit 640. This count value becomes the time stamp information of the packet.

A control signal for the memory 620 is generated based on the packet head detection signal input to the control circuit 631.
As a write clock for the memory 620, a clock signal input from the terminal 604 is used. For this, a signal that matches the packet signal frequency input from the terminal 601 is used. As a reading clock of the memory 620, a clock signal input from the terminal 603 is used. As this clock signal frequency, a frequency higher than the write clock frequency input from the terminal 604 is selected. As an example, when the write clock frequency is 30.3 MHz, the read clock frequency is 49.152 MHz. This read clock is shown in FIG.
The bus clock frequency of the signal sent from the interface circuit 50 to the bit stream recording / reproducing device 70 shown in FIG. At this time, the counting circuit 61 input from the terminal 600
Assuming that the clock signal of 0, that is, the clock signal frequency for the time stamp is the same as the clock signal frequency input from the terminal 603, the clock signal for the time stamp and the bus clock signal input from the terminal 603 are the same. Can be used. However, the present invention does not limit the time stamp clock frequency to the same as the bus clock signal frequency.

After the packet is input to the memory 620,
After a predetermined time, the data is read from the memory. Since the frequency of the read clock signal is set higher than the frequency of the write clock signal, the transmission time of the output packet is made shorter than the transmission time of the input packet signal as shown in FIGS. be able to. Therefore, even in a portion where packets are continuously transmitted, a period for adding header information including time stamp information can be obtained as shown in FIG. The output signal of the memory 620 is output to the multiplexing circuit 64.
Input to 0.

The delay circuit 650 delays the packet head detection signal, and outputs a gate signal indicating a position where a time stamp signal is added in accordance with the packet signal output from the memory 620. The gate signal is input to the multiplexing circuit 640, and the multiplexing circuit 640 adds the time stamp information from the latch circuit 611 and outputs the signal shown in FIG.

The signal shown in FIG. 4C is input to the bit stream recording / reproducing device 70. FIG. 6 (1) is FIG.
The signal corresponding to (3) is rewritten, and P1, P2,
.. Indicate the input packet signals. FIG.
Although there is a gap between the packets of the input signal shown in (1) as described with reference to FIG. 4, if the recording is performed in a state where the interval between the packet signals is narrowed as shown in FIG. It can be lower than the packet signal rate. Therefore, the recording rate in the tape transport system can be reduced. In FIG. 6, the input signal (1) and the output signal (2)
Has been shown with a delay of one track period, but this is shown for the sake of convenience and is not limited to one track period, but may be delayed for signal processing.

At the time of reproduction, the signal reproduced from the tape transport system includes packet signals P1 and P1 in the same manner as in FIG.
P2, ... are the signals in the filled state. FIG. 6 (3) shows the reproduced signal. FIG. 7 shows the reproduced packet signals P1, P2,
Bit stream recording / reproducing device 70 for restoring the interval of...
FIG. 2 is a block diagram showing one embodiment of a time axis adjustment circuit in FIG. FIG. 6D shows the signal after the intervals between the reproduced packet signals P1, P2,.

7, reference numeral 710 denotes a memory; 700, an input terminal of the memory 710; 720, a memory; 701, a read clock input terminal of the memory 720; 702, a write clock input terminal of the memory 720; Output terminal of the output signal, 751 is a counting circuit, 70
4 is an input terminal of the clock signal of the counting circuit 751;
Is a time stamp gate circuit, 740 is a control circuit, 75
0 is a time stamp reading circuit, and 752 is a coincidence detecting circuit.

FIG. 6 inputted from the terminal 700 shown in FIG.
The reproduction signal shown in (3) is input to the memory 710. The signals output from the memory 710 for each packet of the packet signals P1, P2,... Are input to the memory 720 and the time stamp reading circuit 750. Read control of the memory 710 and write / read control of the memory 720 are performed by control signals from the control circuit 740. The control signal from the control circuit 740 is also input to the time stamp reading circuit 750, and a signal indicating the position of the time stamp signal is output in response to the signal from the memory 710, and the time stamp signal at the correct position is read. The read time stamp signal is input to the coincidence detection circuit 752.

A clock signal having the same frequency as that input from the terminal 600 shown in FIG. 5 is input from the terminal 704 and input to the counting circuit 751. The counting circuit 751 counts the input clock signal, and outputs the counted value to the coincidence detecting circuit 752. The coincidence detection circuit 752 outputs a coincidence signal when the two input signals coincide, and inputs the coincidence signal to the control circuit 740.

The control circuit 740 reads a packet signal from the memory 720 based on the coincidence signal. Fig. 6 (4)
Shows the read signal. The reading is terminal 7
This is performed based on the read clock signal input from 01. At the same time, a new packet is input from the memory 710 and written to the memory 720 based on the write clock input from the terminal 702. The frequency of the clock signal input from the terminal 701 may be determined so as to correspond to the signal rate between the interface circuit 50 and the bit stream recording / reproducing device 70.

The time-adjusted packet signals P1, P2,... From the memory 720 are output from a terminal 703 at the same time interval as the signal shown in FIG. Is done.

As described above, signals at the same packet intervals as shown in FIG. The time stamp adding / removing circuit 570 removes the header information and outputs the result. Thereby, the same signal as the signal from tuner 510 can be restored.

[0048]

According to the present invention, for example, when a transport signal, which is a compressed digital broadcast reception signal or a compressed bit stream recording / reproducing apparatus, is expanded, it is included in the transport stream. A clock signal is generated based on a reference signal to be generated, and a compressed signal is expanded using the clock signal. For example, when a program stream signal which is a compressed signal reproduced from a disk-shaped medium is expanded, a stable clock signal is generated. Since the compressed signal is used to decompress the data, both the transport stream and the program stream can be decompressed without any excess or deficiency of data.

Further, since the signal compressed by the variable rate compression method is reproduced while expanding the compressed signal reproduced from a storage device such as a disk device whose reproduction speed can be controlled, it can be recorded on a tape medium. In addition, data can be reproduced without excess or deficiency of data.

Further, since the transport stream reproduced from the tape-like medium is converted into a program stream and the recording rate of the disk-like medium is set to be higher than the average reproduction rate, the recording rate of the tape-like medium is increased. The reproduced compressed signal can be efficiently recorded on a disk-shaped medium.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram showing one embodiment of the present invention.

FIG. 3 is a schematic diagram of an input signal according to the present invention.

FIG. 4 is a schematic diagram of a signal according to the present invention.

FIG. 5 is a block diagram showing one embodiment of the present invention.

FIG. 6 is a schematic diagram of a signal according to the present invention.

FIG. 7 is a block diagram showing one embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Storage apparatus 20, 50 ... Interface circuit 40 ... Decoder 70 ... Bit stream recording / reproducing apparatus 420 ... Decompression circuit 440 ... Crystal oscillator 550 ... Clock generation circuit 560 ... Conversion circuit 570 ... Time stamp addition / removal circuit 610, 751 ... Counting Circuit 630: Packet head detection circuit 640: Multiplex circuit 750: Time stamp reading circuit 752: Match detection circuit

──────────────────────────────────────────────────の Continued on the front page (72) Inventor Kyoichi Hosokawa 1410 Inada, Hitachinaka City, Ibaraki Prefecture Inside the Visual Information Media Division, Hitachi, Ltd. (56) References JP-A-6-253331 (JP, A) JP-A-7-154802 (JP, A) JP-A-7-98890 (JP, A) JP-A-6-237437 ( JP, A) JP-A-4-79588 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N 5/76-5/956 G11B 20/10-20/12

Claims (10)

(57) [Claims] 1. A transport stream including a digital compressed signal obtained by compressing a video signal or an audio signal, a reference signal synchronized with the video signal or the audio signal, and a program stream including a digital compressed signal obtained by compressing the video signal or the audio signal. A first clock signal generating means for generating a first clock signal synchronized with the video signal based on the reference signal, and a second clock signal generating means for generating a stable second clock signal. Clock signal generating means, switching means for switching and selecting the first clock signal and the second clock signal, decompression means for decompressing the digital compressed signal based on the clock signal selected by the switching means, Control means for controlling switching means, wherein the control means In the case of extending the compressed digital signal included in the Sport stream selects the first clock signal, the second in the case of extending the compressed digital signal included in the program stream
A digital signal processing device that controls so as to select a clock signal. 2. A digital signal processing apparatus for processing a digital compressed signal reproduced from a storage means and generating a signal for recording on a bit stream recording medium, wherein the signal reproduced from the storage means is a digital compressed signal. A conversion means for converting the program stream into a transport stream in a packet format; and a packet signal constituting the converted transport stream, a relative time of the transmission time of the packet signal. A digital signal processing device comprising: an adding unit for adding information, wherein the packet signal to which the relative time information is added by the adding unit is used as a recording signal on the bit stream recording medium. 3. A transport stream composed of a digital compressed signal obtained by compressing a video signal or an audio signal and a packet format signal including a reference signal synchronized with the video signal or the audio signal is input. A digital signal processing device for recording in a storage unit; a clock signal generation unit that generates a clock signal synchronized with the video signal based on the reference signal; a conversion unit that converts the transport stream into a program stream; And buffer means for temporarily storing the program stream, and an output signal of the buffer means is recorded in the storage means. 4. The digital signal processing apparatus according to claim 3, wherein an instantaneous recording rate of said storage means is higher than an average input rate of said transport stream. 5. A digital signal processing device for reproducing a program stream including a digitally compressed signal obtained by compressing a video signal or an audio signal from storage means and outputting the reproduced digitally compressed signal. Conversion means for converting to a transport stream in a packet format; and addition means for adding relative time information indicating a time at which the packet signal is output to a packet signal constituting the converted transport stream, A digital signal processing device for outputting a packet signal to which time information has been added by said adding means. 6. A transport stream composed of a digital compressed signal obtained by compressing a video signal or an audio signal and a packet format signal including a reference signal synchronized with the video signal is input, and the digital compressed signal is stored in storage means. A digital signal processing device for recording, comprising: a conversion unit for converting the input transport stream into a program stream; and a buffer unit for temporarily storing the converted program stream. A digital signal processing device, wherein the digital signal is recorded in the storage means. 7. A digital signal processing apparatus for outputting a digital compressed signal obtained by compressing a video signal or an audio signal, comprising: a reproducing means for reproducing a program stream including the digital compressed signal from a storage medium; Conversion means for converting to a transport stream in a packet format; and addition means for adding relative time information indicating a time at which the packet signal is output to a packet signal constituting the converted transport stream, A digital signal processing device for outputting a packet signal to which time information has been added by said adding means. 8. A digital signal processing apparatus for inputting a transport stream composed of a packet format signal including a digital compressed signal obtained by compressing a video signal or an audio signal and a reference signal synchronized with the video signal, Converting means for converting the transport stream into a program stream; buffer means for temporarily storing the converted program stream; and recording means for recording an output signal of the buffer means on a storage medium. A digital signal processing device for recording the program stream on a medium. 9. A digital signal processing method for outputting a digital signal obtained by compressing a video signal or an audio signal, wherein a program stream including the digital signal is reproduced from a storage medium, and the reproduced program stream is converted into a packet format transport stream. And adding relative time information indicating the output time of the packet signal to a packet signal constituting the converted transport stream, and outputting the packet signal with the time information added. Digital signal processing method. 10. A digital signal processing method for inputting a transport stream composed of a packet format signal including a digital compressed signal obtained by compressing a video signal or an audio signal and a reference signal synchronized with the video signal, the digital signal processing method comprising: A digital signal processing method, comprising: converting a transport stream into a program stream; temporarily storing the converted program stream in a buffer; and recording the temporarily stored program stream on a storage medium.