JP3335482B2 - Signal processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing device for a television receiver (TV receiver) or the like.

[0002]

2. Description of the Related Art In recent years, a broadcasting system called EDTV (Extended Definiton TV, so-called clear vision) has been put to practical use due to a demand for higher image quality of television images. Also, MUSE (Multiple Sub-nyquid), which is a kind of HDTV (High Definition TV, so-called high definition) system, is used.
New high-definition broadcasts such as the st Sampling Encoding method have been proposed and some have been put to practical use. EDTV II
(2nd generation EDTV), digital broadcasting, etc. will be implemented. Along with this, video signal processing devices such as TV receivers and video tape recorders (VTRs) need to be compatible with a plurality of broadcasting systems including the current NTSC (National Television System Committee) system.

FIG. 19 shows a configuration example of a conventional TV receiver. In the figure, reference numeral 301 denotes a TV receiver;
It receives TV signals of two types of broadcast systems, the E system and the EDTV system. 303 is dedicated hardware for realizing the MUSE processing algorithm, and 304 is an EDTV
Dedicated hardware for implementing the processing algorithm. One of the image signals decoded by the dedicated hardware 303 and 304 is selected by the selection circuit 305, and an image is displayed on the display device 302.

[0004]

The above-mentioned conventional TV receiver incorporates a plurality of dedicated hardware, each of which corresponds to one broadcasting system, and switches the hardware to be used in accordance with a received signal. There was a disadvantage of becoming high.
In addition, in order to respond to the broadcasting method to be started in the future and to respond to changes in processing algorithms, it is necessary to develop new dedicated hardware, which leads to longer development periods and higher development costs. Had also. These problems are not limited to TV receivers, but are common to various signal processing devices for image processing, recognition, compression processing, audio processing, and the like, in which processing is switched for each system.

The present invention has been made in view of the above problems, and an object of the present invention is to enable one hardware for signal processing to be shared by a plurality of processing methods and a plurality of processing algorithms.

[0006]

In order to achieve the above object, a signal processing apparatus according to the present invention comprises K (K is an integer of 2 or more) arithmetic means for executing a predetermined arithmetic operation processing. At least K + for flexible connection changes
In this configuration, switch means having one input data line and at least K + 1 output data lines is connected to the K arithmetic means. One of the K + 1 input data lines of the switch means is supplied with external input data, and the remaining K input data lines are supplied with outputs of the K arithmetic means. Also, K + 1
Output data to the outside is obtained from one of the output data lines, and the data on the remaining K output data lines is input to the K arithmetic means. The switch means switches K + 1 input data lines and K + 1
Achieving a separable and interchangeable connection with the output data lines of the book. Further, to hold arithmetic control information for specifying the contents of the arithmetic operation processing of each of the K arithmetic means and connection control information for specifying the connection mode between the input data line and the output data line in the switch means. Is provided.

To switch the processing of the signal processing device of the present invention, the arithmetic control information and the connection control information in the information holding means are updated. Further, the information holding means is constituted by a plurality of register sets each for holding operation control information and connection control information, and any one of the plurality of register sets is configured to switch processing of the signal processing device of the present invention. One may be selected.

[0008]

According to the signal processing apparatus of the present invention, the K connection means having various functions, each having a basic function such as a filter function, can be connected by changing the connection inside the switch means based on the connection control information. Can be realized. Specifically, the number, combination, connection order, and the like of the calculation means used can be changed. Accordingly, various types of signal processing devices adapted to each of the plurality of processing methods and the plurality of processing algorithms can be realized with one piece of hardware. It is also possible to change the processing content of each calculation means based on the calculation control information. Specifically, the coefficients used for the product-sum operation in a certain arithmetic unit, the internal connection of the arithmetic unit, and the like are changed.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a signal processing apparatus according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a TV receiver provided with a signal processing device according to a first embodiment of the present invention.

In FIG. 1, reference numeral 201 denotes a MUSE synchronization circuit, and reference numeral 202 denotes an NTSC synchronization circuit. The MUSE synchronization circuit 201 has a function of detecting a synchronization signal from a received MUSE signal and performing A / D conversion of the MUSE signal. The MUSE synchronization circuit 201 includes a MUSE synchronization signal and a digitized MUSE signal.
USE data is output. NTSC synchronization circuit 202
Has a function of detecting a synchronizing signal from an NTSC signal having a signal format different from that of the MUSE signal and performing A / D conversion of the NTSC signal, and converts the NTSC synchronizing signal and the digitized NTSC data. Output. Both synchronization circuits 201 and 202 further have a function of nonlinear processing for improving image quality. Specifically, the MUSE synchronization circuit 201
Is a waveform equalizer or de-emphasis filter,
The NTSC synchronization circuit 202 includes ghost cancellers.

Reference numeral 203 denotes a switching device; and 204, an input data memory constituted by a field memory. The switching device 203 selects output data of the MUSE synchronization circuit 201 or output data of the NTSC synchronization circuit 202.
The selected data is stored in the input data memory 204. The input data memory 204 is configured to hold input data of a plurality of fields.

Reference numeral 205 denotes an image processing apparatus having the features of the present invention, 206 denotes a temporary data storage device, 207 denotes an output data memory, 208 denotes a central processing unit (CPU), 209 denotes a memory control device, and 210 denotes a program memory. . The image processing device 205 performs required signal processing on the image data received from the input data memory 204,
It is shared by the MUSE system and the NTSC system. The data temporary holding device 206 is provided so as to be able to hold an intermediate result of the processing by the image processing device 205. The held data is further processed by the image processing device 205. The final result of the processing by the image processing device 205 is stored in the output data memory 207. The CPU 208 controls operations of various circuits (not shown) in the TV receiver, and operations of the switching device 203 and the image processing device 205. The memory control device 209 controls reading of the input data memory 204 and the data temporary holding device 206,
In addition, write control of the temporary data holding device 206 and the output data memory 207 is performed. Program memory 2
Reference numeral 10 stores an instruction to be executed by the CPU 208.

Reference numeral 211 denotes an audio processing unit, and 212 denotes a speaker. The audio processing unit 211 performs required signal processing on the audio data received from the input data memory 204. The processing result is supplied to the speaker 212, and a sound is output.

Reference numeral 213 denotes a post-processing circuit; 214, a CRT display control unit; and 215, a CRT. Output data memory 20
7 is subjected to appropriate processing by a post-processing circuit 213, and then the D /
A conversion is performed. The conversion result is supplied to the CRT 215, and an image is displayed. At this time, the post-processing circuit 213 and the CRT
The display control unit 214 includes the MUSE synchronization circuit 201 and the NT
It operates in response to each synchronization signal from the SC synchronization circuit 202.

FIG. 2 is a block diagram showing the configuration of the signal processing device according to the first embodiment of the present invention, and shows the internal configuration of the image processing device 205 in FIG. In FIG. 2, reference numerals 1, 2, 3, and 4 in the image processing apparatus 205 denote arithmetic units for performing arithmetic operations such as filter operations on given data. 13a and 13b are register sets each having five registers. One register set 13a includes four operation control registers 5a and 6 for holding operation control information for specifying processing contents such as the type of operation of each of the arithmetic units 1 to 4 and coefficients used for the operation.
a, 7a and 8a, and one connection control register 12a for holding connection control information described later. Similarly, the other register set 13b also has four operation control registers 5b, 6b, 7b and 8b and one connection control register 12b.

The reference numeral 9 in the image processing device 205 has eight input data lines and five output data lines, and the eight input data lines and the five output data lines can be separated. And a bus switch for achieving interchangeable connections.
Four of the five output data lines of the bus switch 9 are connected to the input terminals of the arithmetic units 1 to 4, and the other one is drawn out of the image processing device 205 to the data temporary holding device 206. And the output data memory 207. Reference numeral 10 denotes a line memory, and reference numeral 20 denotes an input selector (input selection circuit). The input selector 20 selects data held in the input data memory 204 or data held in the temporary data holding device 206. The line memory 10 stores data selected by the input selector 20 and data directly supplied from the input data memory 204, and is configured to hold four lines of input data. Four of the eight input data lines of the bus switch 9 are connected to the line memory 10, and the remaining four are connected to the output terminals of the computing units 1-4. The connection control registers 12a and 12b hold connection control information for designating a connection mode between eight input data lines and five output data lines in the bus switch 9, respectively.

Further, in the image processing apparatus 205, 1
4 is a switching circuit, 15 is a switching control circuit, and 17 is a register updating circuit. The switching circuit 14 includes the arithmetic unit 1
5 selection circuits 23 to 4 and bus switch 9
27. Among them, the selection circuit 23 for the arithmetic unit 1 is configured to store the information held in the arithmetic control register 5a belonging to one register set 13a and the other register set 13a.
The information is supplied to the arithmetic unit 1 with any of the information held in the arithmetic control register 5b belonging to b. The functions of the selection circuits 24 to 26 for the arithmetic units 2 to 4 and the selection circuit 27 for the bus switch 9 are the same. Switching control circuit 15
Outputs the switching signal 16 to the selection circuits 23 to 27 to select a desired register set from the two register sets 13a and 13b. Register update circuit 17
Updates the information held in both register sets 13a and 13b.

FIG. 3 is a circuit diagram showing the internal configuration of the bus switch 9 in FIG. The bus switch 9 in FIG. 3 has 40 bus drive circuits 31 arranged in a matrix so that any connection between eight input data lines and five output data lines can be achieved. Each bus drive circuit 31
It is connected to one of the eight input data lines and one of the five output data lines, and responds to the input data when an output control signal 32 of logic 1 is supplied from the selection circuit 27. Data is output to its own output terminal, and when an output control signal 32 of logic 0 is applied, its own output terminal is kept at high impedance. Each of the connection control registers 12a and 12b holds a logical value of an output control signal 32 to be given to 40 bus drive circuits 31. The selection circuit 27 selects one of the connection control registers 12a and 12b according to the switching signal 16, and selects 40
The output control signal 32 is supplied to the bus drive circuits 31.
The bus switch 9 in FIG. 3 can simultaneously transmit one input data to a plurality of output data lines.

Now, in the TV receiver shown in FIG.
8 controls the operation of the switching device 203 according to the broadcasting system, and controls the register updating circuit 1 of the image processing device 205.
7, an instruction and data for updating the information of both register sets 13a and 13b are sent. Further, the CPU 208 instructs the switching control circuit 15 of the image processing device 205 to switch between the two register sets 13a and 13b.

When processing the MUSE signal, the switching device 203 is switched to the MUSE side. This gives M
The output data of the USE synchronization circuit 201 is supplied to the image processing device 205 via the input data memory 204. In the image processing device 205, operation control information and connection control information for realizing a series of MUSE processing algorithms are stored in both register sets 13 a and 13 b by the operation of the register update circuit 17. When one of the register sets 13 a is selected by the operation of the switching circuit 14 and the switching control circuit 15, operation control information is supplied to each of the arithmetic units 1 to 4, and connection control information is supplied to the bus switch 9. Thus, the arithmetic units 1 to 4 are connected to each other via the bus switch 9 so that the first half algorithm of the MUSE process can be realized. Some of the four arithmetic units 1 to 4 include an input selector 20, a line memory 10, and a bus switch 9.
, The read data from the input data memory 204 can be received. The results of the processing by the arithmetic units 1 to 4 are supplied to the data temporary holding device 206 via the bus switch 9 and held there. Next, when the other register set 13b is selected by the operation of the switching circuit 14 and the switching control circuit 15, new arithmetic control information is provided to each of the arithmetic units 1 to 4 and new connection control information is provided to the bus switch 9. Are supplied respectively. Thereby, the four computing units 1-4 through the bus switch 9
Is changed so that the latter half of the MUSE processing algorithm can be realized. The arithmetic units 1 to 4 receive read data from the input data memory 204 and the data temporary holding device 206. The results of the processing by these computing units 1 to 4 are supplied to the output data memory 207 via the bus switch 9 and stored therein.

When processing the NTSC signal, the switching device 203 is switched to the NTSC side. This gives N
The output data of the TSC synchronization circuit 202 is supplied to the image processing device 205 via the input data memory 204. In the image processing device 205, the operation control information and the connection control information for realizing a series of algorithms of the NTSC process are stored in one register set 13a by the operation of the register update circuit 17. When the register set 13a is selected by the operation of the switching circuit 14 and the switching control circuit 15, the arithmetic units 1-4
Are supplied with arithmetic control information and the bus switch 9 is supplied with connection control information. As a result, the computing units 1 to 4
Are connected to each other via a bus switch 9 so that desired NTSC processing can be realized.

As described above, according to the TV receiver of FIG. 1, the four arithmetic units 1-4 in the image processing device 205
It can be used for USE processing and NTSC processing.
The four arithmetic units 1 to 4 can be shared for executing different algorithms during the USE processing. Therefore, compared to the case where dedicated hardware is provided for each broadcasting system as in the past,
The circuit scale of the TV receiver can be significantly reduced.
For the same data stored in the input data memory 204, different processing can be performed by switching the register sets 13a and 13b. Furthermore, arithmetic units 1 to 3 are provided for each line, such as a difference in filter coefficient due to a difference in sampling position of image data between an odd line and an even line.
4 can be dealt with by switching the register sets 13a and 13b.

Further, the four arithmetic units 1-4 are shown in FIGS.
A pipeline operation as shown in FIG. 6 is possible. FIG.
The example of (1) shows a case where the computing unit 1, the computing unit 4, the computing unit 3 and the computing unit 2 are connected in series in this order via the bus switch 9. The input data is sequentially supplied to the arithmetic unit 1, and the output data is sequentially extracted from the arithmetic unit 2. For example, the arithmetic unit 1 executes the processing of the second input data while the arithmetic unit 4 is executing the processing of the output data of the arithmetic unit 1 with respect to the first input data. By employing such a pipeline operation, high-speed image processing can be realized. Further, FIG.
If the processing of each of the arithmetic units 1 to 4 is divided into a plurality of stages as shown in FIG. 4, the processing efficiency can be increased as compared with the case of FIG. In the example of FIG. 6, the operation units 1 and 4 process the input data in parallel so that the operation units 1 and 2 process the output data in parallel, and the operation units 3 and 4 sequentially process the respective outputs. The connection is realized by the bus switch 9. For example, while the computing unit 3 is executing the processing of the output data of each of the computing unit 1 and the computing unit 2 regarding the first input data, the computing unit 1 and the computing unit 2 perform the parallel processing of the second input data. Execute

As described above, if the bus switch 9 of FIG. 3 is used, an arbitrary pipeline connection of the four arithmetic units 1 to 4 can be realized. However, 4 depending on the processing content
Some of the zero bus drive circuits 31 can be omitted. As an internal configuration of each of the arithmetic units 1 to 4,
A series connection or series-parallel connection of a plurality of sub-operation units may be employed.

For high-speed switching between MUSE processing and NTSC processing, both register sets 13a, 13
The information held in the other register set may be updated by the register update circuit 17 while one of the register sets b is selected. If three register sets are provided, MUSE processing and N
High-speed switching with TSC processing can be achieved.

The two register sets 13a, 1 in FIG.
3b, two sets of Rs for holding the arithmetic control information of the arithmetic units 1 to 4 and the connection control information of the bus switch 9, respectively.
An OM (read only memory) may be employed. In this case, the information held in the ROM is fixed, and the register update circuit 17 is unnecessary. The switching of the processing of the image processing device 205 is performed by the switching circuit 14 and the switching control circuit 1.
This is achieved by selecting ROM by the function of 5.

(Embodiment 2) FIG. 7 is a block diagram showing a configuration of a signal processing apparatus according to a second embodiment of the present invention.
The image processing device 205 in FIG. 7 includes first and second bus switches 9 and 21. The first bus switch 9 has 8
And eight input data lines and four output data lines.
This achieves a separable and interchangeable connection between the four input data lines and the four output data lines. Four output data lines of the first bus switch 9 are connected to input terminals of the arithmetic units 1 to 4. The second bus switch 21 has 4
And four input data lines and five output data lines.
It achieves a separable and interchangeable connection between five input data lines and five output data lines. Four input data lines of the second bus switch 21 are connected to output terminals of the computing units 1 to 4. Also, the second bus switch 2
Four of the five output data lines 1 are connected to four of the eight input data lines of the first bus switch 9;
The remaining one is pulled out of the image processing device 205 and is temporarily stored in the data temporary holding device 206 and the output data memory 207.
(See FIG. 1). First bus switch 9
The remaining four of the eight input data lines are connected to the line memory 10.

In the image processing apparatus 205, one register set 13a includes four operation control registers 5a to 8a and two connection control registers 12a and 22a.
And Similarly, the other register set 13b has 4
It has two operation control registers 5b to 8b and two connection control registers 12b and 22b. Two of the four connection control registers (12a, 12b) hold connection control information for the first bus switch 9, and the other two (22a, 22b) hold the second control information. It holds connection control information for the bus switch 21 of FIG.

Further, in the image processing apparatus 205, the switching circuit 14 includes the arithmetic units 1-4 and the two bus switches 9,
21 are provided with six selection circuits 23-28. Among them, the selection circuit 28 for the second bus switch 21 stores the information held in the connection control register 22a belonging to one register set 13a and the other register set 1
One of the information held in the connection control register 22b belonging to the third bus switch 3b is supplied to the second bus switch 21. The functions of the selection circuits 23 to 26 for the arithmetic units 1 to 4 and the selection circuit 27 for the first bus switch 9 are the same. The switching control circuit 15 outputs the switching signal 16 to the selection circuits 23 to 28 and outputs the two register sets 13
a, a desired register set is selected from 13b. The register update circuit 17 includes the two register sets 13
a, 13b is updated.

According to the present embodiment, since the configuration of the image processing apparatus 205 having the two bus switches 9 and 21 is employed, the arithmetic unit can be simplified while simplifying the internal configuration of each of the bus switches 9 and 21. 1 to 4 flexible connections can be realized.
The first bus switch 9 may not be able to achieve any connection between the eight input data lines and the four output data lines.
The same applies to the second bus switch 21.

(Embodiment 3) FIG. 8 is a block diagram showing a configuration of a signal processing apparatus according to a third embodiment of the present invention.
The image processing apparatus 205 in FIG. 8 does not have a register set switching function, and is provided with only one register set 13. The bus switch 9 has five input data lines and five output data lines, and achieves a separable and exchangeable connection between the five input data lines and the five output data lines. It is. Four of the five output data lines of the bus switch 9 are connected to the input terminals of the arithmetic units 1 to 4,
The remaining one is drawn out of the image processing device 205. Four of the five input data lines of the bus switch 9 are connected to the output terminals of the arithmetic units 1 to 4, and the other one is drawn out of the image processing device 205. The register set 13 includes four operation control registers 5 to 8 for holding operation control information of the operation units 1 to 4 and a bus switch 9.
And one connection control register 12 for holding the connection control information. The register updating circuit 17 updates information held in the register set 13.

According to the present embodiment, the register updating circuit 17
Updates the information held in the register set 13 so that the processing of the image processing apparatus 205 is switched. Although the time required for switching the processing is slightly longer than that in the case of switching the register set, there is an effect that the circuit scale of the image processing device 205 can be reduced.

(Embodiment 4) FIGS. 9 to 11 are block diagrams showing the configuration of a signal processing apparatus according to a fourth embodiment of the present invention, which is used commonly for image processing of the EDTV system and the MUSE system. Is shown. FIG. 9 shows an internal connection of a bus switch for realizing a series of algorithms of the EDTV processing, and FIG. 10 shows an internal connection of a bus switch for realizing an algorithm of the motion detection processing in the MUSE processing. Shows internal connections of bus switches for implementing other algorithms in the MUSE process.

The signal processing device according to the present embodiment includes one bus switch 100, eleven arithmetic units 101 to 111,
Data temporary holding devices 141, one input data bus 151, and first and second output data buses 152, 1
53. 101 indicates three input signal lines and one
And a vertical filter having three output signal lines. 10
Reference numerals 2, 103 and 104 denote horizontal filters each having one input signal line and one output signal line. 105,
106 and 107 are addition / interpolation circuits each having two input signal lines and one output signal line. 108, 1
Reference numerals 09 and 110 denote magnitude determination circuits each having three input signal lines and one output signal line. Reference numeral 111 denotes a combining circuit having four input signal lines and one output signal line. The bus switch 100 has 20 input data lines and 27 output data lines, and achieves a separable and exchangeable connection between the 20 input data lines and the 27 output data lines. It is. 27 of the bus switch 100
25 of the output data lines are 11 arithmetic units 10
1 to 111, and the remaining two are connected to the first
And the second output data buses 152 and 153 are connected to the input terminals of the data temporary holding device 141. First
The output data bus 152 is drawn out of the signal processing device. Eleven of the twenty input data lines of the bus switch 100 are connected to eleven computing units 101 to 11.
One output signal line is connected, and the other two are connected to output terminals of the data temporary holding device 141.

The signal processing apparatus of this embodiment further includes first to fourth field memories 121 to 124, and first and second line memories 131 and 132. Input data for each pixel is sequentially supplied to the input data bus 151. For the current pixel data on the input data bus 151, the first field memory 121 stores the pixel data of the previous field, the second field memory 122 stores the pixel data of the previous frame, and the third field memory 123.
Outputs pixel data three fields before, and the fourth field memory 124 outputs pixel data two frames before. In addition, the first line memory 131 outputs the pixel data of one line before and the second line memory 132 outputs the pixel data of two lines before the current pixel data on the input data bus 151. These field memories 12
The output of the line memories 131 and 132 and the current pixel data on the input data bus 151 are supplied to the remaining seven input data lines of the bus switch 100.

The image processing apparatus of this embodiment further includes the same two register sets 13a and 13b, the switching circuit 14, the switching control circuit 15, and the register updating circuit 17 as in FIG. These are not shown in FIG.

FIG. 12 shows the internal configuration of the vertical filter 101 in FIGS. The vertical filter 101 of FIG.
Has three multipliers 40 and one adder 41,
Let three coefficients be A1 to A3 and three input data be D1 to
When D3, A1 × D1 + A2 × D2 + A3 × D3
Is performed. This is a 3-tap vertical filter operation. One operation control register belonging to one register set 13a and the other register set 1
One of the operation control registers belonging to 3b holds different coefficient sets A1 to A3 as operation control information. One of the switching circuits 14 selects one of the two register sets 13a and 13b in response to the switching signal 16 and supplies specific coefficients A1 to A3 to the three multipliers 40. .

The three horizontal filters 10 shown in FIGS.
FIG. 13 shows the internal configuration of one of the circuits 2 to 104. The horizontal filter 102 in FIG. 13 has seven multipliers 50, six adders 51, and six latches 52, with seven coefficients being a1 to a7 and i-th input data being di. Then, a1 × di + a2 × d (i + 1) + a3 × d (i + 2) + a
4 × d (i + 3) + a5 × d (i + 4) + a6 × d (i + 5) + a7
× d (i + 6) is executed. This is a 7-tap horizontal filter operation. The switching method of the coefficients a1 to a7 is the same as in the case of FIG.

The three addition / interpolation circuits 1 in FIGS.
FIG. 14 shows the internal configuration of one of 05 to 107.
The addition / interpolation circuit 105 in FIG. 14 includes an addition / subtraction unit 55 and an output selection circuit 56, and outputs two input data X and Y.
Then, X + Y, XY, X or Y is output. One operation control register belonging to one register set 13a and one operation control register belonging to the other register set 13b hold operation control information specifying the type of operation, respectively. This arithmetic control information is
Which one of X + Y and XY should be output by the adder / subtractor 55, and which of the two input data X and Y and the output of the adder / subtractor 55 should be selected and output by the output selection circuit 56 Is specified. Switching circuit 1
4 selects one of the two register sets 13a and 13b in response to the switching signal 16 and supplies the corresponding operation control information to the adder / subtractor 55 and the output selection circuit 56. I do.

The three magnitude judgment circuits 10 shown in FIGS.
FIG. 15 shows the internal configuration of one of 8-110. The magnitude determination circuit 108 in FIG. 15 includes first to fourth MAX / M
It has IN circuits 61 to 64, nine latches 65 for synchronization, and two input selection circuits 66. When three input data are X, Y, and Z, the maximum value is It is configured so that a minimum value or an intermediate value can be extracted. M
Each of the AX / MIN circuits 61 to 64 has a larger value, a smaller value,
Alternatively, one of the two inputs is output regardless of the value.
The two input selection circuits 66 include first to third input signal lines 6
It is provided for simultaneously taking in three pieces of pixel data supplied to the first, second, and seventh parallel lines 7, 68, and 69, or sequentially taking in three pieces of pixel data supplied to the first input signal line 67. The switching method of the operations of these four MAX / MIN circuits 61 to 64 and the two input selection circuits 66 is the same as in the case of FIG.

First to fourth MAX / MIN circuits 61 to 6
4 is designated to output the larger of the two inputs, the three input data X,
The maximum value data of Y and Z is extracted. 4 MAs
When each of the X / MIN circuits 61 to 64 is designated to output the smaller of the two inputs,
The minimum value data of the three input data X, Y, Z is extracted. In the case of setting the maximum value extraction or the minimum value extraction, only the data X and Y on the first and second input signal lines 67 and 68 among the three input signal lines 67 to 69 are compared. It is also possible to specify. Further, the first and third MAX / MIN circuits 61 and 63 each output the larger of the two inputs, and output the second and fourth M / MINs.
When each of the AX / MIN circuits 62 and 64 is designated to output the smaller of the two inputs,
Intermediate value data among the input data X, Y, and Z is extracted. The specific example in FIG. 15 indicates that the intermediate value data Y is extracted when Z>Y> X. If such an intermediate value extraction setting is adopted, the first input signal line 67
And isolated points can be removed from the pixel data continuously given to the pixel data.

FIG. 16 shows the internal configuration of the synthesizing circuit 111 in FIGS. The combining circuit 111 in FIG. 16 includes a combining control circuit 70, two multipliers 71, and one adder 72, and when given two pixel data are X and Y, kX + (1- k) Execute the operation of Y.
The synthesis control circuit 70 receives the two given control data C
1 and C2 and the arithmetic control information supplied from one of the switching circuits 14, two coefficients k, 1
Determine -k.

FIG. 17 shows the signal processing (EDT) in FIG.
FIG. 14 is a diagram showing a flow of (V processing). The EDTV processing realized by the connection in FIG. 9 includes a motion detection processing, an inter-frame YC separation processing, an intra-field YC separation processing, and a synthesis processing. Among them, the inter-frame YC separation process is a process for a still image, and the intra-field YC separation process is a process for a moving image. The results of these two YC separation processes are combined according to the amount of motion of the image. The amount of motion of the image is detected as one frame difference in the motion detection processing. In consideration of the fact that a difference value is likely to be large even with a slight movement of an image near an edge of an image, an edge amount is evaluated in addition to the one-frame difference in the synthesis processing.
This edge amount is detected together with one frame difference in the motion detection processing. The motion detection processing, the inter-frame YC separation processing, and the intra-field YC separation processing are executed in parallel.

As shown in FIG. 17, the motion detection process
Horizontal filters 104 and two addition / interpolation circuits 10
6, 107, and three magnitude judgment circuits 108, 109, 1
10, two field memories 121, 122, 1
This is realized with the line memories 131. The one-frame difference is obtained by the addition / interpolation circuit 106 of the difference between the current pixel data on the input data bus 151 and the pixel data of the previous frame output from the second field memory 122, and from the result, the magnitude determination circuit is used. Obtained at 108 by removing the isolated points. On the other hand, the larger of the horizontal difference and the vertical difference in the same field is set as the edge amount. The difference in the horizontal direction within the same field, that is, the difference between adjacent pixels on the same line is calculated based on the input data bus 15.
The pixel data is detected using the horizontal filter 104 from the pixel data on the first line. At this time, two multipliers in the horizontal filter 104 are used, and the coefficients of the respective multipliers are set to 1 and −1. The difference in the vertical direction in the same field, that is, the difference between the pixels of two adjacent lines, is the difference between the current pixel data on the input data bus 151 and the pixel data of the previous line output from the first line memory 131. It is detected by the addition / interpolation circuit 107. Then, the larger one of the two differences detected by the horizontal filter 104 and the addition / interpolation circuit 107 is selected by the size determination circuit 109, and the size determination circuit 11 is selected from the selection result.
By removing the isolated point at 0, the edge amount is obtained. The obtained one-frame difference and edge amount are supplied to the synthesis circuit 111 as control data C1 and C2.

The inter-frame YC separation processing is realized by one horizontal filter 103, one addition / interpolation circuit 105, and two field memories 121 and 122. First, the addition / interpolation circuit 105 calculates the sum of the current pixel data on the input data bus 151 and the pixel data of one frame before output from the second field memory 122. This sum is supplied to the synthesizing circuit 111 as a result of the inter-frame YC separation processing after the high frequency component is removed by the horizontal filter 103.

The in-field YC separation processing is realized by the vertical filter 101, one horizontal filter 102, and two line memories 131 and 132. The current pixel data on the input data bus 151 and the first line memory 13
The pixel data of one line before output from 1 and the pixel data of two lines before output from the second line memory 132 are processed by the vertical filter 101, and the result is further processed by the horizontal filter 102. Horizontal filter 102
Is supplied to the synthesizing circuit 111 as a result of the intra-field YC separation processing.

The combining process is realized by the combining circuit 111. The synthesizing circuit 111 outputs the 1
According to the frame difference and the edge amount, the output of the horizontal filter 103 as a result of the inter-frame YC separation and the output of the horizontal filter 102 as a result of the intra-field YC separation are combined, and the combined result is used as the first combination. Output data bus 1
52.

FIG. 18 is a diagram showing the flow of the signal processing (MUSE processing) in FIGS. 10 and 11. The MUSE processing realized by the connection of FIG. 10 and FIG. 11 includes a motion detection processing, an inter-frame interpolation processing, an inter-field interpolation processing, a field interpolation processing, and a synthesis processing. Of these, the frame interpolation processing and the field interpolation processing are still image processing, and the field interpolation processing is moving image processing. The results of the still image processing and the moving image processing are combined according to the amount of motion of the image. The amount of motion of the image is detected as a two-frame difference in the motion detection processing. For the same reason as described above, in the synthesizing process, the edge amount is evaluated in addition to the two-frame difference. This edge amount is detected together with the two-frame difference in the motion detection processing. The motion detection processing is realized by the connection of FIG. 10, and the other processing is realized by the connection of FIG. At this time, the two-frame difference and the edge amount obtained in the first half motion detection processing are temporarily stored in the data temporary holding device 141 for the synthesis processing in the second half processing, and the connection between FIG. The switching is performed every time one field of input image data is processed. Inter-frame interpolation and field interpolation in the latter half of processing
Executed in parallel with each other.

As shown in FIG. 18, the motion detection process
Horizontal filters 102, 103, 104, two addition / interpolation circuits 106, 107, and three magnitude determination circuits 1
08, 109, 110 and four field memories 12
1 to 124 and one line memory 131. The two-frame difference is obtained by adding the difference between the current pixel data on the input data bus 151 and the pixel data two frames before output from the fourth field memory 124 to the addition / interpolation circuit 1.
06, the result is obtained by removing isolated points from the result by the magnitude judgment circuit 108, and then performing frequency conversion processing by the horizontal filter 103. On the other hand, in the first line memory 131, the horizontal filter 102, the addition / interpolation circuit 107, and the size determination circuit 109, the larger of the horizontal difference and the vertical difference in the same field is determined as the edge amount. The points are the same as in the case of the EDTV processing. After the isolated point is removed from the output of the magnitude judgment circuit 109 by the magnitude judgment circuit 110, the horizontal filter 104 performs a frequency conversion process to obtain an edge amount. 2 obtained
The frame difference and the edge amount are stored in the data temporary holding device 141 via the first and second output data buses 152 and 153.
Is stored in

The still image processing of the latter half processing is performed by two horizontal filters 103 and 104 and three addition / interpolation circuits 1
05, 106, 107 and three field memories 12
1, 122, and 123. Addition / interpolation circuit 1
05 is the current pixel data on the input data bus 151 and the second
, By alternately selecting the pixel data of the previous frame output from the field memory 122. The addition / interpolation circuit 106 alternately selects the pixel data of the previous field output from the first field memory 121 and the pixel data of the previous field output from the third field memory 123 by alternately selecting the same. Perform inter-frame interpolation. The outputs of these two addition / interpolation circuits 105 and 106 are supplied to an addition / interpolation circuit 107 after being subjected to frequency conversion processing by two horizontal filters 103 and 104, respectively. The addition / interpolation circuit 107 alternately selects two frequency conversion results by the horizontal filters 103 and 104,
Perform field interpolation. The output of the addition / interpolation circuit 107 is supplied to the synthesis circuit 111 as a result of the still image processing.

The moving image processing includes a vertical filter 101, one horizontal filter 102, two line memories 131,
132. The current pixel data on the input data bus 151, the previous line of pixel data output from the first line memory 131, and the second line memory 132
And the pixel data of two lines before are output by the vertical filter 101 and the horizontal filter 102 sequentially.
The horizontal filter 102 performs both horizontal filtering in a two-dimensional filter and frequency conversion. The output of the horizontal filter 102 is supplied to the synthesis circuit 111 as a result of the moving image processing.

The synthesizing process is realized by the synthesizing circuit 111. The synthesizing circuit 111 includes a data temporary holding device 141
The output of the addition / interpolation circuit 107 as a result of the still image processing and the output of the horizontal filter 102 as a result of the moving image processing are combined in accordance with the two-frame difference and the edge amount read from. The synthesis result is output to the first output data bus 152.

As described above, according to this embodiment, one piece of hardware can be used for EDTV processing and MUSE processing. Further, since the temporary data holding device 141 for holding the intermediate result of the processing is provided, a series of algorithms of the MUSE processing can be divided into two parts and each part can be executed by the same hardware. Therefore, the amount of hardware for signal processing is significantly reduced as compared with the related art. However, if three horizontal filters and two addition / interpolation circuits are added, the provision of the data temporary holding device 141 is omitted, and the motion detection in the MUSE processing is performed as in the case of the EDTV processing. Processing and still image / moving image processing can be executed in parallel.

Further, in this embodiment, as shown in FIGS. 12 to 16, a firmware configuration is employed for each of the arithmetic units 101 to 111, so that the processing speed is increased as compared with the case where a general-purpose processor is used.

Further, in this embodiment, since a plurality of field memories 121 to 124 and a plurality of line memories 131 and 132 are used as memories for holding input data, a plurality of field memories 121 to 124 are used. Handle data freely. However, only one of the memories may be provided. Using a RAM (random access memory), necessary pixel data may be freely read and processed. When processing of data that is temporally separated from each other is not required, such as voice processing, a memory for input data may not be provided.

The number of arithmetic units and their types are arbitrary. If a 5-tap vertical filter is required, the line memory has a 5-stage configuration, and the arithmetic unit for the vertical filter has 5 inputs. In order to be able to handle digital image compressed data, an arithmetic unit for discrete cosine transform (DCT) may be employed.

Further, the switching between the connection in FIG. 10 and the connection in FIG. 11 in the MUSE process may be performed every time one line of input image data is processed. In this case, the pixel data used in the motion detection processing is stored in the line memories 131, 1
32, the still / moving image processing can be executed using the held data. Even if the first to third field memories 121 to 123 are not accessed again for still image / moving image processing, faster line memories 131 and 132 can be used.
It is convenient to access

The YC separation procedure for the EDTV system can be applied to other broadcasting systems requiring the YC separation such as the NTSC system and the EDTV II system. According to the present invention, in addition to these broadcasting systems, PAL (Phase Altern
ATV, which is a kind of digital system
A TV receiver capable of supporting at least two arbitrary broadcasting systems selected from various broadcasting systems including the (Advanced TV) system and the MUSE system can be realized.

[0060]

As described above, according to the present invention, a plurality of arithmetic means each having a basic function, a switch means for achieving a flexible connection between the plurality of arithmetic means, Since the signal processing apparatus is provided with an information holding means for holding arithmetic control information for specifying processing contents of the means and connection control information for specifying a connection mode in the switch means, the information holding means The effect that one hardware can be shared by a plurality of processing methods and a plurality of processing algorithms can be obtained simply by updating or switching the held information.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a TV receiver including a signal processing device according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating an internal configuration of the image processing apparatus in FIG. 1;

FIG. 3 is a circuit diagram showing an internal configuration of a bus switch in FIG. 2;

FIG. 4 is an explanatory diagram of a pipeline operation of four arithmetic units in FIG. 2;

FIG. 5 is an explanatory diagram of another type of pipeline operation of the arithmetic unit.

FIG. 6 is an explanatory diagram of still another type of pipeline operation of the arithmetic unit.

FIG. 7 is a block diagram illustrating a configuration of a signal processing device according to a second embodiment of the present invention.

FIG. 8 is a block diagram illustrating a configuration of a signal processing device according to a third embodiment of the present invention.

FIG. 9 is a block diagram illustrating a configuration of a signal processing device according to a fourth embodiment of the present invention, and also illustrates an internal connection of a bus switch when performing EDTV processing;

FIG. 10 is a diagram similar to FIG. 9, in which the signal processing device performs a motion detection process of the MUSE process.

FIG. 11 is a diagram similar to FIG. 9 in a case where still image / moving image processing of MUSE processing is performed by the signal processing device.

FIG. 12 is a block diagram showing an internal configuration of a vertical filter which is one of the arithmetic units in FIGS. 9 to 11 together with a control circuit thereof.

FIG. 13 is a block diagram showing an internal configuration of a horizontal filter as another arithmetic unit in FIGS. 9 to 11 together with a control circuit thereof.

FIG. 14 is a block diagram showing an internal configuration of an addition / interpolation circuit which is still another arithmetic unit in FIGS. 9 to 11 together with its control circuit.

FIG. 15 is a block diagram showing an internal configuration of a size determining circuit, which is still another arithmetic unit in FIGS. 9 to 11, together with its control circuit.

FIG. 16 is a block diagram showing an internal configuration of a synthesizing circuit, which is still another arithmetic unit in FIGS. 9 to 11, together with its control circuit.

17 is a diagram showing a flow of signal processing (EDTV processing) in FIG.

FIG. 18 shows the signal processing (MUS) shown in FIGS. 10 and 11;
FIG. 14 is a diagram showing a flow of (E processing).

FIG. 19 is a block diagram showing a configuration of a conventional TV receiver.

[Explanation of Signs] 1-4 arithmetic units 5-8, 5a-8a, 5b-8b arithmetic control registers 9, 21 bus switches 10 line memories 12, 12a, 12b, 22a, 22b connection control registers 13, 13a, 13b registers Set 14 Switching circuit 15 Switching control circuit 17 Register updating circuit 20 Input selector (input selection circuit) 23 to 27, 28 Selection circuit 100 Bus switch 101 Vertical filter 102 to 104 Horizontal filter 105 to 107 Addition / interpolation circuit 108 to 110 Large and small Judgment circuit 111 Synthesis circuit 121 to 124 Field memory 131, 132 Line memory 141 Data temporary storage device 204 Input data memory 205 Image processing device 206 Data temporary storage device

────────────────────────────────────────────────── ─── Continuation of the front page Examiner Norio Nishitani (56) References JP-A-6-6718 (JP, A) JP-A-5-35700 (JP, A) JP-A-5-91434 (JP, A) Kaihei 6-67876 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H04N 5/46 G06T 1/20

Claims (16)

(57) [Claims] 1. An output signal line having at least one input signal line and at least one output signal line, and outputting data obtained by subjecting data on the input signal line to arithmetic operation processing on the output signal line. (K is an integer equal to or more than 2) arithmetic means, and at least K + 1 input data lines and at least K + 1
K data lines among the K + 1 input data lines are connected to the K output signal lines of the K arithmetic means, and the K + 1 output data lines Are connected to K input signal lines of the K arithmetic means, and a switch for achieving a separable and exchangeable connection between the K + 1 input data lines and the K + 1 output data lines. Means, operation control information for specifying the content of the arithmetic operation processing of each of the K operation means, and K + 1 in the switch means
A signal processing device comprising: information holding means for holding connection control information for designating a connection mode between one input data line and K + 1 output data lines. 2. The signal processing device according to claim 1, further comprising: means for updating arithmetic control information and connection control information in said information holding means so as to switch processing of said signal processing apparatus. Characteristic signal processing device. 3. The signal processing device according to claim 1, wherein the information holding unit includes a plurality of rewritable register sets for holding the operation control information and the connection control information, respectively. Is one of the plurality of register sets so as to switch the processing of the signal processing device.
A signal processing apparatus, further comprising means for selecting one of the two. 4. The signal processing device according to claim 3, further comprising: means for updating the held information of another register set while one of the plurality of register sets is selected. Characteristic signal processing device. 5. The signal processing device according to claim 1, wherein the information holding unit includes a plurality of memory sets for fixedly holding the operation control information and the connection control information in advance , respectively. Is a signal processing device, further comprising: means for selecting any one of the plurality of memory sets so as to switch processing of the signal processing device. 6. The signal processing device according to claim 1, wherein said switch means comprises at least K + 1 first input data lines and at least K
K first output data lines, and the K first output data lines are connected to K input signal lines of the K arithmetic means, and the K + 1 first input data lines and K A first bus switch for achieving a separable and interchangeable connection with the first output data lines, at least K second input data lines and at least K + 1
K output data lines, the K second input data lines being connected to K output signal lines of the K arithmetic means, and the K + 1 second output data lines. Our K
The book is connected to K of the K + 1 first input data lines of the first bus switch, and is separable and exchangeable between the K second input data lines and K + 1 second output data lines. A second bus switch for achieving a possible connection. 7. An output signal line having at least one input signal line and at least one output signal line, and outputting data obtained by subjecting data on the input signal line to arithmetic operation processing on the output signal line. (K is an integer equal to or more than 2) arithmetic means, and at least K + 1 input data lines and at least K + 1
K data lines among the K + 1 input data lines are connected to the K output signal lines of the K arithmetic means, and the K + 1 output data lines Are connected to K input signal lines of the K arithmetic means, and a switch for achieving a separable and exchangeable connection between the K + 1 input data lines and the K + 1 output data lines. Means, operation control information for specifying the contents of arithmetic processing of each of the K operation means, and K + 1 in the switch means
A plurality of register sets for respectively holding connection control information for specifying a connection mode between the input data lines and the K + 1 output data lines; and the plurality of register sets so as to switch processing of the signal processing device. Signal processing means for selecting any one of the following: and means for updating information held in the plurality of register sets so as to switch processing of the signal processing device. apparatus. 8. The signal processing apparatus according to claim 7, and holds the input data, and the K Starring of K + 1 pieces of input data lines of said switch means the data the holding
Not connected to any of the K output signal lines of the calculating means.
A signal processing device further comprising an input data memory for supplying one of the input data lines . 9. The signal processing apparatus according to claim 7, wherein among the K + 1 pieces of output data lines of said switch means
Connected to any of the K input signal lines of the K arithmetic means
Hold the data output to one of the output data lines which are not connected , and transfer the held data to the K +
Of the one input data line , K K
A signal processing device further comprising a data temporary holding device for supplying one of input data lines not connected to any of the output signal lines . 10. The signal processing device according to claim 9, wherein one of input data and data held by said data temporary holding device is selected, and said selected data is used as K + 1 number of said switch means. wherein the input data line
Connected to any of the K output signal lines of the K arithmetic means
A signal processing device further comprising an input selection circuit for supplying one of the input data lines not connected . 11. The signal processing device according to claim 7, wherein the switch means has K + L + 1 (L is an integer of 2 or more) input data lines, and each of the signal processing devices has an input image of one field. holds data and before of K + L + 1 pieces of input data lines of said switch means for each pixel of the input image data the holding
Connect to any of the K output signal lines of the K arithmetic means
A signal processing apparatus further comprising: L field memories for supplying a corresponding one of the input data lines which are not processed. 12. The signal processing device according to claim 7, wherein the switch means has K + M + 1 (M is an integer of 2 or more) input data lines, and each of the signal processing devices has one line of input image. holds data and the K of K + M + 1 pieces of input data lines of said switch means input image data the holding for each pixel
Connected to any of the K output signal lines of the
A signal processing apparatus further comprising M line memories for supplying a corresponding one of the input data lines which are not used. 13. The signal processing device according to claim 7, wherein the switching of the signal processing by selecting the register set is performed every time one field of input image data is processed. 14. The signal processing apparatus according to claim 7, wherein the switching of the signal processing by selecting the register set is performed every time one line of input image data is processed. 15. The signal processing device according to claim 7, wherein the switching of the signal processing by updating the held information of the plurality of register sets is performed every time the broadcasting system of the input image data is switched. Signal processing device. 16. The signal processing device according to claim 7, wherein the K arithmetic means includes a vertical filter, a horizontal filter,
A signal processing device including an addition / interpolation circuit, a size determination circuit, and a synthesis circuit.