JP3388974B2 - Variable compression / expansion circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compression / expansion variable circuit which is used in, for example, a home wide television (hereinafter referred to as TV) receiver and which has a variable aspect ratio.

[0002]

2. Description of the Related Art As is well known, the aspect ratio (hereinafter, referred to as an aspect ratio) of a screen in a current TV receiver is 4: 3. Therefore, the current TV signal standard (NTSC) is
The video signal has an aspect ratio of 4: 3.

In addition, recently, a wide-screen TV receiver (hereinafter referred to as wide TV) capable of realizing the realism of a theater movie at home has been put on the market and has been well received. This wide TV
Is called a horizontal TV, and has an aspect ratio of 16: 9, which is about 1.3 times longer than the current TV receiver. Recently, a wide range of video software such as VTR (video tape recorder) and LD (laser disk) has begun to appear.

However, since the number of current TV receivers is still large in terms of the total number of TV receivers, the aspect ratio of 4: 3 is predominant in broadcasting and video software. Therefore, the wide-screen TV currently on sale has an aspect conversion function in order to have a compatibility function with the current TV system.

The aspect conversion function in wide TV will be described with reference to FIG. First, as shown in FIG. 5A, a video signal reproduced as a perfect circle when displayed on a current TV receiver is directly displayed on a wide TV receiver without any processing. As shown in the figure, the screen is reproduced in a horizontally extended form by the amount of the horizontally extended screen.

Therefore, in order to correct the distortion extended during this period, as shown in FIG. 5C, a function of inserting side panel signals to the left and right (either one may be right) and converting the aspect ratio of the video signal is provided. You will need it. Incidentally, FIG. 5 (c)
When a 4: 3 video signal is displayed on a 16: 9 wide TV screen, the video signal is horizontally compressed ¾ times and side panel signals are inserted on both sides of the video signal so that the video signal is not stretched. Is a display example of.

Further, as shown in FIG. 5 (d), a 4: 3 video signal is displayed on a 16: 9 wide screen,
There is also a non-linear companding processing method in which a perfect circle is displayed in the middle and the distortion is increased toward both ends of the screen. This method is a method for displaying a 4: 3 screen on a wide TV without a sense of discomfort by utilizing the fact that humans tend to concentrate and watch in the center of the screen.

As described above, when displaying a video signal with an aspect ratio of 4: 3 on a current wide TV receiver, horizontal compression and decompression processing is always required, and effective use of the wide screen is required. It is necessary to change the compression / expansion ratio.

A conventional compression / expansion variable circuit is shown in FIG.
It shows in (b). FIG. 6A shows a circuit configuration of a system for compressing / expanding variable processing of a video signal itself by using a line memory, and FIG. 6B shows a circuit configuration of compressing / expanding variable processing of a display image by utilizing deflection of a cathode ray tube. 3 shows a circuit configuration.

In FIG. 6A, the 4: 3 digital video signal input to the input terminal 10 is supplied to the interpolation filter 11. This interpolation filter 11 is basically an FI
It is composed of an R digital filter and compresses the input video signal according to the coefficient generated by the control circuit 12. For example, in the case of 3/4 compression, a coefficient corresponding to each pixel of the input video signal is multiplied to create a 3/4 compressed signal.

The output of the interpolation filter 11 is selectively supplied to the line memories 14 and 15 by the switch circuit 13, and the output of each line memory 14 and 15 is selectively led to the output terminal 17 by the switch circuit 16.

When the switch circuit 13 is tilted to the line memory 14 side, the line memory 14 is in the write mode and the line memory 15 is in the read mode.
Further, when the switch circuit 13 is tilted to the line memory 15 side, the line memory 14 is in the read mode and the line memory 15 is in the write mode. The switch circuit 16 always falls to the line memory 15 side when the switch circuit 13 falls to the line memory 14 side, and when the switch circuit 13 falls to the line memory 15 side,
It is controlled so as to always fall to the line memory 14 side. Further, the switch circuits 13 and 16 are controlled so as to be switched in one horizontal period.

The control circuit 12 is a line memory 1
4 and 15 are alternately switched to the write mode and the read mode for each horizontal period. Then, in the write mode, for example, in the case of 3/4 compression, a memory control signal for not writing one pixel out of four pixels is sent,
Every time 4 pieces of pixel data are input, 3 pieces of data are written. In the read mode, three out of four data written one horizontal period before are continuously read, and as a result, the data amount is increased by 3/4 to realize 3/4 compression.

The read outputs of the line memories 14 and 15 that realize the 3/4 compression by the above processing are sequentially selected and output by the switch circuit 16 and output from the output terminal 17 as a video signal after aspect conversion. The compression / expansion ratio can be changed by writing the coefficient and line memory,
It can be realized arbitrarily by read control.

In the configuration shown in FIG. 6 (b), the deflection control circuit 20 determines the compression / expansion ratio, generates the deflection control signal, and controls the deflection yoke in the cathode ray tube 21 of the wide TV receiver to scan lines. The speed of is changed according to the compression / expansion ratio. Thereby, an arbitrary compression / expansion ratio can be realized on the screen.

[0016]

However, in the conventional compression / expansion variable circuit using the line memory, the desired compression and expansion pixel data is created by using the interpolation filter. In this case, for a constant compression rate and expansion rate, only one type of interpolation filter coefficient is required, but in order to support many types of compression and extension, a coefficient according to the type is required, and the circuit scale is very large. growing. In addition, in the case of nonlinear compression and expansion, it is necessary to switch the coefficient in one horizontal period, and the memory write control must be controlled in conjunction with the coefficient, which makes the circuit configuration very complicated. .

Further, the conventional compression / expansion variable circuit utilizing the deflection of the cathode ray tube can be realized with a simple circuit configuration, but since the interpolation processing of the video signal is not performed, the pixel of the expansion portion becomes rough. There is.

An object of the present invention is to solve the above-mentioned problems, and to solve various kinds of compression and decompression, non-linear compression and decompression,
It is to provide a compression / expansion variable circuit that can be realized with the same circuit and a simple configuration.

[0019]

In order to solve the above-mentioned problems, a compression / expansion variable circuit according to the present invention converts a video signal of a first aspect ratio at a first sampling frequency into a screen of a second aspect ratio. A compression / expansion variable circuit for compressing / expanding at an arbitrary ratio determined according to the position on the line and converting into a video signal of the second aspect ratio at a second sampling frequency equal to or lower than the first sampling frequency. a is, as a reference value 1 the field <br/> element interval on the time axis of the video signal of the first aspect ratio, a pixel spacing on the line of the video signal of the first aspect ratio on the space when compressed extended in the given ratio and converted into a video signal of said second aspect ratio, the spacing value generating means for generating a distance value representing the distance between the apparent on the time axis of each pixel, the distance value Generation means Gate means for selectively deriving an interval value of each pixel generated, first cumulative addition means for accumulatively adding the interval value of each pixel derived from the gate means at the first sampling frequency, The second cumulative addition means for cumulatively adding the reference value 1 of the pixel interval at the first sampling frequency, the decimal part of the calculation result of the first cumulative addition means, and (1-fractional part) as the coefficient and interpolation means pixel data for one of the aspect ratio of the video signal you interpolate sequentially written into the storage unit the image element data generated by the interpolation processing means in said first sample frequency, written from the storage unit The second sample frequency by sequentially reading out and outputting the pixel data stored at the second sample frequency.
The sample frequency conversion means for generating a video signal of the second aspect ratio by the above and the integer parts of the calculation results of the first and second cumulative addition means are compared, and when they match, Comparing control means for setting the storage unit in a write state and for setting the gate unit in an input state, and for disagreeing, for setting the storage unit in a write-inhibited state and for setting the gate unit in an input-off state. did.

[0020]

Further, an initialization means is provided for clearing the calculation results of the first and second cumulative addition means for each line input of the video signal of the first aspect ratio.

On the time axis when the interval value generating means converts the video signal of the first aspect ratio into the video signal of the second aspect ratio at a constant ratio in space.
The interval value for the reference value 1 representing the pixel interval of is set as a reference interval value, the location information on the line and a correction value corresponding to an arbitrary compression / expansion ratio at that location are input, and each pixel corresponding to the location information is input. The reference interval value of is corrected with the correction value, and the apparent interval on the time axis of each pixel is
The interval value that indicates is generated .

The location information is the second aspect ratio.
Based on the horizontal sync signal of one horizontal period of the video signal of
It was assumed to be an arbitrary position until the next horizontal synchronizing signal.

The compression / expansion variable circuit configured as described above can generate various kinds of compression / expansion, non-linear compression / expansion coefficient and write control signal with the same circuit, and therefore the circuit scale is small and It can be realized with a simple configuration.

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to FIGS.

FIG. 1 shows, as a first embodiment, a configuration in which compression and expansion are changed at a fixed rate.
The digital video signal input to the input terminal 30 is supplied to the interpolation filter 31. The interpolation filter 31 is basically a 2-tap filter, and the flip-flop circuit 3
2, the multipliers 33 and 34, and the adder 36.

That is, the input digital video signal is input to the flip-flop circuit 32 and is equivalent to 6 fsc (fsc
The color subcarrier: 6 fsc is sampled at a clock of about 21 MHz) and supplied to the first multiplier 33 and the second multiplier 34. The first and second multipliers 33 and 34 each input a coefficient and multiply the input video signal, and the respective arithmetic outputs are added by the adder 36 to the memory circuit 37 that performs horizontal compression and expansion operations. Supplied.

The memory circuit 37 is composed of a line memory capable of storing one horizontal period of the TV signal, and is in a write state when the write enable signal WE is at H level, and is in a write prohibited state when it is at L level. Then, the write processing is performed with the write clock WCK corresponding to 6 fsc, and 4 fs
The read processing is performed with the read clock RCK corresponding to c. The read output of the memory circuit 37 is output from the output terminal 38 as an output video signal.

Generation of coefficients for the interpolation filter 31 and generation of a write enable signal for the memory 37 will be described below.

In order to determine the aspect ratio of the output side through the serial bus or the like, the input terminal 40 is input with the sample interval value of the image signal of the aspect ratio of the output side with respect to the sample interval of the image signal of the aspect ratio of the input side. It
This sample interval value is input to the AND (logical product) circuit 41, and when the other input is at high level, the cumulative adder 42
Is supplied to.

The cumulative adder 42 is composed of an adder 43 and a flip-flop circuit 44. The adder 43 adds the cumulative addition result to the input sample interval value, and the addition result is the sampling frequency of the input digital video signal. 6 fsc
Cumulatively add with the clock. The cumulative addition result is cleared every horizontal period by the horizontal clear signal ΗCL input from the input terminal 45.

The output of the cumulative adder 42 is divided by the separation circuit 48 into a decimal part and an integer part. The fractional part becomes a coefficient of the interpolation filter 31 and is supplied to the multiplier 34. Further, a value obtained by subtracting the fractional part from 1 by the subtractor 35 is input to the multiplier 33 as a coefficient.

On the other hand, the integer part is supplied to the comparison circuit 47. The comparison circuit 47 compares the output of the counter circuit 46 with the above integer part, and sets the output level to the Η level only when the levels of both match. The counter circuit 46 counts at the sampling frequency 6 fsc of the input video signal, and like the cumulative adder 42, the horizontal clear signal ΗC
It is cleared by L every horizontal period. That is, the counter circuit 46 cumulatively adds the sample interval value of the video signal having the aspect ratio on the input side at the sample frequency.

The output of the comparison circuit 47 is supplied to the memory circuit 37 as a write enable signal WE, and at the same time AN
It is supplied to the D circuit 41. The AND circuit 41 controls so that the sampling clock is not added to the cumulative adder 42 when the outputs of the comparison circuit 47 do not match, that is, at the L level.

The compression / expansion variable circuit configured as described above can perform horizontal expansion processing in addition to horizontal compression processing. In order to realize the expansion processing, the sampling frequency of the input digital video signal is set higher than the sampling frequency of the output video signal.

In the present embodiment, the frequency of the input video signal is 1.5 times that of the output video signal, that is, the sampling frequency of the input video signal is 6 fsc (about 21 MHz) and the sampling frequency of the output video signal is 4 fsc (about 14 MHz). In order to simplify the description, the number of samples in one horizontal period of the input digital video signal will be described as 8 points.

First, FIG. 2A shows an example in the case of expanding by 1.5 times. In this case, the final output video signal is 4f.
The input signal is 6 fsc (WC
K), write all to memory 37, and output the signal at 4 fsc
If it is read out at the sampling frequency RCK of 1, the 1.5 times expansion can be realized. The sample interval of the output video signal in this case is
Since all input samples are output, the input sample interval is 1, which is the same as the input sample interval.

Next, FIG. 2B shows an example of the case without compression / expansion. In this case as well, the output video signal is read out at 4 fsc, so one out of every three input samples (marked x in the figure)
Of the interpolation filter 31
Then, it is necessary to produce an output video signal by applying a coefficient corresponding to the position of the output video signal to the input signal.

In this case, for example, the first sample point of the output video signal is located in the middle of the first and second points of the input video signal. I am hanging. When the input sample interval is 1 as the sample interval, the number of output samples is apparently 1 / 1.5, and the sample interval of the output video signal is 1.5.

Next, FIG. 2C shows an example in the case of 3/4 compression. In this case, 1 / 1.5 of that without compression
In addition to doubling, the number of output samples is (1 / 1.5) × (3 /
4) = 1/2 needs to be set. For this reason, control is performed so that one in two input samples is written during memory writing. At this time, the sampling interval is 2.

Regarding other compression / decompression, various compression / decompression processes can be realized by appropriately selecting the sample interval value. However, input at 6 fsc and enter at 4 fs
In the above example of outputting with c, the expansion operation is up to 1.5 times.

Therefore, according to the above configuration, arbitrary fixed compression / expansion can be realized by a simple circuit. By using this compression / expansion variable circuit, it is possible to convert the video signal of the aspect ratio on the input side into the video signal of the arbitrary aspect ratio by applying arbitrary fixed compression and expansion.

However, in order to realize the expansion processing, it is assumed that the sampling frequency of the video signal having the aspect ratio on the input side is equal to or higher than the sampling frequency of the video signal having the aspect ratio on the output side.

FIG. 3 shows, as a second embodiment, a configuration for changing compression and expansion at a non-linear rate. In FIG. 3, the same parts as those in FIG. 1 are designated by the same reference numerals, and only different parts will be described here.

In FIG. 3, the serial bus input terminal 50
In, is input sample information including a sample interval value, location information indicating a horizontal pixel position (or a vertical line position), and a sample interval correction value at that location. The input sample information is supplied to the serial bus control circuit 51,
It is divided into sample interval values, location information, and correction values. still,
The location information is an arbitrary position up to the next horizontal synchronizing signal with reference to the horizontal synchronizing signal in one horizontal period of the video signal.

The three data divided here are supplied to the data control circuit 52. This data control circuit 51 is
A sample interval correction value corresponding to the sample interval value and the input location information is output. These data are added by adder 5
3, the sample interval value is added to the sample interval correction value and corrected to a value corresponding to the location. The output of the adder 53 is input to the AND circuit 41 described above, and thereafter processed in the same manner as in the case of the first embodiment shown in FIG.

A case where the sampling interval is set to 1.5 in the compression / expansion variable circuit having the above configuration will be described. Here, the location information for realizing the non-linearity and the correction value of the sample interval at that location are 0.10 at the location of sample 0 and 0.13 at the location of sample 5.

First, as shown in FIG. 4, the outputs of the cumulative adder 42 are 0, 1.
It becomes 6,3.2,3.2,4.8. From the fifth sample, the correction value changes to 0.13, so 6.4
It will be 3, 6.43, 8.06. Non-linear processing can be realized by giving the decimal value as a coefficient of the interpolation filter 31. In this embodiment, the correction value is input as a positive value, but a negative value does not cause any problem.

The compression / expansion variable circuit configured as described above can realize flexible non-linear compression and expansion processing with a simple circuit structure, and further, when integrated into an integrated circuit, the circuit scale can be greatly reduced. This makes it possible to realize a very inexpensive aspect conversion system. By using this compression / expansion variable circuit, it is possible to convert the video signal having the aspect ratio on the input side into the video signal having the arbitrary aspect ratio by performing arbitrary nonlinear compression and expansion.

However, also in this case, in order to realize the expansion processing, it is assumed that the sampling frequency of the video signal having the aspect ratio on the input side is equal to or higher than the sampling frequency of the video signal having the aspect ratio on the output side.

In the above embodiment, the case of the compression / expansion variable processing in the horizontal direction has been described, but the compression / expansion variable processing in the vertical direction can also be realized by the same processing.

[0052]

As described above, according to the present invention, it is possible to provide a compression / expansion variable circuit which can be realized with the same circuit and with a simple structure for various kinds of compression / expansion and nonlinear compression / expansion. .

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing the configuration of a first embodiment of a fixed compression / expansion variable circuit according to the present invention.

FIG. 2 is a timing chart for explaining a processing operation of the embodiment.

FIG. 3 shows a second nonlinear compression / expansion variable circuit according to the present invention.
2 is a block circuit diagram showing the configuration of the embodiment of FIG.

FIG. 4 is a timing chart for explaining a processing operation of the embodiment.

FIG. 5 is a diagram showing a display example of a wide TV receiver to which the present invention is applied.

FIG. 6 is a block circuit diagram showing a specific example of a conventional compression / expansion variable circuit.

[Explanation of symbols]

10 ... Digital video signal input terminal, 11 ... Interpolation filter, 12 ... Control circuit, 13 ... Switch circuit, 1
4, 15 ... Line memory, 16 ... Switch circuit, 17 ...
Output terminal, 20 ... Deflection control circuit, 21 ... CRT, 3
0 ... Digital video signal input terminal, 31 ... Interpolation filter,
32 ... Flip-flop circuit, 33, 34 ... Multiplier, 3
6 ... Adder, 37 ... Memory circuit, 38 ... Video signal output terminal, 40 ... Sampling interval input terminal, 41 ... AND circuit, 42 ... Cumulative adder, 43 ... Adder, 44 ... Flip-flop circuit, 45 ... Horizontal Clear signal input terminal, 46 ...
Counter circuit, 47 ... Comparison circuit, 48 ... Fractional part / integer part separation circuit, 50 ... Serial bus input terminal, 51 ... Serial bus control circuit, 52 ... Data control circuit, 53 ... Adder.

Front Page Continuation (72) Inventor Naoki Akamatsu 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Inside Multimedia Technology Laboratory, Toshiba Corp. (56) Reference JP-A-5-260445 (JP, A) JP-A-2 -53266 (JP, A) JP-A-7-298087 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04N 5/66 H04N 7/01 H04N 1/393 G09G 5/00 G06F 15/66

Claims (4)

(57) [Claims] 1. A video signal of a first aspect ratio at a first sample frequency is compressed and expanded at an arbitrary ratio determined according to a location on a line of a screen of a second aspect ratio, A compression / expansion variable circuit for converting into a video signal of the second aspect ratio at a second sample frequency equal to or lower than a sample frequency of 1, wherein a pixel interval on the time axis of the video signal of the first aspect ratio is used as a reference. the value 1, when converted into a video signal of the first pixel spacing on the line of the video signal of aspect ratio compression and expansion at the given ratio and the second aspect ratio on the space, the time of each pixel Interval value generating means for generating an interval value representing an apparent interval on the axis, gate means for selectively deriving an interval value of each pixel generated by the interval value generating means, and from the gate means First cumulative addition means for cumulatively adding the derived interval value of each pixel at the first sample frequency, and second cumulative addition for cumulatively adding the pixel interval reference value 1 at the first sample frequency. Means, a decimal part of the calculation result of the first cumulative addition means, and (1-
And interpolation processing means you interpolate the pixel data of the video signal of the first aspect ratio fractional portion) as a coefficient, in the storage unit the image element data generated by the interpolation processing means in said first sample frequency Sequential writing is performed, and the pixel data written from the storage unit is sequentially read and output at a second sampling frequency to output the second sampling frequency.
The sample frequency conversion means for generating a video signal of the second aspect ratio by the number and the respective integer parts of the calculation results of the first and second cumulative addition means are compared, and when they match, Sets the storage unit to a write state and the gate means to an input state,
A compression / expansion variable circuit, comprising: a comparison control unit that sets the storage unit to a write-inhibited state and sets the gate unit to an input disconnected state when they do not match. 2. The initialization means for clearing the calculation results of the first and second cumulative addition means for each line input of the video signal of the first aspect ratio. The variable compression / expansion circuit described. 3. The time axis when the interval value generating means converts the video signal of the first aspect ratio into the video signal of the second aspect ratio at a fixed ratio in space.
An interval value with respect to the reference value 1 representing the upper pixel interval is set as a reference interval value, and position information on the line and a correction value corresponding to an arbitrary compression / expansion ratio at that position are input, and each of the values corresponding to the position information is input. The reference interval value of the pixel is corrected by the correction value, and the apparent interval on the time axis of each pixel is
2. The variable compression / expansion circuit according to claim 1 , wherein an interval value indicating a distance is generated . 4. The location information is the second aspect.
4. The compression / expansion variable circuit according to claim 3, wherein the ratio of the video signal is an arbitrary position between the horizontal synchronization signals of one horizontal period and the next horizontal synchronization signal.