JP3314885B2 - Software processing method in sequence controller system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sequence controller system installed at a manufacturing site such as a steel plant, an automobile manufacturing plant, etc., and more particularly, to multiplexing of the systems, load distribution (load leveling), or a sequence controller. The present invention relates to a software processing method that does not depend on the physical structure of a sequence controller system and that can easily realize an extension or the like.

[0002]

2. Description of the Related Art Conventionally, the configuration of a sequence controller system is as shown in FIGS. FIG.
, The I / O device 6 and the I / O device 7
Input the signal from. The CPU device 4 receives the signal via the communication line 2, performs a sequence processing operation on the signal, and outputs a signal of the operation result via the communication line 2 to the I / O.
The data is transmitted to the O device 6 and the I / O device 7. I / O devices 6 and I
The / O device 7 outputs the signal to the mechanical device 10. I /
The O device 8 and the I / O device 9 receive signals from the mechanical device 10. The CPU device 5 receives the signal via the communication line 3, performs a sequence processing operation on the signal, and transmits a signal of the operation result to the I / O device 8 via the communication line 3.
It transmits to the O device 9. The I / O device 8 and the I / O device 9 output the signal to the mechanical device 10. In FIG.
The I / O device 17, the I / O device 18, and the I / O device 19 receive signals from the mechanical device 20. The IOP device 15 receives the signal via the communication line 16. CPU device 11,
The CPU device 12 and the CPU device 13 input the signal from the IOP device 15 via the bus signal line 14. CPU
The device 11, the CPU device 12, and the CPU device 13 operate simultaneously, perform a sequence processing operation on the signal, and transmit a signal of the operation result to the IOP device 1 via the bus signal line 14.
5 is output. The IOP device 15 transmits the signal to the communication line 16
To the I / O device 17, the I / O device 18, and the I / O device 19. I / O device 17, I / O device 18,
The I / O device 19 outputs the signal to the mechanical device 20.

[0003]

However, FIG.
In such a conventional system, for example, the CPU device 4 cannot directly receive a signal from the I / O device 8. If an attempt is made to receive, the CPU device 4 and the CPU device 5 are connected by another communication line 1 and received by the route of the I / O device 8-communication line 3-CPU device 5-communication line 1-CPU device 4. In other words, the communication efficiency is poor because the signal passes through an extra communication line. This is a drawback of the hierarchical system. Further, in the conventional system as shown in FIG. 11, each CPU device can share each I / O device, and can freely communicate via the bus signal line 14. For this reason C
Although it is possible to multiplex PU devices and to distribute the load on the CPU device, the IOP device 1
If 5 fails, there is a significant weak point that the system will stop working altogether. Accordingly, an object of the present invention is to provide a method that facilitates CPU multiplexing, load distribution between CPUs, and system expansion.

[0004]

In order to solve the above problems, a first means according to the present invention comprises a plurality of CPU devices which incorporate a plurality of sequence programs and perform a logical operation;
A plurality of I / O devices for performing interface processing of a signal of a mechanical device to be controlled are connected via a communication line, message communication is performed by broadcast communication, and each of the devices is transmitted in a predetermined order between the devices. In a sequence controller system in which a device transmits and receives the message in a token ring system in which a token is exchanged, all the CPUs
One transmission line to which the devices and I / O devices are directly connected, a CPU built in each I / O device, and all CPs
A software module which is built in at least one of a U device and an I / O device and has a data buffer for storing data included in an input signal message and an output signal message belonging to each of the I / O devices; And an identification code included in the output signal message so that the software module can determine the source of each message;
A synchronization flag for an input signal message and an output signal message, the flag being built in a device and an I / O device and comprising flag bits in which when a message is transmitted or received, all bits corresponding to the message become 1. Each I / O device starts inputting a signal from the mechanical device when the input signal message synchronization flag becomes all 0, and each CPU device outputs a logic signal when the input signal message synchronization flag becomes all 1 The operation is started and each I /
The O device starts outputting a signal to the mechanical device when the output signal message synchronization flag becomes all ones. The second means of the present invention further comprises the same software module incorporated in the plurality of CPUs in the first means, and transmits the output signal message only when the output signal message synchronization flag corresponding to each software module is 0. Add features.

[0005]

According to the above-mentioned means, even if the physical position of the I / O device on the communication line is changed, the setting change of the CPU device and the change of the C device can be performed.
There is no need to change the sequence processing program in the PU device. Even if the sequence processing program is transferred to another CPU device, there is no need to change the setting of the I / O device. Even if a new CPU device or I / O device is added on the communication line, it is necessary to change the setting of the existing CPU device, change the sequence processing program in the CPU device, or change the setting of the I / O device. Absent. Instead of multiplexing in units of CPU devices, multiplexing in units of sequence processing programs becomes possible, and a detailed multiplexing system can be realized. In addition, it is easy to multiplex necessary sequence programs after the system operation starts. Further, if a sequence processing program with a large load (long processing time) is found after the start of operation, it is not necessary to change the settings of other programs or hardware even if the program is transferred to a CPU device with a light load.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a system example of a sequence controller having a configuration in which each CPU device and each I / O device are directly connected to a communication line, and mainly describes a physical configuration of the system.
Referring to FIG. 1, an I / O1 device 25 receives an I1 input signal 28 from a mechanical device 34 and outputs an O1 output signal 29 to the mechanical device 34. The I / O2 device 26 is a mechanical device 34
Input the I2 input signal 30 and output the O2 output signal 31 to the mechanical device. The I / O3 device 27 is the mechanical device 3
4 to input an I3 input signal 32 and output an O3 output signal 33 to a mechanical device 34. I / O1 device 25, I / O2
The device 26 and the I / O3 device 27 transmit the I1 input signal 28, the I2 input signal 30, and the I3 input signal 32 to the communication line 2 respectively.
4, CPU1 device 21, CPU2 device 22, C
The data is transmitted to the PU3 device 23. Each CPU device performs a logical operation on the signal, and outputs O1 output signals 29 and O
2 output signal 31 and O3 output signal 33
The data is transmitted to the first device 25, the I / O2 device 26, and the I / O3 device 27 via the communication line 24. As described above, since all CPU devices and all I / O devices are directly connected to one signal line, the system configuration includes not only communication between CPU devices but also C
Free communication between PU devices and I / O devices, sharing of multiple I / O devices by each CPU device, multiplexing of CPU devices, or changing existing hardware and software New CPU device and I / O
This is a prerequisite to be able to add devices. The transmission line may be a serial communication line or a parallel signal bus. FIG. 2 is a diagram for explaining a logical configuration of the system shown in FIG. The software modules used in FIG. 2 are defined in FIG. I / O
One device 25 sends the I1 input signal together with the identification code IM1 to the P1 software module 38 in the form of an input signal message 41. P1 software module 38
Performs a logical operation on the I1 input signal, and transmits an O1 output signal as a result of the operation together with the identification code OM1 to the I / O1 device 25 in the form of an output message 42. I
The / O2 device 26 sends the I2 input signal together with the identification code IM2 to the P2 software module 39 in the form of an input signal message 43. The P2 software module 39 performs a logical operation on the I2 input signal, and transmits the O2 output signal as a result of the operation together with the identification code OM2 to the I / O2 device 26 in the form of an output signal message 44. The I / O3 device 27 converts the I3 input signal to an identification code I
Along with M3, an input signal message 45 is transmitted to the P3 software module 40. The P3 software module 40 performs a logical operation on the I3 input signal, and outputs the O3 output signal as the operation result as the identification code O.
I / O3 device 2 in the form of output message 46 with M3
7 P1 software module 38 is CP
It exists in the U1 device 21 and the CPU2 device 22. P2
The software module 39 includes the CPU 1 device 21 and the CP
It exists in the U2 device 22 and the CPU3 device 23. P
The 3 software module 40 exists only in the CPU 3 device 23. As described above, each software module exists in a plurality of CPU devices. P1 software module 38 responds to IM1 input signal messages 41 only. P2 software module 39 responds to IM2 input signal message 43 only. P3 software module 40 responds to IM3 input signal message 45 only. The relationship between the software module and the message is independent of the CPU device that is the physical container. A message exchanged between the I / O device and the CPU device is performed in the form of broadcast communication without specifying a physical communication address. Therefore, for example, the P1 software module 38 in the CPU 1
There is no need to change the hardware or software related to the system configuration even when transferring to the three devices 23. In FIG.
FIG. 2 is a diagram showing a functional configuration of an I / O1 device 25. I / O2
Since the functional configurations of the device 26 and the I / O3 device 27 are the same as those of the I / O1 device, only the I / O1 device 25 will be described below. In FIG. 3, 25 is an I / O1 device, 50
Is a communication interface, 51 is a control program, and 52 is a microprocessor that operates according to the control program 51. 53 is a synchronization flag for judging the timing of sending the input signal and the output signal from the I / O device,
This will be described in detail with reference to FIG. 55 is a software module, I
B1 input signal buffer 56, OB1 output signal buffer 5
7 and a sequence program 58. Next, the operation will be described. Microprocessor 5
2 operates according to the control program 51. The control program 51 is a basic program for controlling the entire inside of the I / O1 device 25, and its details will be described with reference to FIG. Microprocessor 52 receives I1 input signal 28 from machine 34 via input / output interface 54 and stores the signal in IB1 input signal buffer 56. Next, the I1 input signal in the IB1 input signal buffer 56 is transmitted to the communication line by the communication interface 50 in the form of the input signal message 41 together with the identification code IM1. Conversely, when the communication interface 50 receives the output signal message 42 including the O1 output signal and the identification code OM1, the microprocessor 52 outputs the output signal message 42.
Are stored in the OB1 output signal buffer 57. Next, the microprocessor reads the O1 output signal 29 in the OB1 output signal buffer 57 and outputs it to the mechanical device 34 via the input / output interface 54.
FIG. 4 is a diagram showing a functional configuration of the CPU 1 device 21. C
Since the configurations of the PU2 device 22 and the CPU3 device 23 are the same as those of the CPU1 device 21, only the CPU1 device 21 will be described below. In FIG. 4, reference numerals 38 and 39 denote software modules built in the CPU 1 as described with reference to FIG. 2. The configuration of the software module 38 is as follows. 63 is an IB1 input signal buffer for storing an I1 input signal. , 64 are an OB1 output signal buffer for storing the O1 output signal, and 65 is a sequence program. Next, the operation will be described. The microprocessor 70 operates according to the control program 71. The control program 71 is a basic program for controlling the whole of the inside of the CPU 1 device 21, and its details will be described in the description of FIG. Communication interface 72 receives input signal message 4
Upon receiving a 1, the microprocessor 70 stores the I1 input signal in the input signal message 41 in the IB1 input signal buffer 63 in the P1 software module 38. When the communication interface 72 receives the input signal message 43, the microprocessor 70 stores the I2 input signal in the input signal message 43 in the IB2 input signal buffer 66 in the P2 software module 39. I1 input signal and I2 required by P1 software module 38 and P2 software module 39
When the input signals are ready, the microprocessor 70 executes the sequence program 65 of the P1 software module. The sequence program 65 performs a logical operation on the I1 input signal, and stores the O1 output signal, which is the operation result, in the OB1 output signal buffer 64. Next, the microprocessor 70 reads the O1 signal from the OB1 output signal buffer, and sends the O1 signal together with the identification code OM1 to the communication line in the form of the output signal message 42 by the communication interface 72. Subsequently, the microprocessor 70 executes the sequence program 68 of the P2 software module. The sequence program 68 performs a logical operation on the I2 input signal, and stores the O2 output signal, which is the operation result, in the OB2 output signal buffer 67. Next, the microprocessor 70 reads the O2 output signal from the OB2 output signal buffer, and sends out the O2 output signal together with the identification code OM2 to the communication line in the form of the output signal message 44 by the communication interface 72. FIG. 5 is a diagram showing the configuration of the synchronization flag 53 of FIG. 3 and the synchronization flag 69 of FIG. This synchronization flag is possessed by all CPU devices and all I / O devices and has the same bit configuration. In FIG. 5, the IF1 flag bit 77 indicates when the I / O1 device 25 has transmitted the IM1 input signal message 41 and when all other devices (CP
U1 and I / O devices) receive an IM1 input signal message 41 and become 1 in each device.
IF2 flag bit 78 indicates that I / O2 device 26
Becomes 1 in each device when transmitting the input signal message 43 and when all other devices receive the IM2 input signal message 43. IF3 flag bit 7
9 indicates that the I / O3 device 27 sends the IM3 input signal message 4
5 in each device when it sends 5 and when all other devices receive the IM3 input signal message 45. The OF1 flag bit 80 will be 1 in each device when the P1 software module 38 sends the OM1 output signal message 42 and when all other devices receive the OM1 output signal message 42. The OF2 flag bit 81 becomes 1 in each device when the P2 software module 39 sends the OM2 output signal message 44 and when all other devices receive the OM2 output signal message 44. O
The F3 flag bit 82 becomes 1 in each device when the P3 software module 40 sends the OM3 output signal message 46 and when all other devices receive the OM3 output signal message 46. The operation of the synchronization flag will be described in detail with reference to FIGS. FIG.
This indicates the order in which the O device and the CPU device acquire the right to send a message. In the present invention, a token ring system is used. Hereinafter, a description will be given on the assumption that the I / O1 device has initially acquired the transmission right. When the I / O1 device finishes transmitting the IM1 input signal message, it subsequently sends a token for giving the transmission right to the I / O2 device. When the I / O2 device receives the token, it has acquired the transmission right,
The two devices send an IM2 input signal message. When the transmission is completed, a token for transferring the transmission right to the I / O3 device is transmitted. Similarly, the transmission right is transferred to the CPU 1, the CPU 2, and the CPU 3 in the same manner, and the I / O is performed again.
One device acquires the transmission right. Such an operation is performed endlessly and periodically. FIG. 7 is a time chart showing the operation of the entire system. The description starts from the left end of FIG. First, the I / O1 device 25 transmits the IM1 input signal message 41. This message is received by all devices except the I / O1 device. CPU1
In the device 21, the microprocessor 70 of FIG. 4 converts the I1 input signal in the received IM1 input signal message to the IB1 input signal buffer 63, because the P1 software module 38 is responsive to the IM1 input signal message.
To be stored. As shown in FIG. 2, the same thing as the CPU1 device 21 occurs because the P1 software module 38 that responds to the IM1 input signal message also exists in the CPU2 device 22. That is, the microprocessor of the CPU2 device 22 stores the I1 input signal in the received IM1 input signal message in the input signal buffer of the P1 software module. As shown in FIG. 2, there is no P1 software module in the CPU3 device 23 that responds to the IM1 input signal message. Therefore, the microprocessor in the CPU3 device 23 does not store the I1 input signal in the received IM1 input signal message. Then I
The / O2 device 26 sends an IM2 input signal message 43. This message is also received by all devices except the I / O2 device. As shown in FIG.
Due to the presence of the P2 software module 39 that responds to the input signal message, the microprocessor in each CPU unit will send the I2
2 Store the input signal in the input signal buffer of the P2 software module. Next, the I / O3 device transmits an IM3 input signal message 45. This message is also I / O3
All devices except the device receive. CPU as shown in FIG.
3 device 23 has a P3 software module that responds to the IM3 input signal message,
3 The microprocessor of the device 23 stores the I3 input signal in the received IM3 input signal message in the input signal buffer of the P3 software module. Since there is no program in the CPU1 device and the CPU2 device that responds to the IM3 input signal message, the microprocessors of both CPU devices do not store the I3 input signal in the received IM3 input signal message. Next, when the transmission of all the IM1 input signal message 41, the IM2 input signal message 43, and the IM3 input signal message 45 is completed, all the I / O devices simultaneously transmit the I1 input signal 86, the I2 input signal 87, the I3 input signal from the mechanical device. Each of the signals 88 is input and stored in an input signal buffer of each I / O device.
The signal input at this time is used in the next cycle. Next, in each CPU device, the IM1 input signal message 41, IM2
Input signal message 43, IM3 input signal message 4
Upon completion of receiving all the messages of No. 5, the microprocessors of the respective CPU units simultaneously start executing the sequence program. The CPU 1 device and the CPU 2 device simultaneously execute the same sequence program 65 (FIGS. 89 and 9).
0). As a result of the execution, the CPU1 device sends an OM1 output signal message 42. However, the CPU2 device does not send the OM1 output signal message. The reason is that as shown in FIG. 6, the CPU 1 acquires the transmission right first, and the OM 1
From the transmission of the output signal message (42 in the figure), the CP
The U2 device does not need to send an OM1 output signal message. Thereafter, the CPU1 device and the CPU2 device start executing the same sequence program 68 (FIGS. 92 and 9).
3). Here, if the CPU 1 device has failed, C
So-called multiplexing, in which the PU2 device transmits the OM1 message on behalf of the CPU1 device, is easily achieved. CP
The U3 device executes the sequence program in the P3 software module and sends an OM3 output signal message (46 in the figure). Subsequently, the CPU 3 executes the P2 sequence program (94 in the figure). When the execution of the P2 sequence program ends, the CPU3 device transmits the OM2 output signal message 44 because it has not been transmitted from another CPU device. When this transmission ends C
Although the PU1 device and the CPU2 device are still executing the P2 sequence program, when both CPU devices receive the OM2 output signal message 44, the microprocessors of both CPU devices stop executing the P2 sequence program halfway. This is an example of load leveling. Finally, all the I / O devices output the OM1 output signal message 42, OM
Since all of the 2 output signal messages 44 and the OM3 output signal message 46 have been received, each I / O
The signals of the output signal buffer of the device are simultaneously output to the mechanical device. The output signals are an O1 output signal 98, an O2 output signal 99, and an O3 output signal 100. Thus, one cycle of the operation of the sequence controller system shown in FIG. 1 is completed. FIG. 8 shows a control program 5 for the I / O1 device shown in FIG.
FIG. 3 is a diagram illustrating processing contents of No. 1; In FIG. 8, the processing content is divided into processing 1 and processing 2. The process 1 is executed in a manner interrupting the process 2. Process 1 is started when the communication interface receives something and sends something. Process 2 is started from process 1. First, processing 1
Will be described in the order of processing step numbers. “N” in the description is 1, 2, or 3. 101 When process 1 is started, it is checked whether reception is completed or transmission is completed. If NO, processing 1 ends. It checks whether a 102 token has been received. If YES, process 2 is started. Treatment 2 is IMn
An input signal message is transmitted (step 117). Check if 104 IMn input signal message was received or transmitted. If 105 YES, set the IFn flag bit corresponding to the IMn input signal message to 1. 106 Flag bits IF1, IF2, IF3 are all 1
Find out if If YES, process 2 is started. Process 2 receives a signal from a mechanical device (step 120). Check whether a 108 OMn output signal message has been received. 109 If YES, set the OFn flag bit to 1. Check to see if the 110OMn output signal message is to be output to the machine at your I / O device. 111 YES if O in OMn output signal message
The n output signal is stored in the OBn output signal buffer. 112 It is checked whether all of the flag bits OF1, OF2, OF3 are 1. If YES, process 2 is started. Process 2 outputs a signal to the mechanical device (step 123). Next, the content of the process 2 will be described. 114 When this I / O device starts, it first receives the In input signal from the mechanical device and stores it in the IBn input signal buffer. Check whether the token has been received. If NO, the process waits until the process 1 is started from 103. 117 If YES, the IBn input signal buffer
Read the n input signal and send it in IMn input signal message. 119 Flag bits IF1, IF2, IF3 are all 1
Find out if If NO in step 118, the process waits until the process 1 is started from 107. If YES, the same process as 114 is performed. The signal input here is used in the next cycle. 119
Is to synchronize the timing of inputting a signal from a mechanical device. 121 Check whether all of the flag bits OF1, OF2, OF3 are 1. If 122 is NO, the process waits until the process 1 is started from 113. 123 If YES, OBn output signal buffer On
Read the signal and output the On signal to the mechanical device.
The purpose of 121 is to synchronize the timing of outputting a signal to the mechanical device. 124 All synchronization flag bits are set to 0 in preparation for processing in the next cycle. FIG. 9 is a diagram showing the processing content of the control program 71 of the CPU 1 device shown in FIG. In FIG. 9, the processing contents are divided into processing 1 and processing 2. The process 1 is executed in a manner interrupting the process 2. Process 1 is started when the communication interface receives something and sends something. Process 2 is started from process 1. First, the contents of the process 1 will be described. Hereinafter, description will be made in the same manner as in FIG. 125 When process 1 is started, it is checked whether reception is completed or transmission is completed. If NO, processing 1 ends. Check to see if a 126 IMn input signal message has been received. If YES, set the IFn flag bit corresponding to the IMn input signal message to 1. Check if there is a Pn software module in your CPU device to respond to the 128 IMn input signal message. 129 If YES, then I in the IMn input signal message
Store the n signal in the IBn input signal buffer of the Pn software module. 130 Flag bits IF1, IF2, IF3 are all 1
Find out if If YES, the process 2 is started. Process 2 starts the execution of the program. Check if 132 token has been received. 133: If YES, start processing 2. Process 2 transmits an OMn output signal message, which is the execution result of the program. Check whether the 134 OMn message has been received or transmitted. 135 If YES, the OFn synchronization flag bit is set to 1. 136 It is checked whether the Pn program corresponding to the OFn synchronization flag bit is being executed. 137 If YES, the Pn program is interrupted. That is, 143 of process 2 is forcibly ended. 138 Check whether all of the synchronization flag bits OF1, OF2, OF3 are 1. 139 If YES, the process 2 is started. Next, the content of the process 2 will be described. 140 Check whether the synchronization flag bits IF1, IF2, IF3 are all 1; If NO, the process waits until the process is started from 131 of process 1. 142 It is checked whether the OFn flag bit corresponding to the Pn sequence program to be executed is 1 or not. That is, it is checked whether the OMn output signal message, which is the processing result of the Pn sequence program, has already been transmitted from another CPU device. 143 If NO, execute the Pn sequence program. Check to see if a 144 token has been received. If 145 NO, the process waits until it is started from 133 in process 1. 146 It is checked whether the OFn flag bit corresponding to the currently executed Pn sequence program is “1”. That is, it is checked whether the OMn output signal message, which is the processing result of the Pn sequence program, has already been transmitted from another CPU device. If 147 NO, send an OMn output signal message. 148 It is checked whether all the programs in the CPU device have been executed. Process 2 if there are remaining programs
Return to step 142 and execute. 149 When all the programs have been executed, it is checked whether or not all of the synchronization flag bits OF1, OF2, OF3 are 1. If NO, the process waits until 139 of process 1 is activated. 151 If YES, set all synchronization flag bits to 0 to prepare for the next cycle.

[0007]

As described above, in the conventional sequence controller system, since the software depends on the physical structure of the system, it is difficult to multiplex the CPU devices and to level the load between the CPU devices. However, the present invention has made it difficult to change software due to the expansion of the system. However, by making the software independent of the physical structure of the system, the flexibility of the software has been increased, and these difficulties have been solved. Flexible systems with increasing needs can be easily realized. That is, even if the physical position of the I / O device on the communication line is changed, there is no need to change the setting of the CPU device or change the sequence processing program in the CPU device. Even if the sequence processing program is transferred to another CPU device, there is no need to change the setting of the I / O device. Even if a new CPU device or I / O device is added on the communication line,
There is no need to change the settings of the CPU device, change the sequence processing program in the CPU device, or change the settings of the I / O device, which exist conventionally. Instead of multiplexing in units of CPU devices, multiplexing in units of sequence processing programs becomes possible, and a detailed multiplexing system can be realized.
In addition, it is easy to multiplex necessary sequence programs after the system operation starts. If a sequence processing program with a large load (long processing time) is found after the start of operation,
There is no need to change the settings of other programs or hardware even if you transfer to the U device.

[Brief description of the drawings]

FIG. 1 is a diagram showing a physical configuration in an embodiment of a sequence controller system according to the present invention.

FIG. 2 is a diagram showing a logical configuration in an embodiment of a sequence controller system according to the present invention.

FIG. 3 is a configuration diagram of an I / O device according to the present invention.

FIG. 4 is a configuration diagram of a CPU device according to the present invention.

FIG. 5 is a configuration diagram of a synchronization flag for establishing synchronization between a CPU device and an I / O device according to the present invention.

FIG. 6 is a diagram showing a circulation order of transmission rights of a CPU device and an I / O device.

FIG. 7 is a diagram showing the operation of the entire system according to the present invention.

FIG. 8 is a diagram showing processing of a control program for an I / O device according to the present invention.

FIG. 9 is a diagram showing processing of a control program of the CPU device according to the present invention.

FIG. 10 is a diagram showing a configuration example of a conventional sequence controller system.

FIG. 11 is a diagram showing a configuration example of a conventional sequence controller system.

[Explanation of symbols]

 21 CPU1 device 22 CPU2 device 23 CPU3 device 24 Communication line 25 I / O1 device 26 I / O2 device 27 I / O3 device 34 Machine device 38 P1 software module 39 P2 software module 40 P3 software module 41, 43, 45 Input signal message 42, 44, 46 Output signal message 50, 72 Communication interface 51, 71 Control program 52, 70 Microprocessor 53, 69 Synchronization flag 54 Software module

Claims (2)

(57) [Claims] A plurality of sequence programs;
A plurality of CPU devices for performing a logical operation and a plurality of I / Os for performing interface processing of signals of a mechanical device to be controlled
The device is connected via a communication line, message communication is performed by broadcast communication, and each device transmits the message in a token ring system in which tokens are exchanged in a predetermined order between the devices. In this sequence controller system, all CPU devices and I / O devices are directly connected.
A transmission line, a CPU built in each I / O device, and at least one or more input signal messages and output signal messages that are built in at least one of all CPU devices and I / O devices and belong to each of the I / O devices. A software module having a data buffer for storing data included in the input signal message and the output signal message, and an identification code that enables the software module to determine the source of each message; and all the CPUs Device and I / O device,
When one message is transmitted or received, all the bits corresponding to the message are set to 1 and a synchronization flag for an input signal message and a synchronization flag for an output signal message are provided. When the synchronization flag for the input signal message becomes all 0, the input of the signal from the mechanical device is started. When the synchronization flag for the input signal message becomes all 1, the CPU starts the logical operation. A software processing method in a sequence controller system, wherein the output of a signal to the mechanical device is started when all of the output signal message synchronization flags become 1. 2. The same software module is connected to a plurality of C
2. The software processing method in the sequence controller system according to claim 1, wherein the output signal message is transmitted only when the output signal message synchronization flag corresponding to each software module is 0, which is built in the PU.