JP3308060B2 - Semiconductor device mounting method - Google Patents

Semiconductor device mounting method

Info

Publication number
JP3308060B2
JP3308060B2 JP22193493A JP22193493A JP3308060B2 JP 3308060 B2 JP3308060 B2 JP 3308060B2 JP 22193493 A JP22193493 A JP 22193493A JP 22193493 A JP22193493 A JP 22193493A JP 3308060 B2 JP3308060 B2 JP 3308060B2
Authority
JP
Japan
Prior art keywords
solder
solder bump
strain rate
semiconductor device
connection electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP22193493A
Other languages
Japanese (ja)
Other versions
JPH0778848A (en
Inventor
棚橋  昭
善次 坂本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
Denso Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Corp filed Critical Denso Corp
Priority to JP22193493A priority Critical patent/JP3308060B2/en
Publication of JPH0778848A publication Critical patent/JPH0778848A/en
Application granted granted Critical
Publication of JP3308060B2 publication Critical patent/JP3308060B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01019Potassium [K]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases

Landscapes

  • Wire Bonding (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】この発明は、半導体装置のうち、
フェイスダウンで実装されるフリップチップICの実装
方法に関するものである。
BACKGROUND OF THE INVENTION The present invention relates to a semiconductor device,
The present invention relates to a method for mounting a flip-chip IC mounted face-down.

【0002】[0002]

【従来の技術】従来、フリップチップICのフェイスダ
ウン実装方法として、半導体チップの接続電極表面に形
成されたはんだバンプを配線基板の接続電極にその融点
未満の温度条件下で直接に圧接し、はんだバンプを塑性
変形して配線基板の接続電極と接合する方法が知られて
いる。
2. Description of the Related Art Conventionally, as a face-down mounting method of a flip-chip IC, a solder bump formed on the surface of a connection electrode of a semiconductor chip is directly pressed into contact with a connection electrode of a wiring board under a temperature condition lower than its melting point. There is known a method in which a bump is plastically deformed and joined to a connection electrode of a wiring board.

【0003】[0003]

【発明が解決しようとする課題】しかしながら上記実装
方法では、はんだバンプの接合強度が溶融はんだ(はん
だリフロー)方式に比べて劣るので、接合後、はんだバ
ンプの再溶融工程を必要となる問題があった。本発明は
上記問題に鑑みなされたものであり、バンプの再溶融工
程を必要とせず、従来より格段に生産性を向上可能なバ
ンプ接合式の半導体チップの実装方法を提供すること
を、その目的としている。
However, in the above mounting method, the bonding strength of the solder bump is inferior to that of the molten solder (solder reflow) method. Was. The present invention has been made in view of the above problems, and an object of the present invention is to provide a bump bonding type semiconductor chip mounting method which does not require a step of re-melting bumps and can significantly improve productivity compared to the related art. And

【0004】[0004]

【課題を解決するための手段】本発明の半導体チップの
実装方法は、半導体チップの接続電極表面に形成された
はんだバンプを配線基板の接続電極にその融点未満の温
度条件下で圧接し、前記はんだバンプを塑性変形して前
記配線基板の接続電極と合金接合する半導体装置の実装
方法において、前記はんだバンプの変形速度を10μm
/sec以下とすることを特徴とする。
According to a method of mounting a semiconductor chip of the present invention, a solder bump formed on a surface of a connection electrode of a semiconductor chip is pressed against a connection electrode of a wiring board under a temperature condition lower than its melting point. In a semiconductor device mounting method in which a solder bump is plastically deformed and alloy-bonded to a connection electrode of the wiring board, the solder bump has a deformation speed of 10 μm.
/ Sec or less.

【0005】好適な態様において、前記はんだバンプの
変形速度は1〜3μm/sec以下とされる。好適な態
様において、はんだバンプのSnとPbとの比率は30
〜70重量部対70〜30重量部とされる。好適な態様
において、はんだバンプはSnを61〜65wt%含む
共晶性はんだとされる。
[0005] In a preferred embodiment, the deformation speed of the solder bump is 1 to 3 µm / sec or less. In a preferred embodiment, the ratio of Sn to Pb of the solder bump is 30
To 70 to 30 parts by weight. In a preferred embodiment, the solder bump is a eutectic solder containing 61 to 65 wt% of Sn.

【0006】好適な態様において、歪み速度をεt 、変
形抵抗をσ、比例定数をk、歪み速度依存指数をm、σ
=k×εt m とし、その歪み速度依存指数mが0.3以
上の範囲で前記圧接を実施する。
In a preferred embodiment, the strain rate is ε t , the deformation resistance is σ, the proportionality constant is k, the strain rate dependence index is m, σ
= K × ε t m, and the above-described pressure welding is performed in a range where the strain rate dependence index m is 0.3 or more.

【0007】[0007]

【作用及び発明の効果】第一発明の半導体チップの実装
方法は、はんだバンプの変形速度を10μm/sec以
下とすることを特徴としている。このようにすれば、は
んだ溶融工程を追加することなしに良好な接合強度が得
られることがわかった。
The method of mounting a semiconductor chip according to the first invention is characterized in that the deformation speed of the solder bump is set to 10 μm / sec or less. In this way, it has been found that good joining strength can be obtained without adding a solder melting step.

【0008】好適な態様において、前記はんだバンプの
変形速度は1〜3μm/sec以下とされる。このよう
にすれば、はんだ溶融工程を追加することなしにそれと
ほとんど遜色が無い接合強度が得られることがわかっ
た。好適な態様において、はんだバンプのSnとPbと
の比率は30〜70重量部対70〜30重量部とされ
る。
[0008] In a preferred embodiment, the deformation speed of the solder bump is 1 to 3 µm / sec or less. In this way, it has been found that a joining strength almost equal to that can be obtained without adding a solder melting step. In a preferred embodiment, the ratio of Sn to Pb of the solder bump is 30 to 70 parts by weight to 70 to 30 parts by weight.

【0009】実験によれば、この組成範囲のはんだは、
後述する歪み速度依存指数mが0.3以上となるので、
共晶はんだと同様に良好な接合強度が得られることがわ
かった。好適な態様において、はんだバンプはSnを6
1〜65wt%含む共晶性はんだとされる。
According to experiments, solder in this composition range is:
Since the strain rate dependence index m described later is 0.3 or more,
It was found that good joint strength was obtained as with the eutectic solder. In a preferred embodiment, the solder bump has an Sn of 6
The eutectic solder contains 1 to 65 wt%.

【0010】実験によれば、この組成範囲のはんだは、
後述する歪み速度依存指数mが0.3以上となるので、
共晶はんだと同様に良好な接合強度が得られることがわ
かった。好適な態様において、歪み速度をεt 、変形抵
抗をσ、比例定数をk、歪み速度依存指数をm、σ=k
×εt m とする場合に、その歪み速度依存指数mが0.
3以上の範囲で前記圧接を実施する。
According to experiments, the solder in this composition range is:
Since the strain rate dependence index m described later is 0.3 or more,
It was found that good joint strength was obtained as with the eutectic solder. In a preferred embodiment, the strain rate is ε t , the deformation resistance is σ, the proportionality constant is k, the strain rate dependence index is m, and σ = k
× ε t m , the strain rate dependent index m is equal to 0.
The pressure welding is performed in three or more ranges.

【0011】この意味を説明すると、はんだバンプの接
合強度を溶融(合金)レベルに接近させるには、接合面
の一部ではなく全面において良好な接合を実現する必要
がある。歪み速度εt と変形抵抗σとの間には、σ=k
×εt m の関係が成立し、はんだのような超塑性材料で
はmが通常の金属より大きい。mが大きいということ
は、次のことを意味している。すなわち、局部的に大き
な外力により歪み速度εtが大きくなっている部位の変
形抵抗σは大きいのでこの部位は変形しにくく、一方、
局部的に小さい外力により歪み速度εt が小さくなって
いる部位の変形抵抗σは小さいのでこの部位は変形し易
い。つまり、小外力印加部位は変形し易く、大外力印加
部位は変形しにくい。
In order to explain the meaning, in order to bring the bonding strength of the solder bump closer to the melting (alloy) level, it is necessary to realize good bonding not on a part of the bonding surface but on the entire surface. Σ = k between the strain rate ε t and the deformation resistance σ
A relationship of × ε t m holds, and m is larger than a normal metal in a superplastic material such as solder. The fact that m is large means the following. That is, since the deformation resistance σ of the portion where the strain rate ε t is large due to the locally large external force is large, this portion is hardly deformed.
Since the deformation resistance σ of a portion where the strain rate ε t is small due to a locally small external force is small, this portion is easily deformed. That is, the small external force application part is easily deformed, and the large external force application part is hardly deformed.

【0012】もし、これが上記とは異なって、小外力印
加部位も大外力印加部位も同じ変形し易さとすれば、局
部的に大きな外力が印加されている部位の歪み速度εt
は大きいのでこの部分の変形量は大きく、局部的に小さ
い外力が印加されている部位の歪み速度εt は小さいの
でこの部分の変形量は小さく、結果的に、大外力印加部
位が集中的に変形し、小外力印加部位の変形量が不足
し、はんだバンプで言えばその部位の接合強度が不足す
ることになる。特にはんだバンプは半球形状をを有して
おり、外力が均一に印加されない形状であるので、mが
小さいと接合全面にわたって良好に変形することが難し
い。
If this is different from the above, if the small external force application site and the large external force application site are easily deformed in the same manner, the strain rate ε t of the site where the locally large external force is applied is obtained.
Is large, the deformation amount of this part is large, and the strain rate ε t of the part where a small external force is locally applied is small, so the deformation amount of this part is small, and as a result, the part where the large external force is applied is concentrated It deforms, and the amount of deformation at the small external force application site becomes insufficient, and the bonding strength at that site in the case of solder bumps becomes insufficient. In particular, since the solder bump has a hemispherical shape and a shape to which an external force is not uniformly applied, it is difficult to satisfactorily deform the entire bonding surface if m is small.

【0013】実験結果によれば、はんだバンプでは、歪
み速度依存指数mが0.3以上あれば、溶融はんだ並み
の接合強度が得られることがわかった。
According to the experimental results, it has been found that, when the strain rate dependence index m is 0.3 or more, the bonding strength of the solder bump is comparable to that of the molten solder.

【0014】[0014]

【実施例】以下、この発明を具体化した一実施例を図面
に従って説明する。本実施例装置は、ガラス基板(液晶
表示装置)上に半導体チップを搭載するCOG(Chi
p On Glass)製品であり、図1にガラス基板
1上にICチップ2が直接ボンディングされた状態を示
し、図2にボンディングの、図3にボンディング
ICチップ2の要部を示す。
DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. The device of this embodiment is a COG (Chi) in which a semiconductor chip is mounted on a glass substrate (liquid crystal display device).
FIG. 1 shows a state in which an IC chip 2 is directly bonded to a glass substrate 1, FIG. 2 shows a main part of the IC chip 2 after bonding, and FIG. 3 shows a main part of the IC chip 2 before bonding.

【0015】ICチップ2の表面にはチップ側接続電極
としてアルミ電極3が形成され、その表面はパッシベー
ション層4にて覆われている。又、アルミ電極3の一部
が露出され、この露出部分において、アルミ電極3上に
はクロムやチタンよりなるバリアメタル5が形成されて
いる。そのバリアメタル5上には銅バンプ6が配置さ
れ、銅バンプ6の表面にはハンダ7が配置されている。
このハンダ7としては、Pbー63Sn(共晶ハンダ)
が用いられており、このハンダの融点は183℃であ
る。製造工程としては、バリアメタル5を蒸着後、銅及
びハンダの連続メッキを行い、さらに、不活性雰囲気中
250℃にてリフローすることにより電極先端部を半球
状とすればよい。
An aluminum electrode 3 is formed on the surface of the IC chip 2 as a chip-side connection electrode, and the surface is covered with a passivation layer 4. Further, a part of the aluminum electrode 3 is exposed, and a barrier metal 5 made of chromium or titanium is formed on the aluminum electrode 3 in this exposed portion. Copper bumps 6 are arranged on the barrier metal 5, and solder 7 is arranged on the surface of the copper bumps 6.
As the solder 7, Pb-63Sn (eutectic solder)
Is used, and the melting point of this solder is 183 ° C. In the manufacturing process, after the barrier metal 5 is deposited, continuous plating of copper and solder is performed, and the electrode tip is made hemispherical by reflowing at 250 ° C. in an inert atmosphere .

【0016】ボンディング前のガラス基板(配線基板)
1を図4(平面図)に示す。ガラス基板1には、チップ
側接続端子としての導電パタ−ン10が形成されてい
る。導電パタ−ン10は三層構造をなし、ソーダガラス
上にITO(インジウム・スズ・オキサイド)層11と
ニッケル層12と金層13とが順に積層されている。こ
の積層構造は、ITO/Ni/Auを蒸着,メッキ似て
形成される。ここで、表面の金層13は、配線母材とし
てのITO層11とニッケル層12の酸化防止材となっ
ている。
Glass substrate (wiring substrate) before bonding
1 is shown in FIG. 4 (plan view). A conductive pattern 10 is formed on the glass substrate 1 as a chip-side connection terminal. The conductive pattern 10 has a three-layer structure in which an ITO (indium tin oxide) layer 11, a nickel layer 12, and a gold layer 13 are sequentially laminated on soda glass. This laminated structure is formed by depositing and plating ITO / Ni / Au. Here, the gold layer 13 on the surface is an antioxidant for the ITO layer 11 and the nickel layer 12 as the wiring base material.

【0017】そして、ボンディングの際には、ガラス基
板1を所定位置に置き、吸着ヘッドによりICチップ2
をガラス基板1の上方に搬送し、位置合わせを行う。そ
して、ICチップ2をガラス基板1上に載置する。その
後、ダングステン(W)製の加熱ヘッドにてICチップ
2の裏面(図1、2の上面)から1つのバンプ当たり必
要な荷重をかけるとともに、加熱ヘッドの温度を120
〜175℃にして10〜30秒間保持する。つまり、ハ
ンダ7の融点の183℃よりも低い温度で、ICチップ
2とガラス基板1との間を加圧してハンダ7を塑性変形
させながら接合する。
At the time of bonding, the glass substrate 1 is placed at a predetermined position, and the IC chip 2 is
Is transported above the glass substrate 1 and alignment is performed. Then, the IC chip 2 is placed on the glass substrate 1. Then, a necessary load per bump is applied from the back surface (the upper surface in FIGS. 1 and 2) of the IC chip 2 by a dangsten (W) heating head, and the temperature of the heating head is set to 120.
Keep at 17175 ° C. and hold for 10-30 seconds. That is, at a temperature lower than the melting point of 183 ° C. of the solder 7, the IC chip 2 and the glass substrate 1 are pressurized and joined while plastically deforming the solder 7.

【0018】このとき、加熱温度がハンダ7の融点以下
なのでハンダ7は溶融していないが柔らかくなってお
り、接合部は変形し面接触となっている。又、この加圧
してハンダ7を塑性変形させながら接合させる時にハン
ダ7の表面が先送りされ、新鮮なハンダが露出されて接
合界面が作られる。そして、導電パタ−ン10でのAu
(金)は接合部近傍のハンダ7中にほぼ拡散しており、
ニッケルも界面のSn粒子に少量拡散していることがE
DX分析法による断面分析で確認した。
At this time, since the heating temperature is equal to or lower than the melting point of the solder 7, the solder 7 is not melted but is soft, and the joint is deformed and comes into surface contact. In addition, when the solder 7 is joined while being plastically deformed by applying the pressure, the surface of the solder 7 is advanced, and fresh solder is exposed to form a joining interface. Then, Au in the conductive pattern 10 is used.
(Gold) is almost diffused into the solder 7 near the joint,
It is found that nickel also diffuses a little into the Sn particles at the interface.
It was confirmed by cross-sectional analysis by the DX analysis method.

【0019】さらに、端子数や端子サイズに応じて加熱
ヘッドによる加圧力を調整することにより接続面積、ハ
ンダバンプ形状を容易に調整することができる。尚、局
部加熱は、加熱ヘッドによらずに、レーザをバンプ部分
に照射することにより行ってもよい。ここで、前述の接
合条件について詳細に説明する。
Further, by adjusting the pressing force by the heating head according to the number of terminals and the size of the terminals, the connection area and the shape of the solder bumps can be easily adjusted. It should be noted that the local heating may be performed by irradiating a laser to the bump portion without using the heating head. Here, the above-mentioned joining conditions will be described in detail.

【0020】加熱時間(10〜30秒)は、加熱ヘッド
から基板側へ熱伝導が行われるに十分な時間であり、か
つ、生産性を確保するための上限の時間である。図5に
上記はんだバンプ7の変形速度(μm/sec)を種々
変化させた場合の接合強度の変化を示す。ただし、はん
だバンプ7の直径は約250μm、その厚さ(変形後)
は最大で約40μm、銅バンプ6の厚さは最大で約30
μmとした。
The heating time (10 to 30 seconds) is a time sufficient for conducting heat from the heating head to the substrate side and an upper limit time for securing productivity. FIG. 5 shows a change in the bonding strength when the deformation speed (μm / sec) of the solder bump 7 is variously changed. However, the diameter of the solder bump 7 is about 250 μm and its thickness (after deformation)
Is a maximum of about 40 μm, and the thickness of the copper bump 6 is a maximum of about 30 μm.
μm.

【0021】接合装置としては、ミスズFA株式会社製
のフリップチップマウンタ(機種名フリップチップマウ
ンタ(特注品))を用い、同時に44個のはんだバンプ
7を接合した。はんだバンプ7の変形速度はフリップチ
ップマウンタの下降速度に等しいと考えることができる
ので、変形速度の制御はフリップチップマウンタの下降
速度を制御して実施し、各変形速度毎に40回、試験し
た。図5からわかるように、平均変形速度が10μm
(歪み速度εt 換算10-1(1/sec))でのバンプ
電極7一個当たりの接合強度は80g重が得られ、3μ
m(歪み速度εt 換算3×10-1(1/sec))での
バンプ電極7一個当たりの接合強度は85g重得られ、
1μm(歪み速度εt 換算×10-2(1/sec))で
のバンプ電極7一個当たりの接合強度は88g重得られ
た。
As a bonding apparatus, a flip chip mounter (model name: flip chip mounter (special order product)) manufactured by Miss FA Corporation was used, and 44 solder bumps 7 were simultaneously bonded. The deformation speed of the solder bump 7 is flip-chip.
Can be considered equal to the descent speed of the top mounter
Therefore, the deformation speed was controlled by controlling the descending speed of the flip chip mounter, and the test was performed 40 times at each deformation speed. As can be seen from FIG. 5, the average deformation speed is 10 μm
At a strain rate of 10 -1 (1 / sec) in terms of strain rate εt, the bonding strength per bump electrode 7 is 80 g weight and 3 μm.
The bonding strength per one bump electrode 7 at 85 m (3 × 10 -1 (1 / sec) in terms of strain rate εt) is 85 g.
At 1 μm (strain rate εt conversion × 10 −2 (1 / sec)), a bonding strength of 7 g per 7 bump electrodes was obtained.

【0022】次に、はんだバンプ7のSnとPbとの組
成を30〜70重量部対70〜30重量部の範囲で変更
して同じ試験を実施した。その結果、図5とほぼ同じ特
性が得られた。すなわち、平均変形速度を10μm以下
とした場合に従来の変形速度(30〜50μm/s)に
比較して格段に良好な接合強度が得られ、平均変形速度
を1〜3μmとした場合に、溶融はんだにほとんど匹敵
する接合強度が達成できた。特にその内、はんだバンプ
をSnを61〜65wt%含む共晶性はんだとすると、
後述する歪み速度依存指数mが大きくなるので、良好な
接合強度が得られた。
Next, the same test was carried out by changing the composition of Sn and Pb of the solder bump 7 in the range of 30 to 70 parts by weight to 70 to 30 parts by weight. As a result, almost the same characteristics as those in FIG. 5 were obtained. That is, when the average deformation speed is 10 μm or less, a significantly better bonding strength can be obtained as compared with the conventional deformation speed (30 to 50 μm / s). Bonding strength almost comparable to solder was achieved. In particular, if the solder bump is made of eutectic solder containing 61 to 65 wt% of Sn,
Since the strain rate dependent index m described later becomes large, good joining strength was obtained.

【0023】次に、上記した共晶はんだの歪み速度εt
と変形抵抗σとの関係を調べた。図6にその結果を示
す。試験には、島津株式会社製の引っ張り試験機(機種
名サーボパルサー(特注品))を用い、板状試験品の断
面積は20mm2 とした。歪み速度εt は、実験式σ=
kεt m で決まり、εt を変化させた時のσを測定し
た。
Next, the strain rate ε t of the above eutectic solder
And the relationship between the deformation resistance σ. FIG. 6 shows the result. For the test, a tensile tester (model name: servo pulser (special order product)) manufactured by Shimadzu Corporation was used, and the cross-sectional area of the plate-shaped test product was 20 mm 2 . The strain rate ε t is determined by the empirical formula σ =
It was determined by kε t m , and σ when ε t was changed was measured.

【0024】図6からわかるように、歪み速度εt が1
×10-1(1/sec)までは歪み速度依存指数mは
0.3以上であり、歪み速度εt の増大に連れて変形抵
抗σが増大する領域であり、上述したよう原理により印
加外力が各部で異なっても均一な変形を可能である。そ
して超塑性をしめすはんだでも歪み速度εt が3(1/
sec)以上、特に6(1/sec)以上になると、歪
み速度εt の増加にもかかわらず変形抵抗σは増加せ
ず、この部位だけが局部的に変形してしまい、全面的な
塑性変形により接合強度が低下してしまうことが推定で
きる。
As can be seen from FIG. 6, the strain rate ε t is 1
Up to × 10 −1 (1 / sec), the strain rate dependent index m is 0.3 or more, and this is a region where the deformation resistance σ increases as the strain rate ε t increases. Can be uniformly deformed even if it differs in each part. And even if the solder shows superplasticity, the strain rate ε t is 3 (1/1 /
sec) or more, especially 6 (1 / sec) or more, the deformation resistance σ does not increase in spite of the increase in the strain rate ε t , and only this part is locally deformed, and the entire area is plastically deformed. It can be presumed that the bonding strength is reduced due to this.

【0025】なお上記実施例では導電パタ−ン10(配
線材)をAu/Ni/ITOとしたが、Au,Ni,S
n,Ag,AgーPd,AgーPt,Cuなどハンダが
付くものであればよく、又、ハンダとしてPbー63S
n以外の組成のハンダを使用してもよく、要は、少なく
ともスズを含む低融点金属であればよい。さらに、前記
実施例では銅バンプ6(突起電極)上にハンダ7を設け
たが、特に突起電極を設ける必要はなく、ハンダボール
をチップ2と基板1との間に供給する方法でもよい。金
層13は省略可能である。ニッケル層12の代わりには
んだバンプ7と合金可能な金属を採用することも可能で
ある。
Although the conductive pattern 10 (wiring material) is Au / Ni / ITO in the above embodiment, Au, Ni, S
n, Ag, Ag-Pd, Ag-Pt, Cu, etc. may be used as long as they are soldered, and Pb-63S
A solder having a composition other than n may be used. In short, any low melting metal containing at least tin may be used. Further, although the solder 7 is provided on the copper bumps 6 (protruding electrodes) in the above embodiment, it is not necessary to particularly provide the protruding electrodes, and a method of supplying solder balls between the chip 2 and the substrate 1 may be used. The gold layer 13 can be omitted. Instead of the nickel layer 12, a metal that can be alloyed with the solder bump 7 can be employed.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本実施例のボンディング部分(端子部分)の拡
大図である。
FIG. 1 is an enlarged view of a bonding portion (terminal portion) of the present embodiment.

【図2】ボンディング後の状態を示す図である。FIG. 2 is a diagram showing a state after bonding.

【図3】ボンディング前のICチップの端子部分を示す
図である。
FIG. 3 is a diagram showing a terminal portion of an IC chip before bonding.

【図4】ボンディング前のガラス基板の端子部分を示す
図である。
FIG. 4 is a diagram showing a terminal portion of a glass substrate before bonding.

【図5】変形速度と接合強度との関係の測定結果を示す
図である。
FIG. 5 is a diagram showing a measurement result of a relationship between a deformation speed and a bonding strength.

【図6】歪み速度と変形抵抗との関係の測定結果を示す
図である。
FIG. 6 is a diagram showing a measurement result of a relationship between a strain rate and a deformation resistance.

【符号の説明】[Explanation of symbols]

1 ガラス基板(配線基板) 2 半導体チップ 3 アルミ電極(半導体チップの接続電極) 7 はんだバンプ 10 導電パタ−ン(配線基板の接続電極) DESCRIPTION OF SYMBOLS 1 Glass substrate (wiring board) 2 Semiconductor chip 3 Aluminum electrode (semiconductor chip connection electrode) 7 Solder bump 10 Conductive pattern (wiring board connection electrode)

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平5−136216(JP,A) 特開 昭63−152136(JP,A) 特開 昭61−80828(JP,A) 特開 昭60−53039(JP,A) (58)調査した分野(Int.Cl.7,DB名) H01L 21/60 311 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-5-136216 (JP, A) JP-A-63-152136 (JP, A) JP-A-61-80828 (JP, A) JP-A-60-1985 53039 (JP, A) (58) Field surveyed (Int. Cl. 7 , DB name) H01L 21/60 311

Claims (5)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】半導体チップの接続電極表面に形成された
はんだバンプを配線基板の接続電極にその融点未満の温
度条件下で圧接し、前記はんだバンプを塑性変形して前
記配線基板の接続電極と合金接合する半導体装置の実装
方法において、 前記はんだバンプの変形速度を10μm/sec以下と
することを特徴とする半導体装置の実装方法。
1. A solder bump formed on a surface of a connection electrode of a semiconductor chip is pressed against a connection electrode of a wiring board under a temperature condition lower than its melting point, and the solder bump is plastically deformed to be in contact with the connection electrode of the wiring board. A method for mounting a semiconductor device to be alloy-joined, wherein a deformation speed of the solder bump is set to 10 μm / sec or less.
【請求項2】前記はんだバンプの変形速度を1〜3μm
/sec以下とすることを特徴とする請求項1記載の
導体装置の実装方法。
2. The deformation speed of the solder bump is 1 to 3 μm.
Implementation of semi <br/> conductor device according to claim 1, characterized in that the / sec or less.
【請求項3】前記はんだバンプのSnとPbとの比率は
30〜70重量部対70〜30重量部とされる請求項1
記載の半導体装置の実装方法。
3. The solder bump according to claim 1, wherein the ratio of Sn to Pb is 30 to 70 parts by weight to 70 to 30 parts by weight.
A mounting method of the semiconductor device described in the above.
【請求項4】前記はんだバンプはSnを61〜65wt
%含む共晶性はんだとされることを特徴とする請求項1
記載の半導体装置の実装方法
4. The solder bump has a Sn content of 61 to 65 wt.
% Claim 1, characterized in that are KyoAkirasei solder containing
A mounting method of the semiconductor device described in the above .
【請求項5】み速度をεt 、変形抵抗をσ、比例定数
をk、歪み速度依存指数をm、σ=k×εt m とし、その
歪み速度依存指数mが0.3以上となる範囲で前記圧接
を実施する請求項1記載の半導体装置の実装方法。
5. A strain observed rate epsilon t, the deformation resistance sigma, the proportionality constant k, and the strain rate dependence exponent m, and σ = k × ε t m, and the strain rate dependence exponent m is 0.3 or more 2. The method for mounting a semiconductor device according to claim 1, wherein the pressing is performed within a certain range.
JP22193493A 1993-09-07 1993-09-07 Semiconductor device mounting method Expired - Fee Related JP3308060B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22193493A JP3308060B2 (en) 1993-09-07 1993-09-07 Semiconductor device mounting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22193493A JP3308060B2 (en) 1993-09-07 1993-09-07 Semiconductor device mounting method

Publications (2)

Publication Number Publication Date
JPH0778848A JPH0778848A (en) 1995-03-20
JP3308060B2 true JP3308060B2 (en) 2002-07-29

Family

ID=16774454

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22193493A Expired - Fee Related JP3308060B2 (en) 1993-09-07 1993-09-07 Semiconductor device mounting method

Country Status (1)

Country Link
JP (1) JP3308060B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0821407A3 (en) * 1996-02-23 1998-03-04 Matsushita Electric Industrial Co., Ltd. Semiconductor devices having protruding contacts and method for making the same

Also Published As

Publication number Publication date
JPH0778848A (en) 1995-03-20

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