JP3244398B2 - PAL color signal demodulation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a color signal demodulation circuit for a PAL television (television) receiver.
In particular, the present invention relates to a PAL color signal demodulation circuit capable of accurately performing a function of adding color signals around 1H (horizontal synchronization signal period) to reduce phase distortion.

[0002]

2. Description of the Related Art In the PAL system, R-out of two color signals is used.
The Y signal is inverted every 1H and sent, and the RY signal is sent at a constant phase. Then, by adding the color signals of about 1H in the TV receiver, the phase distortion generated in the transmission system is reduced, and the hue fluctuation is prevented.

Conventionally, in the color signal demodulation circuit of the PAL system, the addition function has been performed on the RY signal and the BY signal before color demodulation. In that case, a glass delay line was used as a delay component. However, recently, CCDs (Charge Transfer Devices) have begun to be used as delay components. When a CCD is used, the color signal after color demodulation is delayed by 1H.

FIG. 2 shows a part of a TV receiver having such a PAL color signal demodulation circuit. A carrier color signal from an input terminal (1) is input to a BY demodulator (2). And RY demodulator (3). BY demodulator (2)
And the RY demodulator (3), to which different carrier waves are applied, are demodulated respectively. The demodulated outputs of the BY demodulator (2) and the RY demodulator (3) are led out of the IC (6) after unnecessary components are removed by the LPFs (4) and (5), and are output to the CCD IC ( 7) is applied. CCDIC
(7) delays the demodulated color difference signal for 1H period, and is delayed by the first and second CCD circuits (8) and (9).

First and second CCD circuits (8) and (9)
Is returned to the inside of the IC (6) again and is clamped by the first and second clamp circuits (10) and (11). First and second clamp circuits (10) and (11)
Are passed through LPFs (12) and (13) for removing unnecessary components caused by clocks of the first and second CCD circuits (8) and (9), and are output from the first and second adders ( 14) and (15).

On the other hand, the color difference signals from the LPFs (4) and (5) are directly applied to the first and second adders (14) and (15), whereby 1H of each color difference signal is applied.
The signals before and after are added. By this addition operation, phase distortion occurring in the transmission system is reduced, and hue fluctuation is prevented. Next, the operation will be described with reference to FIG. Now, it is assumed that a carrier color signal indicated by a solid line in FIG. As shown, the RY signal arrives while inverting the phase every 1H.

On the other hand, the BY demodulator (2) shown in FIG.
Is applied with a carrier having a constant phase shown in FIG.
To the -Y demodulator (3), a carrier inverted every 1H shown in FIG. 3C is applied. The carrier wave of FIG.
The BY signal component of (a) is demodulated and the B signal shown in FIG.
The -Y signal is derived from the BY demodulator (2) in FIG.
3 (c) demodulates the RY signal component of FIG. 3 (a), and the RY signal shown in FIG. 3 (e) is output from the RY demodulator (3) of FIG. Derived. The same is performed at the 2H-th and the 3H-th in FIG. 3, and the demodulated outputs shown in FIGS. 3 (d) and 3 (e) are obtained.

Next, 1 shown in FIGS. 3D and 3E, respectively.
By adding the signals before and after H, a demodulated output can be obtained. That is, if the 1H and 2H signals in FIG.
Since both are in the 0-degree direction, a BY signal in the 0-degree direction shown in FIG. 3F is obtained. Similarly, if the 1H-th and 2H-th signals in FIG. 3E are added, since both signals are in the 90-degree direction, a BY signal in the 90-degree direction shown in FIG. 3G is obtained.

Next, the reduction of the phase distortion will be described.
Now, it is assumed that the phases of both the BY signal and the RY signal in FIG. 3A fluctuate in the counterclockwise direction, and each of them becomes a vector indicated by a dotted line. The carrier of FIG. 3B demodulates the BY ′ signal component of FIG. 3A, and the BY ′ signal shown in FIG. 3D is output from the BY demodulator (2) of FIG. Derived. at the same time,
The carrier wave of FIG. 3B demodulates the BY axis component of the RY ′ signal component of FIG. 3A and demodulates the RY ′ signal (distortion component) shown in FIG. 3D. Would. Similarly, FIG.
When the 2H carrier color signal of FIG. 3A is demodulated with the 2H carrier wave, the 2H signal of FIG. 3D is demodulated.

Here, when the signals of the 1H and 2H in FIG. 3D are vector-added, the signals of FIG. 3F are obtained. In FIG. 3 (f), the RY ′ signal (distortion component) of the first H and 2
The H-th RY ′ signal (distortion component) is canceled, and only the required BY ′ signal on the BY axis component can be detected. FIG.
The carrier wave of (c) demodulates the RY ′ signal component of FIG. 3A, and the RY ′ signal shown in FIG. 3E is derived from the RY demodulator (3) of FIG. You. At the same time, the carrier wave of FIG. 3C demodulates the RY axis component of the BY ′ signal component of FIG. 3A and demodulates the BY ′ signal shown in FIG. . Similarly, the signal shown in FIG. Vector addition of the 1H-th and 2H-th signals in FIG. 3 (e) results in the signal in FIG. 3 (g), and in this case also, the BY ′ signal, which is an unnecessary distortion component, is canceled.

Therefore, by the addition operation of the first and second adders (14) and (15), phase distortion occurring in the transmission system can be reduced, and hue fluctuation can be prevented. The demodulated RY signal and BY signal from the first and second adders (14) and (15) are matrixed by a matrix circuit (16), and the RY signal, BY signal and The GY signal is derived from the output terminals (17) to (19).

Therefore, according to the circuit of FIG. 2, it is possible to demodulate the PAL color signal.

[0013]

However, in the circuit of FIG. 2, a level fluctuation occurs between the input and output of the first and second CCD circuits (8) and (9), and the first and second adders (14) and There is a problem that the distortion component cannot be accurately canceled at the time of vector synthesis in (15).

That is, R- in the 0-degree direction in FIG.
There is a problem that the magnitude of the Y ′ signal vector and the magnitude of the RY ′ signal vector in the 180-degree direction are not equal, and a canceling distortion component remains.

[0015]

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has a first demodulator for demodulating a first color difference signal and a second demodulator for demodulating a second color difference signal. Adding means for applying an ALC additional pulse to a predetermined position of the output signal of the first demodulator, a first CCD for delaying the output signal of the first demodulator to which the ALC additional pulse has been added for 1H period,
A second CC for delaying the output signal of the second demodulator for 1H period
D, and the magnitude of the output signal of the first CCD
A first ALC for level detection based on the level of the additional pulse, and adjusting the magnitude of the output signal of the first CCD to the output signal level of the first demodulator according to the level detection output
Circuit for adjusting the magnitude of the output signal of the second CCD according to the level detection output of the first ALC circuit.
An LC circuit, an output signal of the first demodulator and the first AL
A first adder for adding the output signal of the C circuit;
A second adder that adds the output signal of the demodulator and the output signal of the second ALC circuit.

[0016]

According to the present invention, an ALC additional pulse is applied to a predetermined position of a demodulated color signal before being applied to a CCD. Then, the level of the ALC additional pulse in the color signal derived from the CCD is detected, and the magnitude of the color signal derived from the CCD is returned to the magnitude before input to the CCD according to the detected output. Therefore, the levels of the color signals before and after the delay become equal, and if both signals are added,
Accurate distortion correction can be performed.

[0017]

FIG. 1 shows a PAL color signal demodulation circuit according to the present invention. (20) is an input terminal to which a color video signal is applied, and (21) is a sync separation for separating a horizontal sync signal. The circuit (22) has a frequency 3 synchronized with the horizontal synchronizing signal.
A horizontal AFC (automatic frequency control) circuit for generating a frequency-divided output of 2fH (fH is a horizontal synchronizing signal frequency) and a horizontal synchronizing signal, and (23) frequency-divides the 32fH signal as a clock signal, and Reset and BGP
(Burst gate pulse) and a frequency dividing circuit for generating an ALC additional pulse, (24) a chroma signal extracting circuit, (2)
5) is a burst extraction circuit for extracting a burst signal, and (2)
6) is a carrier generation circuit for generating a carrier according to the burst signal, and (27) is a switch (28) switched to the a side in response to the ALC additional pulse to determine the output signal of the BY demodulator (2). Position the reference power supply (36) at 0.
An additional circuit for applying an ALC additional pulse of 2 V, (29) is a circuit for converting the level of the BY signal from the LPF (13) and the reference voltage Vref of the reference power supply (30) to B
A clamp detection circuit for generating a detection output for comparing the levels during the GP period and setting the level of the BGP period of the BY signal during the BGP period to the reference voltage Vref; (32) a switch in accordance with the ALC additional pulse from the terminal (33) (34) is closed and a detection circuit for taking out the 0.2 V ALC additional pulse applied by the additional circuit (27), and (35) is a reference power supply (3
0) and 0.2 V of the reference power supply (36) of the additional circuit (27), and a detection circuit (3
The comparator compares the level of the detected output with the level of 2) and generates a comparison output such that the ALC additional pulse detected by the detection circuit (32) returns to the original level of 0.2 V. The capacitors (38) and (39) are first and second ALC circuits for changing the levels of the BY signal and the RY signal in accordance with the voltage held by the capacitor (37).

In the circuit blocks shown in FIG. 1, the same circuit blocks as those in FIG. 2 are denoted by the same reference numerals, and description thereof will be omitted. In the PAL color video signal from the input terminal (20), the chroma signal is converted into a chroma signal extraction circuit (2).
It is extracted in 4) and applied to the BY demodulator (2) and the RY demodulator (3).

The PAL color video signal from the input terminal (20) is obtained by extracting a burst signal by a burst extraction circuit (25) and applying the burst signal to a carrier generation circuit (26). The BY demodulator (2) and the RY demodulator (3)
Carriers synchronized in each phase are applied from the carrier generation circuit (26) and are demodulated respectively. The PAL color video signal from the input terminal (20) is
A horizontal synchronizing signal is extracted by a sync separation circuit (21) and applied to a horizontal AFC circuit (22). Horizontal AFC circuit (2
2) is a PLL that locks the phase with the horizontal synchronizing signal, and applies a phase-locked signal of 32 fH to the clock signal and the horizontal synchronizing signal to the frequency dividing circuit (23). Dividing circuit (23)
Generates a frequency dividing function and a logical output of the frequency-divided signal. Since the signal is reset in accordance with the horizontal synchronizing signal and divides the frequency of the 32 fH signal, various signals with desired timing can be generated. BGP for terminal (40) and A for terminal (41)
An LC additional pulse is generated. The BGP of the terminal (40) is applied to the terminal (31), and the ALC additional pulse of the terminal (41) is applied to the terminal (33).

The switch (28) of the additional circuit (27) is switched in response to the ALC additional pulse from the terminal (41), and the 0.2 V ALC additional pulse of the reference power supply (36) is a part of the BY signal. Will be derived as This will be described with reference to FIGS. FIG. 4 (a)
4 shows a BY signal from a BY demodulator (2). A signal having the phase shown in FIG. 4D is generated from this signal as an ALC additional pulse, and is added to the signal shown in FIG.
Make a signal. The hatched portion of the signal in FIG.
This signal is an additional pulse.
Always constant. Therefore, this ALC additional pulse is converted to CC
D, so that if a level fluctuation occurs, it is returned to the original size. As a result, the RY signal also returns to its original size.

FIG. 5 shows a position where the ALC additional pulse is generated. FIG. 5A shows a video signal, and FIG.
(B) shows BGP. The ALC additional pulse is shown in FIG.
It occurs within period A of (a). The period A is a period from when the content of the video signal ends to when the next 1H burst signal starts. FIG. 5C shows the ALC in the period A.
3 shows an additional pulse.

The signal shown in FIG. 4 (b) is applied to the CCD IC (7), and when it is output, attenuation occurs as shown in FIG. 4 (c). And this attenuated signal is the first
The voltage is applied to the clamp circuit (10), the LPF (13), and the first ALC circuit (38). Note that the RY signal is also B
The signal is transmitted in the same manner as the -Y signal. Clamp detection circuit (2
9) compares the level of the BY signal from the LPF (13) with the reference voltage Vref of the reference power supply (30) during the BGP period from the terminal (31) and compares the level of the BY signal with the BGP.
A detection output for setting the level of the period to the level of the reference voltage Vref is applied to the first clamp circuit (10). Therefore, when the pedestal level is clamped to the reference voltage Vref, R
A -Y signal is generated from the first clamp circuit (10). The output of the clamp detection circuit (29) is also applied to the second clamp circuit (11), and the level of the RY signal is also adjusted in the same manner as the BY signal.

The output signal of the first ALC circuit (38) is applied to the detection circuit (32). The detection circuit (32) switches (3) in accordance with the ALC additional pulse from the terminal (33).
4) is closed, and the ALC additional pulse applied by the additional circuit (27) is extracted. The ALC additional pulse is 0.2 V
However, the level has decreased due to the influence of the CCDIC (7) and the LPF (12). Therefore, a voltage obtained by adding the reference voltage Vref of the reference power supply (30) and 0.2V of the reference power supply (36) of the additional circuit (27) is set as a reference voltage, and it is detected how much the level has dropped from this voltage. By doing so, the level-reduced signal is returned to the original signal. The comparator (35) applies the detection output to the holding capacitor (37), and outputs the first and second ALC circuits (38) and (3) based on the output voltage of the capacitor (37).
Adjustment is made so that the amplitude of 9) becomes large. As a result, at the output terminals of the first and second ALC circuits (38) and (39), the BY signal and the RY signal equal to the level before being input to the CCDIC (7) are obtained.

For this reason, signals of about 1H having the same level are applied to the first and second adders (14) and (15), and the first and second adders (14) and (15) add the signals. By the operation, phase distortion generated in the transmission system can be reduced, and hue fluctuation can be prevented. First and second adders (14) and (1)
The demodulated RY signal and BY signal from 5) are matrixed by a matrix circuit (16), and the RY signal, BY signal, and GY signal are output from the output terminals (17) to (17). 19).

Therefore, according to the circuit of FIG. 2, it is possible to demodulate the PAL color signal. FIG. 6 shows a specific circuit example of the detection circuit (32) and the comparator (35) of FIG. 1. A BY signal is supplied to a terminal (50) and a reference power supply (30) is supplied to a terminal (51). A reference voltage Vref is applied. The multiplication value of the current value of the constant current source (52) and the resistance (53) is 0.2.
V is set. Therefore, the transistor (54)
The comparison between the comparator and the transistor (55) is a comparison operation of the comparator (35). The ALC additional pulse is output from the switch (56).
Are opened and closed, and the comparison operation is performed only during the period in which the ALC additional pulse arrives, and the comparison output is output to the output terminal (57).

[0026]

As described above, according to the present invention, the level of the PAL color signal before and after the delay can be equalized, and if the two signals are added, the color signal distortion can be accurately corrected. be able to. Further, according to the present invention, ALC is performed using an ALC additional pulse, so that a weak electric field or the like can be used.
ALC can be accurately performed even when the level of the color signal is not stable.

Further, according to the present invention, since ALC is performed on the color signal immediately before entering the adder, it is possible to correct not only the CCD fluctuation but also the level fluctuation of the LPF and the like.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a PAL color signal demodulation circuit of the present invention.

FIG. 2 is a block diagram illustrating a conventional PAL color signal demodulation circuit.

FIG. 3 is a vector diagram for explaining the operation of FIG. 2;

FIG. 4 is a waveform chart for describing the operation of FIG. 1;

FIG. 5 is a waveform chart for describing the operation of FIG. 1;

FIG. 6 is a diagram showing a specific circuit example of a detection circuit (32) and a comparator (35) in FIG. 1;

[Explanation of symbols]

 (2) BY demodulator (3) RY demodulator (8) First CCD circuit (9) Second CCD circuit (14) First adder (15) Second adder (38) First ALC circuit (39) ) Second ALC circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 9/66 H04N 9/64 H04N 9/68 102

Claims (4)

(57) [Claims] 1. A first demodulator for demodulating a first color difference signal, a second demodulator for demodulating a second color difference signal, and applying an ALC additional pulse to a predetermined position of an output signal of the first demodulator. Adding means, a first CCD for delaying an output signal of the first demodulator to which an ALC additional pulse is added for 1H period, and a second CC for delaying an output signal of the second demodulator for 1H period
D, and the output of the first CCD is received as an input signal.
Signal is adjusted in amplitude based on the control signal, and the output signal level is adjusted.
So that the bell matches the output signal level of the first demodulator.
A first ALC circuit, and an ALC additional pulse in an output signal of the first ALC circuit.
Level and the ALC additional pulse added by the additional means
And outputs the difference as the control signal.
A comparator and the second CLC in response to the control signal of the first ALC circuit.
A second ALC circuit for adjusting the magnitude of the output signal of the CD, a first adder for adding the output signal of the first demodulator and the output signal of the first ALC circuit, and an output signal of the second demodulator. A second adder for adding an output signal of the second ALC circuit to the PAL color signal demodulation circuit. 2. A first demodulator for demodulating a first chrominance signal, a second demodulator for demodulating a second chrominance signal, and a burst signal from the end of the video signal of the output signal of the first demodulator. Adding means for applying an ALC additional pulse until the beginning, a first CCD for delaying the output signal of the first demodulator to which the ALC additional pulse has been added for 1H period, and delaying an output signal of the second demodulator for 1H period 2nd CC to do
D, and the output of the first CCD is received as an input signal.
Signal is adjusted in amplitude based on the control signal, and the output signal level is adjusted.
To the bell is aligned with the output signal level of said first demodulator
A first ALC circuit, and an ALC additional pulse in an output signal of the first ALC circuit.
Level and the ALC additional pulse added by the additional means
And outputs the difference as the control signal.
A comparator and the second CLC in response to the control signal of the first ALC circuit.
A second ALC circuit for adjusting the magnitude of the output signal of the CD, a first adder for adding the output signal of the first demodulator and the output signal of the first ALC circuit, and an output signal of the second demodulator. A second adder for adding an output signal of the second ALC circuit to the PAL color signal demodulation circuit. 3. A first demodulator for demodulating a first color difference signal, a second demodulator for demodulating a second color difference signal, and applying an ALC additional pulse to a predetermined position of an output signal of the first demodulator. Adding means, a first CCD for delaying an output signal of the first demodulator to which an ALC additional pulse is added for 1H period, and a second CC for delaying an output signal of the second demodulator for 1H period
D, a first clamp circuit for clamping an output signal of the first CCD to a clamp level, a second clamp circuit for clamping an output signal of the second CCD to a clamp level, and an output of the first clamp circuit as an input signal. Receiving
The amplitude of the input signal is adjusted based on the control signal, and the output
The signal level matches the output signal level of the first demodulator.
A first ALC circuit to be activated, and an ALC additional pulse in an output signal of the first ALC circuit.
Level and the ALC additional pulse added by the additional means
And outputs the difference as the control signal.
A comparator, a second ALC circuit for adjusting a magnitude of an output signal of the second clamp circuit according to the control signal of the first ALC circuit, an output signal of the first demodulator, and an output signal of the first ALC circuit And a second adder for adding the output signal of the second demodulator and the output signal of the second ALC circuit. 4. A first demodulator for demodulating a first color difference signal, a second demodulator for demodulating a second color difference signal, and applying an ALC additional pulse to a predetermined position of an output signal of the first demodulator. Adding means, a first terminal to which a signal obtained by delaying the output signal of the first demodulator to which an ALC additional pulse has been added for 1H period is applied, and a signal obtained by delaying the output signal of the second demodulator for 1H period And an output of the first terminal as an input signal, and the input signal
Is adjusted based on the control signal, and the output signal level is adjusted.
A first ALC circuit, and an ALC additional pulse in the output signal of the first ALC circuit.
Level and the ALC additional pulse added by the additional means
And outputs the difference as the control signal.
A comparator, a second ALC circuit that adjusts a signal level from the second terminal according to the control signal of the first ALC circuit, and an output signal of the first demodulator and an output signal of the first ALC circuit. A PAL color signal demodulation circuit comprising: a first adder for adding; and a second adder for adding an output signal of the second demodulator and an output signal of the second ALC circuit.