JP3243990B2 - Digital broadcast receiving terminal device and its packet data recording device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital broadcast receiving terminal device and a packet data recording device thereof, and more particularly to a receiving terminal device for receiving transmitted digital broadcast packet data and recording the received packet data on a tape-shaped recording medium. And a packet data recording device.

[0002]

2. Description of the Related Art At present, with the advancement and development of digital technology and integrated circuit technology, not only existing analog television broadcasting but also digital broadcasting has come into practical use. In this digital television broadcast, for example, a DSS (Digital Satellite System) practically used in the United States is a unique packet, and a DVB practically used in Europe is a DVB.
In (Digital Video Broadcasting), a plurality of programs (programs) are time-division multiplexed and transmitted using an MPEG2 transport packet, which is a color moving image encoding method.

FIG. 8A is a schematic system configuration diagram of the above-described packet transmission, in which transmission information such as video and audio of a plurality of programs (multi-programs) is converted into (transport) packets by an encoder 81, and then the time is converted. Divided and multiplexed.
At this time, when receiving the (transport) packet of any one program, the buffer memory of the receiver does not overflow or underflow.
Send (transport) packets of each program at time intervals.

Accordingly, when transmitting this packet,
It is necessary to accurately reproduce the packet interval (generally called an arrival interval or an arrival time) together with the packet content on the receiving device side.
2 and the receiving unit 85 transmit and receive in a time-managed state.

[0005] The above-mentioned packet data is converted to a transmission frequency band by a transmission unit 82 operating based on a network clock 83 and then transmitted to a network 84. The receiving unit 85, which operates based on the network clock 83, receives and demodulates the packet data arriving via the network 84, and then restores the packet data of the desired program by the decoder 86. In the above-described packet transmission system, the transmission unit 82 and the reception unit 85 operate in synchronization with the network clock 83 and operate in a time-dependent manner, and there is no shift in packet intervals due to delay fluctuation (time fluctuation) occurring in the network 84. It has been like that.

[0006]

However, when the above-described packet data is directly applied to a system for recording and reproducing the packet data on a recording medium, as shown in FIG. It can be considered that the configuration is such that the packet data is recorded on the recording medium at 87, the packet data is reproduced by the reproducing device 88 through the recording medium, and output to the decoder 86. Here, the recording device 87 and the reproducing device 88 need to operate based on the system clock from the same clock oscillator 89.

However, if the clocks of the recording device 87 and the reproducing device 88 are different, the input clocks are different. Therefore, when the compatible reproducing is repeated between the different recording and reproducing devices,
Errors in the data rate and the packet interval may be accumulated and exceed the allowable value. For example, as shown in FIG. 9A, it is assumed that packet data is recorded and reproduced by an apparatus A ′ including a recording unit 91, a reproducing unit 92, and a 27 MHz oscillator 93.

Here, a system clock of 27 Mz is used.
Is oscillated and supplied to the recording unit 91 and the reproducing unit 92.
The 7 MHz oscillator 93 corresponds to the clock oscillator 89, and generates a 27 MHz clock having an error of -5% within the allowable range of ± 5% but full of the allowable limit due to individual differences and aging. For example, when the packet 1 and the packet 2 schematically shown in FIG. 10A are sequentially received at regular time intervals and input to the recording unit 91, the recording unit 91 performs the processing shown in FIG. As schematically shown, the packet 2 is recorded on the recording medium p ′ with the time stamp value “105” added.

When the recording medium p 'is reproduced by the reproducing section 92 (that is, in the case of self-recording / reproducing), the recording medium p' is reproduced by using the same system clock from the 27 MHz oscillator 93 as at the time of recording. The reproduction output a 'is shown in FIG.
As schematically shown in (C), since the packet 2 is reproduced at the timing of the clock value “105”, it is reproduced at the same regular time interval as when it was received.

[0010] However, the recording medium p 'recorded by the recording section 91 described above is reproduced by the reproduction section 95 shown in FIG.
When reproduced by the reproducing apparatus B 'including the oscillator 96, 27M
Hz oscillator 96 has a tolerance of ± due to individual differences and aging.
27M with + 5% error within 5% but full tolerance
When the Hz clock is generated, the reproduced output b '
As schematically shown by 0 (D), the packet 2 to which the time stamp value “105” is added is shifted by about + 10% in clock value from the timing of normal reproduction and at a timing exceeding the allowable range. It will be played.

Further, when the above-mentioned reproduced output b 'is recorded by the recording section 97 of another recording / reproducing apparatus C' shown in FIG. Even if the error of the output clock of the 27 MHz oscillator 99 supplying the system clock is ± 0%, the recording unit 97
Therefore, as schematically shown in FIG. 10E, the packet 2 is input at the timing of the clock value “110”, so that the packet 2 is recorded with the time stamp value “110” added thereto. .

When this recording medium is reproduced by the reproducing section 98, the reproduction is performed using the same system clock from the 27 MHz oscillator 99 as at the time of recording. Therefore, the reproduced output c 'is shown in FIG. As schematically shown in FIG. 5, since the packet 2 to which the time stamp value “110” is added is reproduced at the timing of the clock value “110”, it is reproduced at a timing exceeding the allowable range.

The present invention has been made in view of the above points,
It is an object of the present invention to provide a digital broadcast receiving terminal device and a packet data recording device capable of decoding correctly even if recording and reproduction of packets are repeated between different devices.

Another object of the present invention is to provide a digital broadcast receiving terminal device and a packet data recording device capable of recording a packet with a simple configuration without analyzing the packet structure.

Still another object of the present invention is to provide a digital broadcast receiving terminal device and a packet data recording device capable of performing correct time management even when a packet to which different time management information is added by a plurality of programs is input. Is to provide.

[0016]

In order to achieve the above object, a receiving terminal device of the present invention provides a digital broadcast signal in which at least a packet of information of each of a plurality of programs and a packet containing time management information are multiplexed. Demodulation means for receiving and demodulating, selection means for selecting a packet of a desired program from an output signal of the demodulation means, and identification information for identifying a packet containing time management information among the packets selected by the selection means are selected. And transmission means for transmitting the packet together with the packet, and a decoder for decoding the input packet.

According to another aspect of the present invention, there is provided a packet data recording apparatus for identifying a packet of information of one or more programs, a packet including time management information, and a packet including time management information. Extracting means for receiving a digital signal multiplexed with identification information to be multiplexed and extracting time management information based on the identification information; clock generating means for generating a clock synchronized with the time management information extracted by the extracting means; Recording means for forming a sequential track on a recording medium based on a reference control signal synchronized with a clock output from the clock generating means and recording a digital signal.

In the receiving terminal device of the present invention, the identification information is added to the packet including the time management information among the input packets and transmitted. The packet data recording device of the present invention adds the time management information extracted based on the identification information to the packet. Since the above-mentioned packet is recorded on the recording medium based on the synchronized clock, accumulation of errors in the data rate and the packet interval of the reproducing apparatus can be prevented even when recording and reproducing are repeated.

Further, when the packet selected by the selecting means is a packet of a plurality of programs, and the packet including the time management information has a different packet identification number, the assigning and transmitting means in the receiving terminal device of the present invention, Since the identification information for identifying only the packet with one packet identification number is added and transmitted, it can be generated using only the time management information of one packet identification number as the clock generated by the packet data recording device. it can.

[0020]

Next, an embodiment of the present invention will be described. FIG. 1 shows a block diagram of an embodiment of a digital broadcast receiving terminal device and a packet data recording device thereof according to the present invention. In the figure, a receiving terminal device 10 for receiving a digital television broadcast signal is a set top
It is called a box (STB), and includes a tuner 11, a digital demodulation / error correction / scrambling circuit 12, a demultiplexer 13, a system control unit 14, and a switch (S
W) circuit 15, flag setting circuit 16, decoder 17, header adding circuit 18, and digital interface (I
/ F) circuit 19.

The magnetic recording / reproducing device 20 is an embodiment of a packet data recording device, in which packet data received from the receiving terminal device 10 is input and recorded, and the reproduced packet data is transmitted to the receiving terminal device 10. This is a helical scan recording / reproducing device that supplies and demodulates and displays. The magnetic recording / reproducing device 20 includes a digital I / F circuit 2
1. Program time reference value (PCR: Program Cloc
k Reference) extraction circuit 22, 27 MHz PLL 23,
It comprises a recording processing circuit 24, a rotating drum 25, a magnetic tape 26, a reproduction processing circuit 27 and the like.

Here, it is assumed that the receiving terminal device 10 receives a digital multi-channel CS broadcast signal of an MPEG2 transport stream as an example. The broadcast signal includes channel selection by the tuner 11 and demultiplexer 1
Since the packet specification in step 3 is necessary, the program specification information (PSI: Program Specific Information) 1 for making the receiving terminal device select a channel without being aware of the use of the transmission path is 1
It is transmitted together with an 88-byte fixed-length packet.

The PSI includes a program association table (PAT), a program map table (PMT), a conditional access table (CAT), and a network information table (NIT). The PAT indicates a packet identifier (PID) of the PMT that transmits information of a packet constituting each program, and “0” is fixedly assigned as the PID of the PAT itself. Also, PMT
Indicates the PID of a packet in which a stream of video, audio, additional data, etc., constituting the program is transmitted for each program number. The PID of the PMT itself is specified by PAT. Further, CAT indicates a PID of a packet transmitting descrambling information for descrambling, and NIT indicates physical information on a transmission path.

Next, the operation of this embodiment will be described. The digital broadcast signal is received by the tuner 11 in the receiving terminal device 10 via the antenna. The tuner 11 selects a desired reception transponder signal designated by a channel selection signal from the system control unit 14 output based on the user's program selection information, and demodulates the signal by the digital demodulation / error correction / scrambling circuit 12. , Error correction and descrambling processing to output a transport stream (TS) packet.
Multi-program TS from desired receiving transponder
The packets are supplied to a demultiplexer 13, where only packets of a desired channel designated by a channel selection signal from the system control unit 14 are separated.

That is, a PID is assigned to each of the 188-byte fixed-length received packets sequentially input to the demultiplexer 13, and a program-related information table called PSI is transmitted as described above. I have. The demultiplexer 13 unconditionally refers to the PAT (program table) of PID = 0, selects a required program, and selects a PAT corresponding to the selected program.
A required PID is determined from a program correspondence table called MT, and packets of the PID are separated.

For example, assuming that the PAT of the program 1 is "05", the PID of the program 2 is "07", and the PID of the program 3 is "09" as shown in FIG. When the program 1 is selected, the multiplexer 13 refers to the PMT of the packet of PID = 05 shown in FIG. 2B and separates the packets of PID = 10 and 11 and reproduces the audio data of CH1 and CH2 by the decoder 17, The video data is reproduced by the decoder 17 by separating the packets of PID = 12.

Similarly, when program 2 is selected, PI
With reference to the PMT of the packet of D = 07 shown in FIG. 2C, the audio data packets of CH1 and CH2 of PID = 20 and 21 are separated, and the video data packet of PID = 22 is separated. PI when program 3 is selected
With reference to the PMT shown in FIG. 2D of the packet with D = 09, the packets of the audio data of CH1 and CH2 of PID = 30 and 31 are separated, and the packet of the video data of PID = 22 is separated. Although the selected PID may be fixed until the end of the program, a new PID may be set in the middle of the program.
It may be changed by AT and PMT.

The output packet of the demultiplexer 13 is supplied to the switch circuit 15 shown in FIG. The switch circuit 15 outputs the received packet to the decoder 17 when receiving and playing back the data on the monitor. The decoder 17 outputs a PCR packet of each program (for example, PID in program 1).
= 15 packets), and decodes the received packet in synchronization with a constant frequency 27 MHz clock obtained by extracting a PCR from the extracted packets to output video and audio to a monitor.

The switch circuit 15 includes a magnetic recording / reproducing device 20
When a received packet is recorded on a magnetic tape, the switch circuit 15 is switched so as to selectively output the received packet to the header adding circuit 18. The header adding circuit 18 adds a 4-byte header to all 188-byte fixed-length packets input from the switch circuit 15 and transmits the packet to the magnetic recording / reproducing device 20 via the digital I / F circuit 19. This header is provided with a flag area for PCR identification.

In response to a control signal from the system control unit 14, the flag setting circuit 16
The header providing circuit 18 is controlled so that the packet having the CR is identified and the header providing circuit 18 sets the PCR identifying flag in the PCR identifying flag area of the header provided to the packet having the PCR. This is to make it easier for the magnetic recording / reproducing device 20 to extract the PCR.

To further explain how to set the flag, when recording the program 1 and the program 2 now, the PCR of the program 1 is added as shown in the PMT of the program 1 in FIG. Packet PI
D is “15”, and PM of program 2 in FIG.
As shown in T, the PID of the PCR-added packet of the program 2 is “25”, and the PCR-added packets are different from each other. In this case, the header providing circuit 18 sets the PCR identification flag only in the header of one of the packets of PID = 15 and PID = 25.

This is because if the PCRs of both packets are used together, the 27 MHz PLL 23 having the configuration shown in FIG. 3 cannot correctly generate a constant frequency of 27 MHz because these packets are out of phase. 27M
The original purpose of the Hz PLL 23 is to use a time-based synchronization signal 27M whose frequency matches the system clock at the time of encoding.
Hz.

For example, program 1 and program 3
Is recorded, the P of program 1 in FIG.
As shown in the MT, the PID of the packet to which the PCR of the program 1 is added is “15”, and as shown in the PMT of the program 3 in FIG.
The PID of the packet to which is added is “15”, and in this case, the packet to which PCR is added is the same. In this case, the header adding circuit 18 sets a PCR identification flag in the header of the packet with PID = 15.

The received packet including the packet for which the PCR identification flag is set by the flag setting circuit 16 is used as a recording packet via the digital I / F circuit 19 controlled by the system control unit 14 for the magnetic recording / reproducing apparatus 2.
The signal is supplied to the digital I / F circuit 21 in the “0”, and further supplied to the PCR extraction circuit 22 and the recording processing circuit 24.

The PCR extraction circuit 22 detects a PCR identification flag from the input packet, extracts a PCR from the packet having the PCR identification flag,
The clock is supplied to a phase locked loop circuit (PLL) 23 to generate a time-based synchronization signal 27 MHz whose frequency matches the system clock at the time of encoding. The time-based synchronization signal is supplied to the recording processing circuit 24.

The 27 MHz PLL 23 has a configuration as shown in the block diagram of FIG. That is, the input PCR initializes the counter 35 to that value and simultaneously sets the subtractor 31
, Where it is subtracted from the output value of the counter 35,
After the difference value is converted to an analog signal by the D / A converter 32, the analog signal is passed through a low-pass filter (LPF) 33.
It is supplied to a MHz voltage controlled oscillator (VCO) 34 and variably controls its output oscillation frequency. The oscillation frequency of 27 MHz output from the VCO 34 is output as a system clock, is supplied to a counter 35, is divided, and is fed back to a subtracter 31.

Returning again to FIG. 1, the recording processing circuit 24 sends the digital I / F circuit 2 from the receiving terminal device 10.
The packet supplied to 1 is recorded on the magnetic tape 26 by a rotating head (not shown) attached to the rotating drum 25. The recording processing circuit 24 has, for example, the configuration shown in the block diagram of FIG. In the figure, the same components as those in FIG. 1 are denoted by the same reference numerals. In FIG. 4, packet data of a multiprogram received and demodulated is a digital I / O packet.
The signal is supplied to the PCR extracting circuit 22 and the recording time stamp adding circuit 41 via the / F circuit 21.

The 27 MHz clock output from the PLL 23 as the arrival time management clock is supplied to the mod N counter 42 and is divided by 1 / N. Here, the value of the frequency division ratio N is set to “225000” when the system frequency of the apparatus is 30 Hz, so that the counter 42 outputs a signal of 120 Hz. When the system frequency is 29.97 Hz, the value of the dividing ratio N is “22522”.
5 "and the counter 42 outputs 119.88 Hz.
Is output.

The output signal of the counter 42 is supplied to a recording time stamp adding circuit 41, a mod 12 × k counter 43, and frequency dividers 44 and 45, respectively. The recording time stamp adding circuit 41 adds a 32-bit time stamp indicating the arrival time of the packet data from the digital I / F circuit 21 to the header of the packet data from the digital I / F circuit 21. Even when a time stamp is added to the header of the packet data from the digital I / F circuit 21, a new time stamp is added instead.

The 32-bit time stamp uses the 18-bit count value from the counter 42 as the lower bit, and outputs, for example, 10 Hz (k = 1) from the counter 43.
), The 26-bit count value of the 8-bit count value in the upper case (the upper 4 bits are always 0).
A total of 32 bits, with the upper 6 bits added as a reserve. It is assumed that the packet data to the digital I / F circuit 21 arrives at the receiving terminal device 10 with the arrival time interval maintained.

The frequency divider 44 is a circuit that divides the output signal of the counter 42 by a frequency division ratio corresponding to the recording / reproducing mode to generate a reset signal of a 6-track cycle. 42, 43 and 1/4
The signals are input to the frequency dividers 45 as reset signals. Here, as the recording / reproducing mode, the recording rate is 1
There are an STD mode with 9 Mbps × 1 (ch) and an HD mode with a recording rate of 19 Mbps × 2 (ch).

Here, two tracks are scanned by one rotation of the rotating drum 25, which will be described later, and one track scanning is 1/6.
Since the time is 0 second, in the STD mode in which recording and reproduction are performed at half the speed of the tape running speed in the existing VHS standard mode, the frequency dividing ratio of the frequency divider 44 is set to 1/12,
6 times ((1/60) × 6 = 1/10) track scanning
10 Hz is output so that tracks can be recorded and reproduced.
In the HD mode in which two rotating heads simultaneously record and reproduce two tracks simultaneously in 1/60 second at the same speed as the tape running speed in the existing VHS standard mode, the frequency division ratio of the frequency divider 44 is 1 / 6, 3 times ((1/60) ×
The frequency is set to 20 Hz so that six tracks can be recorded and reproduced by the track scanning of (3 = 1/20). The counter 4
When k is 1 / (12 × k) of the dividing ratio of 3, the recording rate is S
The magnification for the TD mode is shown.

The frequency of the 1/4 frequency divider 45 is 30 Hz or 2
The output signal of 9.97 Hz is input as a rotation reference signal of the rotating drum 25 to a drum rotation control circuit including a motor (not shown) and a drive control circuit for the motor. Thus, the rotating drum 25 is synchronously rotated at 30 rps or 29.97 rps by a motor (not shown). This rotating drum 25
Is that two rotating heads (or two double azimuth rotating heads) having different azimuth angles (not shown) are mounted on the rotating surfaces of the rotating heads facing each other, and the magnetic tape 26 running at a constant speed is slightly more than 180 °. It is wound diagonally over a large angle range.

Here, the two rotary heads are supplied with the packet data having the time stamp in the header extracted from the processor 46 having a memory, so that the known helical scan recording can be performed on the magnetic tape. To do.

In the recording processing circuit 24, a track number indicating the order of the recording tracks is also generated in the recording device and recorded on the magnetic tape. That is, the processor 46 generates a track number synchronized with the six-track reference signal from the frequency divider 44 and records the track number on the track on the magnetic tape 26. Therefore, the change of the time stamp and the recording track number are recorded in correspondence. Similarly to a conventional helical scan type VTR, a control pulse having a two-track cycle is recorded on a magnetic tape by a control head (not shown).

In this embodiment, recording is performed in a synchronous manner in which the change of the time stamp value and the recording track position are synchronized. That is, the rotating drum 25 rotates in synchronization with the change of the time stamp, which is the count value of the counters 42 and 43, to sequentially form the recording tracks, and the six track reference signal synchronized with the time stamp change. At the track repetition period, the processor 46 specifies the position of the recording track and records packet data having a time stamp.

The recording processing circuit 24 controls the rotation of the rotary drum 25 and newly generates a time stamp in synchronization with the repetition position of the six tracks in the recording device, and newly adds the time stamp to the packet data and records it. There are features.

The packets recorded on the magnetic tape 26 are reproduced by a reproduction processing circuit 27. The reproduction processing circuit 27 has, for example, a configuration as shown in the block diagram of FIG. In the figure, the same components as those in FIG. 1 are denoted by the same reference numerals. In FIG. 5, the recorded digital signal on the magnetic tape 26 is reproduced by a rotating head (not shown), and the reproduced signal is supplied to a processor 58.

On the other hand, the oscillation output signal (clock) of 27 MHz output from the crystal oscillator 51 is mod N
After the 1 / N frequency division by the counter 52 of FIG.
3, a mod 12 × k counter 54 and a ４ frequency divider 55, respectively. The output signal of the 1/4 frequency divider 55 is output as a rotation control signal of the rotating drum 25. The output signal of the frequency divider 56 is output to the processor 58
Is input as a reference signal having a 6-track cycle, and 1
While being input to the ４ frequency divider 55 as a reset signal,
Counters 62 and 64 via one-track delay circuit 57
Are respectively input as reset signals.

Here, the frequency divider 56 has a frequency division ratio of 1/12 in the STD mode and 1/6 in the HD mode. It should be noted that the division ratio of the counter 54 is 1 / (12 ×
k in k) indicates a magnification of the recording rate with respect to the STD mode.

The processor 58 discriminates the track number from the reproduction signal, compares the track number with the reference signal from the frequency divider 56, and generates a capstan control signal so that the two are synchronized with each other to drive the capstan 59. The rotation of a motor (not shown) is controlled, and the running phase of the magnetic tape 26 is controlled. Note that a reproduction control pulse is also used for controlling the rotation of the capstan 59, similarly to the existing helical scan type VTR. Further, the processor 58 separates the time stamp from the reproduction signal and supplies the time stamp to the comparison circuit 53.

The output signal of the frequency divider 56 is
This signal is input as a reset signal of the 1/4 frequency divider 55, and after being delayed (offset) by one track period by the one-track delay circuit 57, the signals are sent to the counters 52 and 54. Each is input as an output time management reset signal.

Therefore, the count values of the counters 52 and 54 are offset-synchronized with the position on the track to be reproduced, and the 18-bit count value from the counter 52 and the 8-bit count value from the counter 54 (output clock) ) Are compared in the comparison circuit 53 with the lower 18 bits of the 26-bit time stamp in the reproduction signal from the processor 58 and whether they match the upper 8 bits, and when they match, the comparison circuit 53 generates an output command. .

When this output command is input, the processor 58 reads out the reproduced packet data with the time stamp added to the header stored in its internal memory, via the digital I / F circuit 21. To the digital I / F circuit 19 in the receiving terminal device 10.

The reproduced packet data input through the digital I / F circuit 19 is
, While the PCR is extracted and input to a 27 MHz PLL (not shown). The decoder 17 decompresses and demodulates the input reproduced packet data based on the clock from the 27 MHz PLL, and outputs, for example, video and audio.

According to this embodiment described above, even if the compatible reproduction is repeated between different recording / reproducing apparatuses, errors in the data rate and the packet interval do not accumulate.
Therefore, it does not exceed the allowable value. About this,
An apparatus similar to the apparatus described with the conventional problem will be described with reference to FIG. In the figure, the same parts as those in FIGS. 4 and 5 are denoted by the same reference numerals.

First, in the recording / reproducing apparatus A shown in FIG. 6A, the packet supplied from the receiving terminal is input to the recording unit 61, and the PCR extracted from the input packet by the PCR extraction circuit 22 is converted to a 27 MHz PLL 23. , Where a reference synchronization signal synchronized with the PCR is generated and supplied to the recording unit 61. The recording unit 61 is a circuit corresponding to the recording processing circuit 24 in FIG. 4 and operates as described above based on the input synchronization signal, and records the input packet on the magnetic tape p. The magnetic tape p is reproduced on the basis of the output 27 MHz of the 27 MHz oscillator 51a (corresponding to the crystal oscillator 51 in FIG. 5) by the reproducing section 62 corresponding to the circuit portion of the reproduction processing circuit 27 in FIG. And outputs the output a.

Here, as schematically shown in FIG. 7A, when packet 2 is received at regular time intervals after packet 1 and input to recording unit 61, recording unit 61 Operates with a reference synchronization signal synchronized with the input PCR, so that the packet 2 is recorded with a time stamp value “100” as schematically shown in FIG. 7B.

The recording tape p is supplied from the 27 MHz oscillator 51a of the reproducing section 62 to the 27 MHz oscillator 51a which has an error of -5% within the allowable range, but within the allowable range of ± 5% due to individual differences and aging. When the data is reproduced by the reproducing unit 62 of the recording / reproducing apparatus A, the reproduced output a of the packet 2 having the time stamp value “100” is reproduced at the clock value “100” as schematically shown in FIG. Thus, the data is reproduced at a timing -5% earlier than the original timing (the packet interval shown in FIG. 7A). However, since it is within ± 5% of the allowable range, there is no problem in self-recording / reproducing by the recording / reproducing apparatus A.

Further, the magnetic tape p is set within the allowable range of ± 5.
% But within tolerance of + 5% error of 27M
When the Hz clock is reproduced by the reproducing unit 63 of the reproducing apparatus B shown in FIG. 6B having the same configuration as the reproducing unit 62 supplied from the 27 MHz oscillator 51b, the reproduced output b becomes FIG.
As schematically shown in (D), although the packet 2 with the time stamp value "100" has the clock value "100", it is reproduced at a timing + 5% later than the original timing. However, since it is within ± 5% of the allowable range, there is no problem of reproduction.

Further, when the above-mentioned reproduction output b is recorded by the recording section 64 of another recording / reproducing apparatus C shown in FIG. 6C, the recording section 64 uses the reference synchronization synchronized with the PCR of the reproduction output b. 7E, the timestamp value “100” of the packet 2 is changed at the timing of the clock signal “100” of 27 MHz having an error of + 5%, which is the same as the reproduction output b, as schematically shown in FIG. And recorded on a magnetic tape.

Then, this magnetic tape is set to ± 0 with no error.
When reproduction is performed by the reproducing unit 65 of the recording / reproducing apparatus C shown in FIG. 6C having the same configuration as the reproducing unit 62 supplied with the 27% clock of 27% from the 27 MHz oscillator 51c, the reproduced output c becomes FIG. 7F. As schematically shown in (2), the packet 2 to which the time stamp value “100” is added has the clock value “100” and is reproduced at the original timing. Therefore, even when recording / reproducing is performed by the recording / reproducing apparatus C, normal reproduction can be performed without accumulation of clock errors.

As described above, in this embodiment, even if recording and reproduction of packets between different devices are repeated,
The reproduction output affects the data rate and the packet interval only depending on the error from the system clock at the time of encoding the reference synchronization signal supplied to the reproduction unit. it can.

It should be noted that the present invention is not limited to the above-described embodiment, but generates the reference synchronization signal based on PCR. However, the system time reference value (SCR) defined by MPEG2 is used. : System Clock Refer
ence) can also be used. Also, the receiving terminal device 10
In the case where a time stamp (packet arrival time) synchronized with the PCR or SCR is added and transmitted to the magnetic recording / reproducing apparatus, the change may be synchronized with the change of the time stamp.

Further, the receiving terminal device may transmit only the packet identification number of the packet including the time management information to the magnetic recording / reproducing device through a predetermined procedure for generating the recording clock. For example, the digital I / F circuits 19 and 21 are transmitted from the system control unit 14 of the receiving terminal device 10.
Via the PCR extraction circuit 22 of the magnetic recording / reproducing device 20
According to a predetermined procedure (for example, a management communication packet is provided between the devices 10 and 20 to exchange management information), only the packet identification number of the packet including the PCR is sent out. , A packet including a PCR may be extracted.

[0066]

As described above, according to the receiving terminal device and the packet data recording device of the present invention, the time extracted from the input packet based on the identification information given to the packet including the time management information in the header. Since the above-mentioned packet is recorded on the recording medium based on the clock synchronized with the management information, it is possible to prevent the accumulation of errors in the data rate and the packet interval of the reproducing apparatus even when recording and reproducing are repeated. Normal recording and reproduction of digital broadcast signals (packets) can be performed within an allowable error range.

Further, according to the receiving terminal device of the present invention, since identification information is added to a packet including time management information, the time management information does not have to be analyzed on the recording device side, and the packet structure is not required. A circuit for analysis is unnecessary, and a simple configuration can be achieved.

Further, according to the present invention, when the packet selected by the selecting means is a packet of a plurality of programs, and the packet including the time management information has a different packet identification number, one of the packet identification numbers By assigning identification information for identifying only the packet of the packet data, the time is generated using only the time management information of one packet identification number as a clock generated by the packet data recording device. As compared with the case where a clock is generated, a clock of a constant frequency can be generated stably and high-quality packet recording can be performed.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is an explanatory diagram of a packet selection method in FIG. 1;

FIG. 3 is a block diagram of an example of a 27 MHz PLL in FIG. 1;

FIG. 4 is a block diagram of an example of a recording processing circuit in FIG. 1;

FIG. 5 is a block diagram of an example of a reproduction processing circuit in FIG. 1;

FIG. 6 is a diagram illustrating self-recording / reproduction and compatible reproduction according to the embodiment of the present invention.

FIG. 7 is a time chart of a packet for explaining the operation of FIG. 6;

FIG. 8 is a diagram showing a conventional digital broadcast transmitting / receiving system and a system configuration when the system is applied to a recording / reproducing apparatus.

FIG. 9 is a diagram illustrating self-recording / reproduction and compatible reproduction according to an example of the related art.

FIG. 10 is a time chart of a packet for explaining the operation in FIG. 9;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 Receiving terminal apparatus 11 Tuner 12 Digital demodulation, error correction, descrambling circuit 13 Demultiplexer 14 System control unit 15 Switch circuit 16 Flag setting circuit 17 Decoder 18 Header adding circuit 19, 21 Digital interface (I / F) circuit 20 Magnet Recording / reproducing device 22 PCR extraction circuit 23, 34 27 MHz PLL 24 Recording processing circuit 25 Rotating drum 26 Magnetic tape 27 Reproduction processing circuit 31 Subtractor 32 D / A converter 35 Counter 51 a, 51 b, 51 c 27 MHz oscillator 61, 64 Recording unit 62, 63, 65 playback unit

Continuation of the front page (51) Int.Cl. ⁷ Identification code FI H04L 7/00 H04L 7/00 Z H04N 5/92 H04N 5/92 H (56) References JP-A-8-195723 (JP, A) ( 58) Field surveyed (Int.Cl. ⁷ , DB name) H04H 1/00 H04N 5/92 G11B 20/10

Claims (9)

(57) [Claims] 1. A demodulation means for receiving and demodulating a digital broadcast signal in which at least a packet of information of each of a plurality of programs and a packet containing time management information are multiplexed, Selecting means for selecting a packet; providing transmitting means for transmitting together with the selected packet identification information for identifying a packet including the time management information among the packets selected by the selecting means; decoding the input packet A receiving terminal device comprising a decoder. 2. The receiving terminal device according to claim 1, wherein said adding and sending means adds and sets a time management information identification flag to a header of a packet including the time management information. 3. The receiving terminal device according to claim 1, wherein said adding and sending means sends in advance a packet identification number of a packet including said time management information in a predetermined procedure. 4. When the packet selected by the selecting means is a packet of a plurality of programs, and the packet including the time management information has a different packet identification number, the adding / sending means outputs one of the packets. 4. The receiving terminal device according to claim 1, wherein identification information for identifying only a packet with an identification number is added and transmitted. 5. The digital broadcast signal according to claim 1, wherein the digital broadcast signal is a transport packet having MPEG2 program specification information, and the identification information is a program time reference value. Item 3. The receiving terminal device according to Item 1. 6. A digital signal in which a packet of information of one or more programs, a packet containing time management information, and identification information for identifying a packet containing the time management information are respectively multiplexed, Extraction means for extracting the time management information based on information; clock generation means for generating a clock synchronized with the time management information extracted by the extraction means; synchronization with the clock output from the clock generation means Recording means for forming a sequential track on a recording medium based on the reference control signal and recording the digital signal. 7. The packet data recording apparatus according to claim 6, wherein the identification information is a time management information identification flag added to a header of a packet including the time management information. 8. The packet data recording apparatus according to claim 6, wherein the identification information is a packet identification number of a packet including the time management information input in advance in a predetermined procedure. 9. The packet data recording according to claim 6, wherein the digital signal is an MPEG2 transport packet, and the identification information is a program time reference value. apparatus.