JP3237889B2 - Semiconductor substrate and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor substrate and a method for manufacturing the same, and more particularly, to a semiconductor substrate suitable for an electronic device and an integrated circuit formed on a single crystal semiconductor layer on a dielectric isolation or insulator. The present invention relates to a manufacturing method thereof.

[0002]

2. Description of the Related Art The formation of a single-crystal Si semiconductor layer on an insulator is widely known as a silicon-on-insulator (SOI) technique, and has many advantages that cannot be attained by a bulk Si substrate for fabricating a normal Si integrated circuit. Much research has been done because devices using SOI technology have a. That is, by using the SOI technology, 1. Dielectric separation is easy and high integration is possible. 2. Excellent radiation resistance. 3. Higher speed due to reduced stray capacitance. 4. Well step can be omitted; 5. Latch-up can be prevented. It is possible to obtain a fully depleted field-effect transistor by thinning the film.

[0003] In order to realize many of the above advantages in device characteristics, researches have been made on a method of forming an SOI structure for several decades. This content
For example, they are summarized in the following documents.

Special Issue: "Single-crystal silicon
on non-single-crystal insulators "; edited by GW
Cullen, Journal of Crystal Growth, volume 63, no
3, pp429-590 (1983). In the old days, Si was converted to CV on a single crystal sapphire substrate.
D in (chemical vapor deposition) are known SOS (silicon on sapphire) that formed by heteroepitaxially over, has been the videos tentative success as the most mature SOI technology, Si layer and the underlying sapphire substrate interface a large amount of crystal defects due to lattice mismatch, the delay of the Arumini <br/> incorporation into Si layer-menu arm, and high cost and large area of the substrate and foremost from the sapphire substrate, the spread of its application Hindered. In recent years, attempts have been made to realize an SOI structure without using a sapphire substrate. This attempt is roughly divided into the following two.

[0005] 1. The Si single crystal substrate after the surface oxidation, partially expose the Si substrate by opening the window, it is epitaxially laterally the part as sheet over de, to form a Si single crystal layer onto SiO _2. (In this case, a Si layer is deposited on SiO _2. ) The Si single crystal substrate itself is used as an active layer, and SiO ₂ is formed below the active layer. (This method does not involve the deposition of a Si layer.) In addition, devices on compound semiconductors have high performance that cannot be obtained with Si, such as high speed and light emission.
At present, most of these devices are formed by epitaxial growth on a compound semiconductor substrate such as GaAs.

[0006]

As means for realizing the above item 1, a method of directly growing a single crystal layer Si in a lateral direction by CVD, a method of depositing amorphous Si,
A method in which a solid-phase lateral epitaxial growth is performed by heat treatment, an energy beam such as an electron beam or a laser beam is converged and irradiated on an amorphous or polycrystalline Si layer, and a single crystal layer is grown on SiO ₂ by melting and recrystallization. A method and a method of scanning a molten region in a strip shape by a rod-shaped heater (Zone Melting Recrystallization) are known.

Each of these methods has its advantages and disadvantages, but it still has significant problems in controllability, productivity, uniformity, and quality, and there is no industrially practical method yet. For example, the CVD method requires sacrificial oxidation to make a thin film flat, and the solid phase growth method has poor crystallinity. Further, in the bi chromatography Muani Lumpur method, and processing time by the convergence bi chromatography beam scanning, overlapping state of the bi-over beam, there is a problem in controllability such as focusing. Among them, Zone Melting Recrystallizati
Although the on-method is the most mature and relatively large-scale integrated circuits have been prototyped, a large number of crystal defects such as sub-grain boundaries still remain. Not.

In the above-mentioned method 2 in which the Si substrate is not used as a seed for epitaxial growth, there are the following four methods.

1. An oxide film is formed on a Si single crystal substrate having a V-shaped groove anisotropically etched on its surface, and a polycrystalline Si layer is deposited on the oxide film as thick as the Si substrate, and then polished from the back surface of the Si substrate. Thereby, a dielectrically separated Si single crystal region surrounded by V grooves is formed on the thick polycrystalline Si layer.
In this method, the crystallinity is good, but the polycrystalline S
There is a problem in terms of controllability and productivity in the process of depositing i as thick as several hundred microns and the process of polishing a single-crystal Si substrate from the back surface to leave only the separated Si active layer.

[0010] 2. Simox (SIMOX: Seperati
This is a method called on by ion implanted oxygen (Si) to form a SiO ₂ layer by ion implantation of oxygen into a Si single crystal substrate, and is the most mature method at present because it has good compatibility with the Si process. However, in order to form a SiO ₂ layer, it is necessary to implant oxygen ions of 10 ¹⁸ ions / cm ² or more. However, the implantation time is long and the productivity is not high. Cost is high.
In addition, many crystal defects remain, and from an industrial point of view, the quality has not been sufficient to produce a minority carrier device.

3. A method of forming an SOI structure by dielectric isolation by oxidation of porous Si. This method uses P-type Si
Proton ion implantation of N-type Si layer on a single crystal substrate surface (Imai other, J.Crystal Growth, vol 63, 547 (1983)), or formed in an island shape by epitaxial growth and patterns over training, the Si islands from the surface After making only the P-type Si substrate porous by anodizing in HF solution so as to surround it,
This is a method of separating an N-type Si island from a dielectric by accelerated oxidation. In this method, the separated Si region is determined before the device process, and there is a problem that the degree of freedom in device design may be limited.

In addition to the above-described conventional SOI forming method, in recent years, a Si single crystal substrate has been bonded to another thermally oxidized Si single crystal substrate using a heat treatment or an adhesive to form an SOI structure. The method of forming has attracted attention. This method requires that the active layer for the device be uniformly thinned. That is, it is necessary to thin hundreds microns in thickness Si single crystal substrate or a less Mikuron'o over Dark-. There are two types of thinning as described below.

1. 1. Thinning by polishing Thinning by Selective Etching It is difficult to make a uniform thin film by the first polishing. In particular, when the thickness is reduced to a submicron, the variation becomes tens of percent, and the uniformity is a serious problem. Further, as the diameter of the wafer increases, the difficulty only increases.

Although the etching of 2 is considered to be effective for uniform thinning, the selectivity is not enough at most 10 ^2. The surface properties after etching are poor. Ion implantation, high concentration B-doped Si layer There are problems such as poor crystallinity of the SOI layer due to the use of epitaxial growth or heteroepitaxial growth (C. Harendt, et.al., J. Elect. Mater. V
ol. 20, 267 (1991), H. Baumgart, et.al., Extended Abstra
ct of ECS 1st International Symposium of Wafer Bon
ding, pp-733 (1991), CEHunt, Extended Abstract of E
CS 1st International Symposium of Wafer Bonding, pp
-696 (1991)).

Therefore, in the SOI by bonding, the current method has many problems in controllability and uniformity.

As described above, a compound semiconductor substrate is indispensable for manufacturing a compound semiconductor device. However, compound semiconductor substrates are expensive, and it is very difficult to increase the area.

Further, attempts have been made to epitaxially grow a compound semiconductor such as GaAs on a Si substrate, but the grown film has poor crystallinity due to differences in lattice constant and thermal expansion coefficient, and it is difficult to apply it to devices. It has become very difficult.

[0018] In addition, attempts have been made to epitaxially grow a compound semiconductor on porous Si in order to alleviate lattice misfit. However, due to the low thermal stability of porous Si and its aging, devices are being manufactured. Alternatively, it lacks stability and reliability as a substrate after fabrication.

The method of manufacturing a semiconductor substrate according to the present invention comprises the steps of making at least the surface layer on the main surface side of the first Si substrate porous, oxidizing the inner walls of the pores of the porous Si layer, forming a Tan'yui crystallized compound semiconductor layer on the layer, step bonding the the single crystal compound semiconductor layer surface main surface of the second Si substrate through an insulating layer, and bonded Ri substrate was I if after the removal of the first Si substrate, the porous Si layer exposed to the surface, using a higher etching liquid having an etching rate of Si with respect to the single crystal compound semiconductor, etching the porous Si Characterized by having at least a step of removing.

Further, the method for producing a semiconductor substrate of the present invention comprises:
Forming step, a step of oxidizing the inner wall of the pores of the porous Si layer, the Tan'yui crystallization compound semiconductor layer on the porous Si layer made porous surface layer of at least the main surface side of the first Si substrate Bonding the surface of the single crystal compound semiconductor layer and the main surface of the second Si base via an insulating layer;
A step of removing the substrate by polishing or grinding until immediately before or partially exposing the porous Si layer; a first etching step of etching and removing the remainder of the first Si substrate; the exposed porous Si layer, by using a higher etching liquid having an etching rate of Si with respect to the single crystal <br/> of compound semiconductor, a second etching step of removing by etching the porous Si It is characterized by having at least. Further, in the method for manufacturing a semiconductor substrate according to the present invention, a step of preparing a first Si substrate having a porous layer, a step of forming a single-crystal compound semiconductor layer on the porous layer, Via the substrate 2 and the insulating layer,
In addition, the method includes a step of bonding to obtain a multilayer structure in which the single crystal compound semiconductor layer is located inside, and a step of removing the porous layer from the multilayer structure by etching. Also, the other half of the present invention.
The method of fabricating the conductor substrate is as follows.
Porous silicon layer from single crystal silicon region side and single crystallization
An insulating layer formed between the first substrate having the compound semiconductor layer and the second substrate
Forming a multilayer structure by laminating via
Removing the porous silicon layer from the multilayer structure
The single crystal compound on the second substrate via the insulating layer.
A semiconductor layer. Further, a semiconductor substrate of the present invention is characterized by being manufactured by the manufacturing method having the above configuration.

[0021]

According to the present invention, a compound semiconductor layer having good crystallinity can be formed over a large area on an insulating substrate.

According to the method of manufacturing a semiconductor substrate of the present invention,
By performing the two-stage selective etching, a compound semiconductor single crystal having extremely excellent crystallinity, which is uniform and flat over a large area, can be obtained.

It is well known that the oxidation of the inner wall of the porous Si has the effect of suppressing the structural change of the porous Si due to the thermal process. There is also an effect of improving the selectivity between Si and the porous layer.

The selective etching of bulk Si at the first stage is as follows.
Since the inner surface of porous Si is covered with an oxide film, S
By using an etchant having a higher Si etching rate than iO ₂ , the porous Si layer becomes a sufficient etch stop layer.

The second etching of the present invention is achieved by selectively chemically etching only the porous Si layer using an etching solution having a high Si etching rate with respect to the compound semiconductor.

According to the present invention, a single-crystal Si substrate having extremely excellent crystallinity, which is uniform and flat over a large area, is used to leave a compound semiconductor active layer formed on the surface, from one surface to the active layer. To economically obtain a single crystal compound semiconductor layer with extremely few defects on an insulator.

In the present invention, a single-crystal compound semiconductor layer having good crystallinity is formed on porous Si, and this semiconductor layer is economically transferred onto an insulating substrate having a large area. The difference between the lattice constant and the coefficient of thermal expansion, which are problems, can be sufficiently suppressed, and a compound semiconductor layer having good crystallinity can be formed on the insulating substrate.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below.

[Embodiment 1] The Si substrate is, for example, H
What is necessary is just to make it porous by the anodizing method using F solution. This porous Si layer has a single crystal Si density of 2.33 g /
By changing the HF solution concentration to 50 to 20% as compared with cm ³ , the density can be changed to a range of 1.1 to 0.6 g / cm ³ . This porous layer is not formed on the N-type Si layer but is formed only on the P-type Si substrate for the following reason. According to observation with a transmission electron microscope, pores having an average diameter of about 600 angstroms are formed in the porous Si layer.

The porous Si is manufactured by Uhril et al.
It was discovered in the research process of semiconductor electropolishing in 1957 (A. Uhlir, Bell Syst. Tech. J., vol. 35, 333 (195
6)).

In addition, eel and the like are the
And reported that the anodic reaction of Si in HF solution requires holes, and the reaction is as follows (T. Unakami, J. Electrochem. Soc., vol.127, 476
(1980)).

Si + 2HF + (2-n) e ⁺ → Si
^{_{F 2 + 2H ++ ne - SiF}} 2 + 2HF → SiF 4 + H 2 SiF 4 + 2HF → H 2 SiF 6 or, Si + 4HF + (4- λ) e + → SiF 4 + 4H + +
λe ⁻ SiF ₄ + 2HF → H ₂ SiF ₆ Here, e ⁺ and e ⁻ represent a hole and an electron, respectively. Further, n and λ are the number of holes required for dissolving the Si1 atom, and it is assumed that porous Si is formed when the condition of n> 2 or λ> 4 is satisfied.

From the above, it can be seen that P-type Si containing holes exists.
Is made porous, but N-type Si is not made porous. The selectivity in this porous formation has been demonstrated by Nagano et al. And Imai (Nagano, Nakajima, Yasuno, Onaka, Kajiwara, IEICE Technical Report, vol.79, SSD79-9549 (1979)),
(K. Imai, Solid-State Electronics, vol. 24, 159 (198
1)).

However, there is a report that high-concentration N-type Si is made porous (RP Holmstrom and JYChi, A
ppl. Phys. Lett., vol. 42, 386 (1983)), it is important to select a substrate that can realize porosity regardless of whether it is a P-type or an N-type.

According to observation with a transmission electron microscope, pores having an average diameter of about 600 angstroms are formed in the porous Si layer, and the density thereof is less than half that of single crystal Si. Regardless, single crystallinity is maintained, and it is also possible to epitaxially grow a single crystal Si layer on the porous layer. However, 1000 ° C
Above, rearrangement of the internal holes occurs, and the characteristics of the accelerated etching are impaired. Therefore, the epitaxial growth of the Si layer includes molecular beam epitaxial growth, plasma CV
D, a low pressure CVD method, optical CVD, bias spatter method,
Low-temperature growth, such as liquid phase growth, is considered suitable. Further, epitaxial growth of a compound semiconductor layer is also performed. It is reported that porous Si reduces lattice misfit, and compound semiconductors grown epitaxially on porous Si are expected to have good crystallinity.

Further, the density of the porous layer is reduced to less than half since a large amount of voids are formed therein. As a result, the surface area is dramatically increased as compared with the volume, so that the chemical etching rate is significantly increased as compared with the ordinary etching rate of the single crystal layer.

As shown in FIG. 1A, first, a first Si
A single crystal substrate 11 is prepared, and its surface layer is made porous 12
Then, an oxide film is formed on the inner wall of the hole of the porous Si layer. Further, a single crystal compound semiconductor layer 13 is formed on the porous Si (FIG. 1B). As shown in FIG. 1C, the other Si support substrate 14 and the single-crystal compound semiconductor layer 13 are brought into close contact with each other via an insulating layer 15 at room temperature, and then anodic bonding, pressing, heat treatment, or the like. The two are pasted together by the combination of Thereby, the Si support substrate 14
And the single crystal layer 13 are firmly bonded via the insulating layer 15. The insulating layer 15 is formed on at least one of the single crystal compound semiconductor layer and the Si support substrate 14, or three layers of insulating thin plates are sandwiched and bonded.

Next, only the Si support substrate side of the bonded substrate is covered with an etching resistant mask 16 (FIG. 1).
(D)) Using the porous Si layer 12 as an etch stop layer, the Si single crystal substrate 11 is removed by etching (FIG. 1 (e)). This first selective etching is achieved by using, for example, an etchant such as hydrofluoric nitric acid based ethylenediamine + pyrocatechol + water KOH based system which has a higher Si etching rate than SiO ₂ .

Further, only the porous Si layer 12 is chemically etched using an etchant having a high Si etching rate with respect to the compound semiconductor, so that the thinned single-crystal compound semiconductor layer 13 is left on the insulating substrate 15 + 14. And formed.

FIG. 1 (f) shows the semiconductor substrate obtained by the present invention after removing the mask. Insulating substrate 15
The single crystal compound semiconductor layer 13 is flattened and uniformly thinned on +14, and formed over a large area over the entire wafer. The semiconductor substrate obtained in this manner can be suitably used as a compound semiconductor substrate and further from the viewpoint of producing an insulated and separated electronic element.

[Embodiment 2] As shown in FIG. 2 (a), first, an Si single crystal substrate 21 is prepared, its surface layer is made porous 22, and the inner wall of the pores of the porous Si layer is oxidized. Form a film. Further, a single crystal compound semiconductor layer 23 is formed on the porous Si (FIG. 2B). As shown in FIG. 2C, the other Si support substrate 24 and the single-crystal compound semiconductor layer 23 are brought into close contact with each other via an insulating layer 25 at room temperature, and then subjected to anodic bonding, pressing, heat treatment, or the like. Paste with the combination of Thereby, the Si support substrate 24 and the single crystal layer 23 are firmly bonded via the insulating layer 25. The insulating layer 25 is formed on at least one of the single crystal compound semiconductor layer and the Si support substrate 24, or is laminated with three thin insulating sheets.

Next, the Si single crystal substrate 21 is
The layer 22 is removed by polishing and grinding until just before the layer 22 is exposed (FIG. 2D), and the remaining Si single crystal substrate 21 is removed by etching using the porous Si layer 22 as an etch stop layer (FIG. 2E). )). This first selective etching is achieved by using, for example, an etchant such as hydrofluoric nitric acid based ethylenediamine + pyrocatechol + water KOH based system which has a higher Si etching rate than SiO ₂ .

Further, by using an etching solution having a high Si etching rate with respect to the compound semiconductor, porous Si2
Only 2 is chemically etched to leave the single crystal compound semiconductor layer 23 thinned on the insulating substrate 25 + 24.

FIG. 2F shows a semiconductor substrate obtained by the present invention. The single-crystal compound semiconductor layer 23 is flat and uniformly thinned on the insulating substrate 25 + 24,
A large area is formed over the entire wafer. The semiconductor substrate obtained in this manner can be suitably used as a compound semiconductor substrate and further from the viewpoint of producing an insulated and separated electronic element.

[Embodiment 3] As shown in FIG. 3 (a), first, an Si single crystal substrate 31 is prepared, its surface layer is made porous 32, and the inner wall of the pores of the porous Si layer is oxidized. Form a film. Further, a single-crystal compound semiconductor layer 33 is formed on the porous Si layer 32 (FIG. 3B).

As shown in FIG. 3C, the other Si
The supporting substrate 34 and the single crystal compound semiconductor layer 33 are
After bonding at room temperature through the step 5, bonding is performed by anodic bonding, pressing, heat treatment, or a combination thereof. Thereby, the Si support substrate 34 and the single crystal layer 33
Is firmly bonded through the insulating layer 35. The insulating layer 35 is formed on at least one of the single crystal compound semiconductor layer and the Si support substrate 34, or is sandwiched between insulating thin plates.
Laminate and stack.

Next, the Si single crystal substrate 31 is
Polishing and grinding are performed until the layer is partially exposed (Fig. 3
(D)) The remaining Si single crystal substrate 31 is removed by etching using the porous Si layer 32 as an etch stop layer (FIG. 3 (e)). This first selective etching is achieved by using, for example, an etchant such as hydrofluoric nitric acid based ethylenediamine + pyrocatechol + water KOH based system which has a higher Si etching rate than SiO ₂ .

Further, by using an etching solution having a high Si etching rate with respect to the compound semiconductor,
Only 2 is chemically etched to leave the thinned single crystal compound semiconductor layer 33 on the insulating substrate 35 + 34.

FIG. 3F shows a semiconductor substrate obtained by the present invention. The single crystal compound semiconductor layer 33 is made flat and uniformly thin on the insulating substrate 35 + 34,
A large area is formed over the entire wafer. The semiconductor substrate obtained in this manner can be suitably used as a compound semiconductor substrate and further from the viewpoint of producing an insulated and separated electronic element.

[0050]

(Example 1) Specific resistance 0.01 having a thickness of 625 μm
Ω · cm P-type or N-type 6 inch diameter first (1
00) A single crystal Si substrate was anodized in an HF solution.

The anodizing conditions were as follows. Current density: 5 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1 Time: 12 (min) Thickness of porous Si: 10 (μm) Porosity: This substrate was oxidized at 400 ° C. for 1 hour in an oxygen atmosphere. Due to this oxidation, the inner wall of the porous Si hole was covered with the thermal oxide film. MOCVD (Metal Organic Chemical) on porous Si
Single-crystal GaAs was epitaxially grown to a thickness of 1 μm by a vapor deposition method. The growth conditions are as follows. Source gas: TMG / AsH ₃ / H ₂ Gas pressure: 80 Torr Temperature: 700 ° C. The surface of the GaAs layer is superimposed on the surface of the SiO _{2 of} a separately prepared Si substrate on which a second 500 nm thermal oxide film is formed. After contact, heat treatment at 900 ° C for 1 hour,
Lamination was performed. By this heat treatment, both substrates were firmly bonded. Next, only the second Si substrate side of the bonded substrate is covered with Si ₃ N ₄ and 66HNO ₃ + 34HF
Etching with a solution leaving the first Si substrate at 10 μm,
Thereafter, a 10 μm single crystal Si substrate was selectively etched with 1HF + 20HNO ₃ + 20CH ₃ COOH using the porous Si layer whose inner wall of the hole was oxidized as an etch stop layer. After 10 minutes, the first Si substrate was completely etched, exposing the porous Si layer.

After removing the oxide film on the inner wall of the porous Si layer with hydrofluoric acid, the porous Si was etched at 110 ° C. with ethylenediamine + pyrocatechol + water (ratio of 17 ml: 3 g: 8 ml). One minute later, the single-crystal GaAs remained without being etched, and the porous Si substrate was selectively etched using the single-crystal GaAs as a material for the etch stop, and completely removed.

The etching rate of single crystal GaAs with respect to the etching solution is extremely low, and the film thickness can be practically ignored.

That is, after removing the Si ₃ N ₄ layer on the back surface, a single-crystal Ga having a thickness of 1 μm is formed on the insulating substrate.
An As layer was formed. There was no change in the single crystal GaAs layer even by selective etching of porous Si.

As a result of observation of a cross section by a transmission electron microscope, G
No new crystal defects were introduced in the aAs layer, and it was confirmed that good crystallinity was maintained.

Example 2 A P-type or N-type first (100) single-crystal Si substrate having a thickness of 625 μm and a specific resistance of 0.01 Ω · cm and a diameter of 5 inches was anodized in an HF solution. Was done.

The anodizing conditions were as follows. Current density: 10 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1 Time: 24 (min) Thickness of porous Si: 20 (μm) Porosity: This substrate was oxidized in an oxygen atmosphere at 400 ° C. for 2 hours. Due to this oxidation, the inner wall of the porous Si hole was covered with the thermal oxide film. 0.5 μm single crystal AlGaAs was epitaxially grown on the porous Si by MBE (Molecular Beam Epitaxy).

The surface of the AlGaAs layer and the SiO substrate of the Si substrate on which a second separately prepared thermal oxide film of 500 nm was formed.
_{After the two} surfaces were overlapped and brought into contact with each other, heat treatment was performed at 800 ° C. for 2 hours to perform bonding. By this heat treatment, both substrates were firmly bonded.

Next, only the second Si substrate side of the bonded substrate was coated with Si ₃ N ₄ , and ethylenediamine + pyrocatechol + water (17 ml: 3 g: 8 ml)
Etching is performed at 110 ° C. while leaving the first Si substrate at 10 μm, and then a 10 μm single-crystal Si substrate is etched with 1HF + 40HNO ₃ + 40CH ₃ COOH using the porous Si layer whose inner wall of the hole is oxidized as an etch stop layer. Selectively etched. After 20 minutes, the entire first Si substrate was etched, exposing the porous Si layer.

Thereafter, the porous Si was etched with a hydrofluoric acid solution. Two minutes later, the single-crystal AlGaAs remained without being etched, and the porous Si was selectively etched using the single-crystal AlGaAs as an etch stop material, and completely removed.

The etching rate of the single crystal AlGaAs with respect to the etching solution is extremely low, and the film thickness can be practically ignored.

That is, after removing the Si ₃ N ₄ layer on the back surface, a single-crystal Al having a thickness of 1 μm is formed on the insulating substrate.
A GaAs layer was formed. The single crystal AlGaAs layer did not change at all even by the selective etching of the porous Si.

As a result of the cross-sectional observation with a transmission electron microscope,
No new crystal defects have been introduced into the lGaAs layer,
It was confirmed that good crystallinity was maintained.

Example 3 A 6-inch diameter first P-type or N-type (100) single-crystal Si substrate having a thickness of 625 μm and a resistivity of 0.01 Ω · cm was anodized in an HF solution. Was done.

The anodizing conditions were as follows. Current density: 5 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1 Time: 24 (min) Thickness of porous Si: 20 (μm) Porosity: This substrate was oxidized in an oxygen atmosphere at 400 ° C. for 2 hours. Due to this oxidation, the inner wall of the porous Si hole was covered with the thermal oxide film. Single crystal GaP is deposited on porous Si by liquid phase epitaxy.
μm epitaxial growth was performed.

The surface of the GaP layer and a separately prepared 500 n
m of the second Si substrate on which the thermal oxide film of
_{After the two} layers were superposed and brought into contact with each other, they were firmly adhered to each other at room temperature by an anodic bonding method, and then subjected to a heat treatment at 700 ° C. for 2 hours to perform bonding. By this heat treatment, both substrates were firmly bonded.

Next, only the second Si substrate side of the bonded substrate is coated with Si ₃ N ₄ and etched with a 66HNO ₃ +34 HF solution while leaving the first Si substrate at 10 μm. Using a porous Si layer whose inner wall was oxidized as an etch stop layer, a 10 μm single crystal Si substrate was selectively etched. After 10 minutes, the first Si substrate was completely etched, exposing the porous Si layer.

After removing the oxide film on the inner wall of the porous Si layer with hydrofluoric acid, the porous Si was etched at 110 ° C. with ethylenediamine + pyrocatechol + water (ratio of 17 ml: 3 g: 8 ml). Two minutes later, the single-crystal GaP remained without being etched, and the porous Si substrate was selectively etched using the single-crystal GaP as an etch stop material, and completely removed.

The etching rate of single crystal GaP with respect to the etching solution is extremely low, and the film thickness can be practically ignored.

That is, after removing the Si ₃ N ₄ layer on the back surface, a single-crystal Ga layer having a thickness of 2 μm is formed on the insulating substrate.
A P layer was formed. There was no change in the single crystal GaP layer even by selective etching of the porous Si layer.

As a result of observation of a cross section by a transmission electron microscope, G
No new crystal defects were introduced into the aP layer, and it was confirmed that good crystallinity was maintained.

Example 4 A P-type or N-type 4-inch diameter first (100) single-crystal Si substrate having a thickness of 525 μm and a specific resistance of 0.01 Ω · cm was anodized in an HF solution. Was done.

The anodizing conditions were as follows. Current density: 5 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1 Time: 24 (min) Thickness of porous Si: 20 (μm) Porosity: This substrate was oxidized in an oxygen atmosphere at 400 ° C. for 2 hours. Due to this oxidation, the inner wall of the porous Si hole was covered with the thermal oxide film. Single crystal GaAs on porous Si by MOCVD
Was epitaxially grown by 1 μm.

The surface of the GaAs layer and a separately prepared 500
of the second Si substrate on which a thermal oxide film of
After overlapping and contacting the O ₂ layer surface, anodic bonding was performed at 800 ° C. and bonding was performed. By this heat treatment, both substrates were firmly bonded.

Next, 10 μm of the first Si substrate was removed by polishing and grinding, and thereafter, ethylenediamine + pyrocatechol + water (ratio of 17 ml: 3 g: 8 ml) was heated at 110 ° C. to oxidize the inner wall of the hole. Using a porous Si layer as an etch stop layer, a 10 μm single crystal Si substrate was selectively etched. After 15 minutes, the first Si substrate was completely etched, exposing the porous Si layer.

Then, after removing the oxide film on the inner wall of the porous Si layer with hydrofluoric acid, the porous Si was etched at 110 ° C. with ethylenediamine + pyrocatechol + water (17 ml: 3 g: 8 ml ratio). Two minutes later, the single crystal GaAs remained without being etched, and the porous Si substrate was selectively etched using the single crystal GaAs as an etch stop material, and completely removed.

The etching rate of single crystal GaAs with respect to the etching solution is extremely low, and the film thickness can be practically ignored.

That is, a single-crystal GaAs layer having a thickness of 1 μm was formed on the insulating substrate. There was no change in the single crystal GaAs layer even by selective etching of porous Si.

As a result of observing the cross section with a transmission electron microscope, G
No new crystal defects were introduced in the aAs layer, and it was confirmed that good crystallinity was maintained.

Example 5 A 5-inch diameter first (100) single-crystal Si substrate having a thickness of 625 μm and a specific resistance of 0.01 Ω · cm was anodized in an HF solution. Was done.

The anodizing conditions were as follows. Current density: 5 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1 Time: 12 (min) Thickness of porous Si: 10 (μm) Porosity: This substrate was oxidized at 400 ° C. for 1 hour in an oxygen atmosphere. Due to this oxidation, the inner wall of the porous Si hole was covered with the thermal oxide film. Single-crystal GaAs was epitaxially grown on the porous Si by 0.3 μm by MBE.

Further, a 500 nm SiO ₂ layer was formed on the surface of the epitaxial GaAs layer by the CVD method.

The surface of the SiO ₂ layer and a separately prepared 200
S of the second Si substrate on which the Si ₃ N ₄ film is formed.
After overlapping and contacting the surface of the i ₃ N ₄ layer, 800 ° C.
Were bonded by anodic bonding. As a result, both substrates were firmly bonded.

Next, the first Si substrate was removed by polishing and grinding while leaving a thickness of 5 μm. Thereafter, the porous Si layer whose inner wall of the hole was oxidized with 1HF + 10HNO ₃ + 10CH ₃ COOH was used as an etch stop layer to form a 10 μm single layer. The crystalline Si substrate was selectively etched. After 5 minutes, the entire first Si substrate was etched, exposing the porous Si layer.

Then, after removing the oxide film on the inner wall of the porous Si layer with hydrofluoric acid, the porous Si was etched at 115 ° C. with ethylenediamine + pyrazine + water (ratio of 7.5 ml: 2.4 g: 2.4 ml). One minute later, the single-crystal GaAs remained without being etched, and the porous Si substrate was selectively etched using the single-crystal GaAs as a material for the etch stop, and completely removed.

The etching rate of the single crystal GaAs with respect to the etching solution is extremely low, and the film thickness can be practically ignored.

That is, a single-crystal GaAs layer having a thickness of 1 μm was formed on the insulating substrate. There was no change in the single crystal GaAs layer even by selective etching of porous Si.

As a result of observing the cross section with a transmission electron microscope, G
No new crystal defects were introduced in the aAs layer, and it was confirmed that good crystallinity was maintained.

The present invention is not limited to the above embodiments, but can be applied to all compound semiconductors, and further to an etching solution in which the etching rate of Si with respect to those compound semiconductors is sufficiently high.

[0090]

According to the present invention, in obtaining a compound semiconductor layer having good crystallinity on an insulating substrate, productivity, uniformity,
An excellent method in terms of controllability and economy can be provided.

Further, according to the present invention, it is possible to realize the advantages of the conventional SOI device and propose a method for manufacturing a semiconductor substrate which can be applied.

According to the present invention, a high-quality single-crystal Si substrate is used as a starting material, and a single-crystal layer is left only on the surface, and the lower Si substrate is chemically removed and transferred onto an insulator. In addition, as described in detail in the embodiments, it is possible to perform a large number of processes in a short time, and there is a great improvement in productivity and economy.

According to the present invention, a compound semiconductor single crystal having extremely excellent crystallinity, which is uniform and flat over a large area, is obtained by performing two-step selective etching in which the second-stage selectivity is excellent. be able to.

It is well known that the oxidation of the inner wall of the porous Si has the effect of suppressing the structural change of the porous Si due to the thermal process. There is also an effect of improving the selection ratio.
Selective etching of the first stage bulk Si, since the inner surface of the porous Si is covered with an oxide film, S than SiO ₂
By using an etching solution having a high etching rate of i, the porous Si layer becomes a sufficient etch stop layer.

The region where the porous Si layer is first exposed due to the non-uniform thickness of the porous Si and the unevenness of the first-stage etching waits for the completion of the etching of the bulk Si in other regions. Although the porous Si becomes thinner, the selectivity of the second-stage etching is extremely excellent, so that the unevenness of the remaining thickness of the porous Si can be sufficiently compensated.

According to the present invention, a single crystal compound semiconductor layer having good crystallinity can be formed on porous Si, and this semiconductor layer can be economically transferred onto an insulating substrate having a large area. In addition, it is possible to sufficiently suppress the difference between the lattice constant and the coefficient of thermal expansion and form a compound semiconductor layer having good crystallinity on the insulating substrate.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view for explaining a process of the present invention.

FIG. 2 is a schematic cross-sectional view for explaining a process of the present invention.

FIG. 3 is a schematic cross-sectional view for explaining a process of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 ... Si board | substrate 12 ... Porous Si which formed the oxide film in the inner wall of the hole 13 ... Single-crystal compound semiconductor layer 14 ... Si support substrate 15 ... Insulating layer 16 ... Etching resistance Mask 21: Si substrate 22: Porous Si with oxide film formed on inner wall of hole 23: Single crystal compound semiconductor layer 24: Si support substrate 25: Insulating layer 31: Si Substrate 32: Porous Si with oxide film formed on inner wall of hole 33: Single crystal compound semiconductor layer 34: Si support substrate 35: Insulating layer

Claims (15)

(57) [Claims] 1. A step of making at least a surface layer on the main surface side of a first Si substrate porous, a step of oxidizing inner walls of holes of the porous Si layer, and a step of forming a single crystal compound semiconductor layer on the porous Si layer. Forming a, bonding the single crystal compound semiconductor layer surface and the main surface of the second Si base via an insulating layer,
And after removing the first Si substrate from the bonded substrate,
At least a step of removing the porous Si layer exposed on the surface by etching the porous Si using an etching solution having a high Si etching rate with respect to the single crystal compound semiconductor. A method for manufacturing a semiconductor substrate. 2. A step of making at least a surface layer on the main surface side of the first Si substrate porous, a step of oxidizing inner walls of holes of the porous Si layer, and a step of forming a single crystal compound semiconductor layer on the porous Si layer. Forming a, bonding the single crystal compound semiconductor layer surface and the main surface of the second Si base via an insulating layer,
Until the porous Si layer is exposed on the first Si substrate,
Alternatively, a step of removing by polishing and grinding until partially exposed, a first etching step of etching and removing the remainder of the first Si substrate, and a step of removing the porous Si layer exposed on the surface by the single crystal compound A method for manufacturing a semiconductor substrate, comprising at least a second etching step of removing porous Si by etching the semiconductor with an etching solution having a high Si etching rate. 3. The method for manufacturing a semiconductor substrate according to claim 1, wherein the insulating layer is formed on at least one of a single crystal compound semiconductor layer and a main surface of a second Si substrate. 4. The method according to claim 1, further comprising: depositing Si on the single crystal compound semiconductor layer.
The method for producing a semiconductor substrate according to claim 3, further comprising an O ₂ film. Wherein said Zemmidori material layer formed on the second Si on the substrate, a thermal oxide film walk the method for manufacturing a semiconductor substrate according to claim 3 which is S i ₃ N ₄ film. Wherein said insulating layer comprises a deposited SiO ₂ film on the single crystal compound semiconductor layer, S i ₃ on the second Si substrate
4. The method for producing a semiconductor substrate according to claim 3, wherein the method comprises a N ₄ film. 7. An insulating thin plate is used for the insulating layer.
The method for producing a semiconductor substrate according to claim 1 or 2, wherein the semiconductor substrate is laminated. 8. The bonding step includes anodic bonding, pressing,
The method according to claim 1, wherein the method is performed by heat treatment or a method selected from a combination thereof. 9. The method of manufacturing a semiconductor substrate according to claim 1, wherein the step of making porous is anodization. 10. The method according to claim 9, wherein the anodization is performed in an HF solution. 11. The method according to claim 1, wherein the step of oxidizing the porous Si layer is performed by thermal oxidation. 12. A step of preparing a first Si substrate having a porous layer, a step of forming a single crystal compound semiconductor layer on the porous layer, and forming the first substrate with a second substrate and an insulating layer. And bonding the monocrystalline compound semiconductor layer so as to obtain a multilayer structure located inside, and removing the porous layer from the multilayer structure by etching. A method for manufacturing a semiconductor substrate. 13. The single crystal compound semiconductor layer is made of GaAs.
3. The method according to claim 1, wherein said s, AlGaAs or GaP is used.
13. The method for producing a semiconductor substrate according to any one of the above items 12. 14. A semiconductor substrate manufactured by the manufacturing method according to claim 1. Description: 15. A first substrate and a second substrate each having a porous silicon layer and a single-crystal compound semiconductor layer over a single-crystal silicon region from the single-crystal silicon region side with an insulating layer interposed therebetween. Forming a multilayer structure, and removing the porous silicon layer from the multilayer structure,
A method for manufacturing a semiconductor substrate including the single crystal compound semiconductor layer over the second substrate with the insulating layer interposed therebetween.