JP3112101B2 - Manufacturing method of semiconductor substrate - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor substrate, and more particularly to a method for manufacturing a semiconductor substrate suitable for an electronic device or an integrated circuit formed on a single crystal semiconductor layer on a dielectric isolation or insulator. It is about the method.

[0002]

2. Description of the Related Art The formation of a single-crystal Si semiconductor layer on an insulator is widely known as a silicon-on-insulator (SOI) technology. A device utilizing this SOI technology is not suitable for a bulk Si substrate for fabricating a normal Si circuit. Much research has been done because of its many inaccessible advantages. In other words, by using SOI technology,
1. 1. Easy dielectric separation and high integration. 2. Excellent radiation resistance. 3. Higher speed due to reduced stray capacitance. 4. Well step can be omitted. 5. Latch-up can be prevented. Advantages such as the possibility of a fully depleted field-effect transistor by thinning can be obtained.

[0003] In order to realize many of the above advantages in device characteristics, researches have been made on a method of forming an SOI structure for several decades. The contents are summarized in, for example, the following documents.

Special Issue: "Single-crystal silic
on on non-single-crystal insula-tors "; edited by
GWCullen, Journal of Crystal Growth, volume63, n
o.3, pp429-590 (1983) Also, SOS (silicon on sapphire) formed by heteroepitaxy of Si on a single-crystal sapphire substrate by CVD (chemical vapor deposition) is known. Despite its success as the most mature SOI technology, a large amount of crystal defects due to lattice mismatch between the Si layer and the underlying sapphire substrate, the incorporation of aluminum from the sapphire substrate into the Si layer, and above all, High prices and delays in increasing area have hindered the spread of their applications.

[0005] In recent years, attempts have been made to realize an SOI structure without using a sapphire substrate. This attempt is roughly divided into the following two.

[0006] 1. After the surface of the Si single crystal substrate is oxidized, a window is opened to partially expose the Si substrate, and the Si substrate is epitaxially grown in a lateral direction using the portion as a seed to form a Si single crystal on SiO ₂ (in this case, S on SiO ₂
with the deposition of an i-layer).

[0007] 2. The Si single crystal substrate itself is used as an active layer, and an SiO ₂ layer is formed below the active layer (this method does not involve deposition of a Si layer).

[0008]

As means for realizing the above item 1, a method of directly growing single crystal Si in a lateral direction by CVD, or a method of depositing amorphous Si and subjecting it to a solid phase lateral epitaxial growth by heat treatment A method in which an energy beam such as an electron beam or a laser beam is converged and irradiated to an amorphous or polycrystalline Si layer, and a single crystal is grown on SiO ₂ by melting and recrystallization, or is melted in a band shape by a rod-shaped heater. How to scan an area (Zone
Melting Recrystallization) is known.

Each of these methods has its advantages and disadvantages, but it still has significant problems in controllability, productivity, uniformity, and quality, and none of them has been industrially used yet.

For example, in the CVD method, sacrificial oxidation is required to make a thin film flat, and the solid phase growth method has poor crystallinity.

In the beam annealing method, there is a problem in processing time by convergent beam scanning, and in controllability such as beam overlap and focus adjustment.

[0012] Among them, Zone Melting Recrystallizati
The on method is the most mature and relatively large-scale integrated circuits have been prototyped, but there are still many crystal defects such as sub-grain boundaries remaining, and it has not been possible to create minority carrier devices .

In the above-mentioned method 2 in which the Si substrate is not used as a seed for epitaxial growth, the following 3
There are different methods.

1. An oxide film is formed on a Si single crystal substrate having a V-shaped groove anisotropically etched on the surface, and an oxide film is formed on the oxide film.
After depositing a polycrystalline Si layer as thick as the Si substrate,
By polishing from the surface of the base, a single crystal Si region which is dielectrically separated and surrounded by V-grooves is formed on the thick polycrystalline Si layer.

However, in this method, although the crystallinity is good, a step of depositing polycrystalline Si several hundred microns thick and a step of polishing a single crystal Si substrate from the back surface to leave only a separated Si active layer. However, there is a problem in terms of controllability and productivity.

2. Simox (SIMOX: Seperati
This is a method called on by Ion Implanted Oxygen) for forming a SiO ₂ layer by ion implantation of oxygen into a Si single crystal substrate, and is the most mature method at present because it has good compatibility with the Si process.

However, in order to form an SiO ₂ layer, it is necessary to implant oxygen ions of 10 ¹⁸ ions / cm ² or more, but the implantation time is long and the productivity is not high. Also, the wafer cost is high. Furthermore, many crystal defects remain, and from the industrial point of view, the quality has not yet reached a sufficient level to produce a minority carrier device.

3. A method of forming an SOI structure by dielectric isolation by oxidation of porous Si. This method uses P-type Si
An N-type Si layer is formed on the surface of the single crystal substrate by proton ion implantation (Imai et al., J. Cryst. Growth, vol. 63, 547 (1983)), or is formed in an island shape by epitaxial growth and patterning. After surrounding only the P-type Si substrate by anodizing in an HF solution so as to surround it,
This is a method in which N-type Si islands are dielectrically separated by the enhanced oxidation method.

In the method, the separated Si regions are:
This is determined before the device process, and there is a problem that the degree of freedom in device design may be limited.

In general, on a light-transmitting substrate represented by glass, the deposited thin-film Si layer is amorphous or amorphous due to the disorder of the crystal structure due to the disorder of the substrate. It is only a polycrystalline layer at best, and a high-performance device cannot be manufactured. This is due to the fact that the crystal structure of the base is amorphous, and a simple single-layer layer cannot be obtained simply by depositing a Si layer.

However, the light-transmitting base, which is one of the insulating bases, is important in forming a contact sensor as a light receiving element and a projection type liquid crystal image display device. In order to further increase the density, resolution, and definition of a picture element, a high-performance driving element is required. As a result, it is necessary that the element provided on the light-transmitting substrate be manufactured using a single crystal layer having excellent crystallinity.

Therefore, it is difficult to manufacture a driving element having sufficient performance at present or in the future due to the crystal structure of amorphous Si or polycrystalline Si having many defects.

Therefore, there is a problem that it is difficult to provide an SOI layer having crystallinity comparable to that of a Si wafer on a light-transmitting glass substrate, which is one of the insulating substrates, by using any of the above methods.

Next, the porous S, which is essential for the method of the present invention, is used.
The removal of the i-layer by chemical etching is discussed.

In general, P = (2.33-A) /2.33 (1) is called Porosity, and this value can be changed during anodization and can be expressed as follows.

P = (m 1 −m 2) / (m 1 −m 3) (2) or P = (m 1 −m 2) / ρAt (3) m 1: Total weight before anodization m 2: Total weight after anodization m 3 : Total weight after removing porous Si ρ: Density of single crystal Si A: Porous area t: Thickness of porous Si In many cases, you can't. In this case, equation (2) is valid, but porous Si must be etched to measure m3.

In the above-described epitaxial growth on porous Si, since the porous Si has a structural property, it is possible to alleviate the strain generated during heteroepitaxial growth and suppress the generation of defects. . However, also in this case, it is clear that the Porosity of the porous Si is a very important parameter. Therefore, the above measurement of Porosity is also essential in this case.

The method for etching porous Si is as follows. Etch porous Si with NaOH aqueous solution (G. Bonchil, R. Herino, K. Barla, and JCPfister, J. El.
ectrochem. Soc., vol. 130, no. 7, 1611 (1983)). 2.
It is known to etch porous Si with an etchant capable of etching single-crystal Si.

In the above method 2, an etching solution of hydrofluoric nitric acid is usually used, and the etching process of Si at this time is as follows: Si + 2O → SiO ₂ (4) SiO ₂ +4 HF → Si F ₄ As shown by + H ₂ O (5), Si is oxidized with nitric acid and transformed into SiO ₂ , and the etching of Si proceeds by etching the SiO ₂ with hydrofluoric acid.

As a method of etching crystalline Si,
In addition to the above hydrofluoric / nitric acid-based etchants, there are ethylenediamine-based, KOH-based, hydrazine-based, and the like.

From these facts, in order to selectively etch porous Si, it is necessary to select an etchant capable of etching porous Si other than the above Si etchant. The conventional selective etching of porous Si is only etching using a NaOH aqueous solution as an etching solution.

Further, as described above, although the porous Si is etched by the hydrofluoric-nitric acid-based etchant, there is a problem that the single crystal Si is also etched.

In the conventional method of selectively etching porous Si using an aqueous NaOH solution, it is inevitable that Na ions are adsorbed on the etched surface.

The Na ion is a main cause of impurity contamination, is not only movable but also has an adverse effect such as formation of an interface state, and is a substance which must not be introduced in a semiconductor process. (Object of the Invention) It is an object of the present invention to propose a method of manufacturing a semiconductor substrate which can meet the above-mentioned problems and requirements by using the above-mentioned bonding method.

Further, according to the present invention, a transparent glass substrate (light-transmitting substrate) is provided on a transparent glass substrate (light transmitting substrate).
It is an object of the present invention to propose a method for manufacturing a semiconductor substrate which is excellent in productivity, uniformity, controllability, and cost in obtaining a crystal layer.

Still another object of the present invention is to propose a method of manufacturing a semiconductor substrate which can realize the advantages of the conventional SOI device and can be applied.

The present invention is also applicable to a case where a large-scale integrated circuit having an SOI structure is manufactured, using an expensive SOS or SIMOX.
It is an object of the present invention to propose a method of manufacturing a semiconductor base material which can be substituted for the above.

It is another object of the present invention to provide a method for efficiently and uniformly selectively etching porous Si without adversely affecting a semiconductor process and without etching non-porous Si. It is.

[0039]

According to the present invention, as a means for solving the above problems, a porous single crystal semiconductor layer and a first single crystal semiconductor layer are provided.
A non-porous single-crystal semiconductor layer formed at a temperature of
Preparing a first member, the first member, and a light transmitting member;
A non-porous single crystal semi-conductor
Paste to obtain a multilayer structure with the body layer located inside
Combining, from the multilayer structure, the porous single crystal half
A removing step of removing the conductor layer, and after the removing step,
The non-porous single-crystal semiconductor provided on the second member
A single crystal half-crystal is formed on the layer at a second temperature higher than the first temperature.
Forming a conductive layer by epitaxial growth.
And a method of manufacturing a semiconductor substrate .

The method for epitaxially growing a single crystal semiconductor layer at the second temperature is a CVD method.

Further, the first single crystal semiconductor layer is formed on the porous single crystal semiconductor layer .
The total thickness of the non-porous semiconductor single-crystal layer formed at the temperature of the second temperature and the single-crystal semiconductor layer formed at the second temperature is 1
It is characterized by being less than 00 microns.

Further, the non-porous semiconductor single crystal layer formed at the first temperature is formed by epitaxial growth.

The non-porous semiconductor single crystal layer formed at the first temperature is selected from a bias sputtering method, a molecular beam epitaxial method, a plasma CVD method, a photo CVD method, a liquid phase growth method, and a CVD method. It is characterized by being formed by a method.

Further, the second temperature is not lower than 900 ° C.

Further, the porous single crystal semiconductor layer is removed.
The method is characterized in that, after covering the surface other than the porous single crystal semiconductor with an etching prevention film, an electroless wet chemical etching step is performed.

[0046]

According to the present invention, before performing selective etching,
Non-porous silicon growth temperature on a porous substrate (first
) And the growth temperature (second temperature) of single crystal silicon on non-porous silicon after selective etching, a silicon layer having a good single crystal structure can be formed on the insulator.

Hereinafter, the temperature control of the present invention will be described.

According to observation with a transmission electron microscope, pores having an average diameter of about 600 angstroms are formed in the porous Si layer, and the density thereof is less than half that of single crystal Si. Regardless, single crystallinity is maintained, and it is also possible to epitaxially grow a single crystal Si layer on the porous layer.

However, if the high-temperature treatment is performed at this time, the porous Si may be deteriorated, and the characteristics of the accelerated etching and the like may be changed. Characteristics are impaired. Therefore, the non-porous silicon epitaxial growth of the Si layer on the porous silicon layer needs to be performed at a low temperature.

As such a low-temperature growth method, low-temperature growth such as molecular beam epitaxial growth, plasma CVD, optical CVD, bias sputtering, and liquid phase growth is preferable. It is most preferable that epitaxial growth free of crystal defects can be realized at such a low temperature (T. Ohmi, T. Ichikawa, H. Iw
abuchi, andT.Shibata, J.Appl.Phys.vol.66, pp4756-4
766, 1989).

However, in consideration of device formation, a high-quality single-crystal silicon layer is desired, but the highest-quality single-crystal silicon layer at present is 9
It is formed by a CVD method at a substrate temperature of 00 ° C. or higher.

That is, the device region is preferably a single crystal silicon layer grown at a higher temperature by a CVD method than a single crystal silicon layer grown at a low temperature.

Therefore, low-temperature growth is preferable for growing a single-crystal Si layer on porous silicon, and high-temperature growth is preferable for forming a single-crystal Si layer in a device region. It is preferable that the single crystal is grown in two temperature ranges of two.

Further, according to the present invention, by using a wet chemical etching solution which does not adversely affect the semiconductor process, it is possible to selectively etch porous Si without etching crystalline Si. .

In particular, the method for selectively etching porous Si according to the present invention employs hydrofluoric acid (or buffered hydrofluoric acid, hereinafter abbreviated as BHF) or hydrofluoric acid (or buffered hydrofluoric acid) having no etching effect on crystalline Si. BHF) to which hydrogen peroxide solution has been added, or hydrofluoric acid (or BHF) to which alcohol has been added, or hydrofluoric acid (or BHF)
The object of the present invention can be further achieved by using a mixed solution obtained by adding a hydrogen peroxide solution and an alcohol as a selective etching solution.

The hydrogen peroxide in the selective wet chemical etching solution for porous Si of the present invention acts as an oxidizing agent, and the reaction rate can be controlled by changing the ratio of hydrogen peroxide.

The alcohol in the selective wet chemical etching solution of the porous Si of the present invention acts as a surfactant, instantaneously removes bubbles of the reaction product gas from the etching from the etching surface, and makes the porous silicon uniformly and efficiently. Selective etching of high quality Si becomes possible. According to the present invention, crystalline Si is used by using a solution used in a normal semiconductor process.
The porous Si mixed in the same substrate can be selectively chemically etched.

Further, by etching after covering the surface other than the porous silicon surface to be etched with the etching prevention film, the selectivity of the etching can be improved.

As the etching prevention film, for example,
It can be formed by depositing 0.1 μm of Si ₃ N ₄ by a plasma CVD method, covering the two bonded substrates, and removing only the nitride film on the porous substrate by reactive ion etching.

The same effect can be obtained when the piezo-wax or the electron wax is coated as the etching prevention film, and only the porous Si substrate can be completely removed. [Embodiment Example] An embodiment example of the present invention will be described below with reference to a sectional process diagram of FIG. In FIG. 1, a porous Si substrate was used.
11 and the non-porous silicon single crystal layer 12
First part having semiconductor layer and non-porous single crystal semiconductor layer
Material (FIG. 1 (b)), and the light-transmitting glass substrate 13
A second member made of a light-transmitting substrate, and a porous Si-based
Body 11, non-porous silicon single crystal layer 12, and light-transmitting glass
The substrate 13 is a multilayer structure (FIG. 1C).

First, as shown in FIG. 1A, a Si single crystal substrate 11 is prepared, and the whole is made porous. Si
The substrate is made porous by an anodizing method using an HF solution. This porous Si layer has a density of single crystal Si of 2.
Compared to 33 g / cm ³ , the density was 50
Density 1.1-0.6g / cm by changing to ~ 20%
It can be changed in the range of ³ .

The porous layer used in the present invention is easily formed on a P-type Si substrate for the following reasons.

The porous Si was prepared by Uhlir et al.
It was discovered in the research process of semiconductor electropolishing in 1957 (A. Uhlir, Bell Syst. Tech. J., vol. 35, 333 (195
6)).

In addition, Unagami and the like have
And reported that the anodic reaction of Si in HF solution requires holes, and the reaction is as follows (T. Unakami, J. Electrochem. Soc., vol.127, 476
(1980)).

[0065] Si + 2HF + (2-n ) e + → SiF 2 + 2H + + ne - SiF 2 + 2HF → SiF 4 + H 2 SiF 4 + 2HF → H 2 SiF 6 or, Si + 4HF + (4- λ) e + → SiF 4 + 4H + + λe ^- where _{SiF 4 + 2HF → H 2 SiF} 6, e + , e ^- represent a hole and an electron, respectively. Further, n and λ are the number of holes required for dissolving the Si1 atom, and it is assumed that porous Si is formed when the condition of n> 2 or λ> 4 is satisfied.

From the above, generally, P-type Si having holes is made porous, while N-type Si is not made porous. The selectivity in this porous formation has been demonstrated by Nagano et al. And Imai (Nagano, Nakajima, Yasuno, Onaka, Kajiwara, IEICE Technical Report, vol.79, SSD7
9-9549 (1979)), (K. Imai, Solid-State Electron
ics, vol. 24, 159 (1981)).

The density of the porous layer is reduced to less than half because a large amount of voids are formed inside the porous layer.
As a result, the surface area is dramatically increased as compared with the volume, so that the chemical etching rate is significantly increased as compared with the ordinary etching rate of the single crystal layer.

Next, as shown in FIG. 1B, epitaxial growth is performed on the surface of the porous substrate by various low-temperature growth methods to form a thin nonporous silicon single crystal layer 12 at a first temperature. I do.

The first temperature must be such that the porous Si layer and the non-porous silicon single crystal layer are not deteriorated so that the selective ratio between the porous Si layer and the non-porous silicon single crystal layer by the subsequent selective etching is sufficiently obtained. If there is no crystal defect in the non-porous silicon single crystal layer formed on the porous Si, the temperature is low, and it is good.

Next, as shown in FIG. 1C, a light-transmitting substrate 13 is prepared, and the light-transmitting substrate 13 is attached to the surface of the non-porous silicon single crystal layer 12 on the porous Si substrate 11. Put on.

Thereafter, the entire porous Si substrate 11 is treated with hydrofluoric acid (or buffered hydrofluoric acid, hereinafter abbreviated as BHF), hydrofluoric acid (or BHF) to which a hydrogen peroxide solution is added, or hydrofluoric acid (or BHF). Acid (or BHF) with alcohol, or hydrofluoric acid (or BHF)
A mixture of hydrogen peroxide and alcohol was added to the mixture as a selective etchant, without stirring when alcohol was present, or by infiltrating with stirring when no alcohol was present. Only the Si layer 11 is subjected to electroless wet chemical etching to leave a thin nonporous silicon single crystal layer 12 on the light-transmitting substrate 13 to form it (FIG. 1D).

Next, as shown in FIG. 1E, a high-quality single-crystal silicon layer 14 is formed on the non-porous silicon single-crystal layer 12 by an epitaxial method at a second temperature.
The substrate temperature at this time does not need to be low, but is preferably higher than the first temperature and formed by a CVD method at 900 ° C. or higher.

FIG. 1F shows a semiconductor substrate obtained by the present invention. That is, the single-crystal Si layer 12 + 14 having the same crystallinity as that of the silicon wafer is flattened and uniformly thinned on the light-transmitting substrate 13, and formed over a large area over the entire wafer. The semiconductor substrate thus obtained can be suitably used from the viewpoint of producing an insulated electronic element.

Next, the selective etching method of the present invention in which only porous Si is subjected to electroless wet chemical etching will be described below.

In the present invention, hydrofluoric acid (or buffered hydrofluoric acid, hereinafter abbreviated as BHF), hydrofluoric acid (or BHF) to which hydrogen peroxide is added, or hydrofluoric acid (or BHF) to alcohol Or a mixture of hydrofluoric acid (or BHF) and an aqueous solution of hydrogen peroxide and alcohol is used as a selective etching solution without agitation when alcohol is present. Selective etching is performed by infiltrating with stirring.

FIG. 2 shows that porous Si and single-crystal Si are 49%
4 shows the etching time dependence of the thickness of the etched porous Si and single-crystal Si when infiltrated into a mixed solution of hydrofluoric acid, alcohol and 30% hydrogen peroxide without stirring.

The porous Si is prepared by anodizing single crystal Si and an example of the conditions is shown below.

The porous S formed by anodization
The starting material of i is not limited to single crystal Si, but may be Si having another crystal structure.

Applied voltage: 2.6 (V) Current density: 30 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1 Time: 2.4 ( Time) Thickness of porous Si: 300 (μm) Porosity: 56 (%) The porous Si prepared under the above conditions was removed at room temperature by 49%.
After infiltration into a mixture of 10% hydrofluoric acid, alcohol and 30% hydrogen peroxide solution (10: 6: 50) (open circles) without stirring, a decrease in the thickness of the porous Si was measured.

The porous Si is rapidly etched,
Minutes, 107 μm, and after 80 minutes, 244
μm also had a high degree of surface properties and was uniformly etched. The etching rate depends on the solution concentration and the temperature.

At this time, when the hydrogen peroxide solution is added, the oxidation of silicon can be accelerated and the reaction rate can be increased as compared with the case where no addition is made. By further changing the ratio of the hydrogen peroxide solution, The reaction rate can be controlled.

Further, the non-porous Si having a thickness of 500 μm was stirred at room temperature without mixing in a mixed solution (10: 6: 50) of 49% hydrofluoric acid, alcohol and 30% hydrogen peroxide (black circle). After infiltration, the decrease in thickness of the non-porous silicon was measured.

The non-porous silicon was etched less than 100 angstroms even after 120 minutes had elapsed.

At this time, when alcohol is added, bubbles of the reaction gas generated by the etching can be instantaneously removed from the etching surface without stirring, and the porous Si can be etched uniformly and efficiently. .

Porous Si and Non-porous Si after Etching
Was washed with water and the surface thereof was trace-analyzed with secondary ions. As a result, no impurities were detected.

The conditions of the solution concentration and the temperature were as follows.
The etching rate and the etching selectivity between porous Si and non-porous Si are set within a range that is practically acceptable in a manufacturing process or the like.

FIGS. 3 to 9 show the etching time dependence of the thicknesses of porous Si and single-crystal Si by other etching solutions, respectively. FIG. 3 shows buffered hydrofluoric acid and etching solution as etching solutions. Etching characteristics of porous and non-porous Si when using a mixture of hydrogen peroxide and alcohol.

FIG. 4 shows porous and non-porous Si when a mixed solution of hydrofluoric acid and hydrogen peroxide solution is used as an etching solution.
Etching characteristics.

FIG. 5 shows the etching characteristics of porous and non-porous Si when a mixed solution of hydrofluoric acid and alcohol is used as the etching solution.

FIG. 6 shows the etching characteristics of porous and non-porous Si when hydrofluoric acid is used as an etching solution.

FIG. 7 shows the etching characteristics of porous and non-porous Si when a mixed solution of buffered hydrofluoric acid and alcohol was used as the etching solution.

FIG. 8 shows the etching characteristics of porous and non-porous Si when a mixed solution of buffered hydrofluoric acid and aqueous hydrogen peroxide was used as the etching solution.

FIG. 9 shows the etching characteristics of porous and non-porous Si when buffered hydrofluoric acid is used as an etchant.

Hereinafter, the present invention will be described with reference to specific examples.

[0095]

EXAMPLE 1 First, a P-type (100) single-crystal Si substrate having a thickness of 200 microns was anodized in a 50% HF solution. The current density at this time is
It was 100 mA / cm ² . At this time, the rate of making porous is 8.4 μm / min. The entire P-type (100) Si substrate having a thickness of 200 microns was made porous in 24 minutes.

Next, a non-porous single crystal silicon epitaxial layer was grown at a low temperature of 0.05 μm on the P-type (100) porous Si substrate by bias sputtering. The deposition conditions are as follows.

(Substrate surface cleaning conditions) RF frequency: 100 MHz High frequency power: 5 W Temperature: 380 ° C. Ar gas pressure: 15 × 10 ⁻³ Torr Cleaning time: 5 minutes Target DC bias: −5 V Substrate DC bias: +5 V (deposition conditions) ) RF frequency: 100 MHz High frequency power: 100 W Temperature (first temperature): 380 ° C. Ar gas pressure: 15 × 10 ⁻³ Torr Growth time: 4 minutes Growth film thickness: 0.05 μm Target DC bias: −150 V Substrate DC bias : +10 V Next, a fused quartz glass substrate having the surface of the epitaxial layer optically polished and Si
By superimposing the substrates and heating at 600 ° C. for 0.5 hour in an oxygen atmosphere, both substrates were firmly joined.

Next, 0.1 μm of Si ₃ N ₄ as an etching prevention film was deposited by a plasma CVD method to cover the two bonded substrates, and only the nitride film on the porous substrate was subjected to reactive ion etching. To remove.

Thereafter, the bonded substrates were mixed with a mixture of 49% hydrofluoric acid, alcohol and 30% hydrogen peroxide solution (10:
6:50) and selective etching was performed without stirring.
After 65 minutes, only the non-porous silicon single crystal layer remained without being etched, and the porous Si substrate was selectively etched using single crystal Si as the etch stop material, and completely removed.

The etching rate of the non-porous Si single crystal with respect to the etching solution is extremely low, not more than 50 angstroms even after 65 minutes, and the selectivity with respect to the etching rate of the porous layer reaches more than ten-fiveth power. Etching (several tens of angstroms) in the non-porous layer results in a practically negligible thickness reduction.

That is, the porous Si substrate having a thickness of 200 μm is removed, and after removing the Si ₃ N ₄ layer as an etching prevention film, a 0.05 μm-thick silicon substrate is placed on the fused quartz glass substrate. A thick single-crystal Si layer was formed.

Next, a 1 μm high-quality epitaxial Si single crystal film was deposited on the non-porous silicon single crystal by the ordinary CVD method. The deposition conditions are as follows.

Source gas: SiH ₂ Cl ₂ … 1000 sccm Carrier gas: H ₂ … 230 1 / min Base temperature (second temperature): 1080 ° C. Pressure: 80 Torr Growth time: 2 min Further, Si ₃ N as an etching prevention film The same effect can be obtained when apiesone wax or electron wax is applied instead of the _four layers, and only the porous Si substrate can be completely removed.

As a result of observing the cross section with a transmission electron microscope,
No new crystal defects were introduced into the Si layer formed by the S method and the Si layer formed by the CVD method, and it was confirmed that a SOI structure having a thickness of about 1 μm was formed, which maintained good crystallinity.

On the other hand, there was no difference in hole measurement and other electrical characteristics from those of ordinary bulk silicon. Example 2 First, a P-type (100) single crystal Si substrate having a thickness of 200 microns was anodized in a 50% HF solution. The current density at this time is 100 mA
/ Cm ² . The porosity rate at this time is 8.4 μm.
m / min. The entire P-type (100) Si substrate having a thickness of 200 microns was made porous in 24 minutes.

Next, MBE (Molecular Beam Epitaxy: Molecular) is formed on the P-type (100) porous Si substrate.
A Si epitaxial layer was grown at a low temperature of 0.1 μm by a Beam Epitaxy method. The deposition conditions are
It is as follows.

Temperature (first temperature): 700 ° C. Pressure: 1 × 10 ⁻⁹ Torr Growth rate: 0.1 nm / sec Next, a fused quartz glass substrate optically polished is superposed on the surface of the epitaxial layer. 70 in oxygen atmosphere
By heating at 0 ° C. for 0.5 hour, both substrates
Strongly joined.

Next, 0.1 μm of Si ₃ N ₄ as an etching prevention film was deposited by a plasma CVD method to cover the two bonded substrates, and only the nitride film on the porous substrate was reactive. It was removed by ion etching.

Then, the bonded substrate was treated with BHF (a mixed aqueous solution of 36% ammonium fluoride and 4.5% hydrofluoric acid) in a mixed solution of 49% hydrofluoric acid, alcohol and 30% hydrogen peroxide (10: 6). : 50) and selective etching was performed without stirring. After 205 minutes, only the single-crystal Si layer remains without being etched, and the porous Si substrate is selectively etched using single-crystal Si as an etch stop material,
It has been completely removed.

The etching rate of the non-porous Si single crystal with respect to the etching solution is extremely low, even after 205 minutes.
Angstrom or less, the selectivity with respect to the etching rate of the porous layer reaches more than ten-fiveth power, and the etching amount (several tens of angstroms) of the non-porous layer is a film thickness decrease that can be ignored in practical use.

That is, the porous Si substrate having a thickness of 200 μm is removed, and after removing the Si ₃ N ₄ layer as an etching prevention film, the Si substrate has a thickness of 0.1 μm on SiO _2. A single-crystal Si layer was formed.

Next, a 1 μm high-quality epitaxial Si single crystal film was deposited on the non-porous silicon single crystal by the ordinary CVD method. The deposition conditions are as follows.

Source gas: SiH ₂ Cl ₂ ··· 1000 sccm Carrier gas: H ₂ ··· 230 1 / min Substrate temperature (second temperature): 1080 ° C. Pressure: 80 Torr Growth time: 2 min Further, Si ₃ N as an etching prevention film The same effect can be obtained when apiesone wax or electron wax is applied instead of the _four layers, and only the porous Si substrate can be completely removed.

As a result of observation of a cross section by a transmission electron microscope,
No new crystal defects were introduced into the Si layer formed by the S method and the Si layer formed by the CVD method, and it was confirmed that an SOI structure having a thickness of about 1 μm, in which good crystallinity was maintained, was formed.

On the other hand, there was no difference in hole measurement and other electrical characteristics from those of ordinary bulk silicon.

(Example 3) First, a P-type (100) single-crystal Si substrate having a thickness of 200 μm was immersed in 50% HF.
Anodization was performed in the solution. The current density at this time was 100 mA / cm ² . At this time, the rate of making porous is 8.4 μm / min. The entire P-type (100) Si substrate having a thickness of 200 microns was made porous in 24 minutes.

Next, a Si epitaxial layer was grown at a low temperature of 0.1 μm on the P-type (100) porous Si substrate by a plasma CVD method. The deposition conditions are as follows.

Gas: SiH ₄ High frequency power: 100 W Temperature (first temperature): 800 ° C. Pressure: 1 × 10 ⁻² Torr Growth rate: 2.5 nm / sec Next, the surface of the epitaxial layer is subjected to optical polishing. The fused quartz glass substrates were placed on each other and
By heating at 0 ° C. for 0.5 hour, both substrates
Strongly joined.

Next, 0.1 μm of Si ₃ N ₄ as an etching prevention film was deposited by a plasma CVD method to cover the two bonded substrates, and only the nitride film on the porous substrate was reactive. It was removed by ion etching.

Thereafter, the bonded substrates were selectively etched while being stirred with a mixed solution of 49% hydrofluoric acid and 0% hydrogen peroxide solution (1: 5). After 62 minutes, only the single crystal Si layer remains without being etched, and the single crystal Si is etched.
As a stop material, the porous Si substrate was selectively etched and completely removed.

The etching rate of the non-porous Si single crystal with respect to the etching solution is extremely low, not more than 50 angstroms even after 62 minutes, and the selectivity with the etching rate of the porous layer reaches not less than tenth power, The etching amount (several tens of angstroms) in the non-porous layer is a thickness reduction that can be ignored in practical use.

That is, the porous Si substrate having a thickness of 200 μm is removed, and after removing the Si ₃ N ₄ layer as an etching prevention film, a 0.1 μm-thick silicon substrate is placed on the fused quartz glass substrate. A thick single-crystal Si layer was formed.

Next, a high-quality epitaxial Si single crystal film of 1 μm was deposited on the non-porous silicon single crystal by the ordinary CVD method. The deposition conditions are as follows.

Source gas: SiH ₂ Cl ₂ ··· 1000 sccm Carrier gas: H ₂ ··· 230 1 / min Base temperature (second temperature): 1080 ° C. Pressure: 80 Torr Growth time: 2 min Further, Si ₃ N as an etching prevention film The same effect can be obtained when apiesone wax or electron wax is applied instead of the _four layers, and only the porous Si substrate can be completely removed.

As a result of observing the cross section with a transmission electron microscope,
No new crystal defects were introduced into the Si layer formed by the S method and the Si layer formed by the CVD method, and it was confirmed that an SOI structure having a thickness of about 1 μm, in which good crystallinity was maintained, was formed.

On the other hand, there was no difference in hole measurement and other electrical characteristics from those of ordinary bulk silicon. Example 4 First, a P-type (100) single crystal Si substrate having a thickness of 200 microns was anodized in a 50% HF solution. The current density at this time is 100 mA
/ Cm ² . The porosity rate at this time is 8.4 μm
m / min. The entire P-type (100) Si substrate having a thickness of 200 microns was made porous in 24 minutes.

Next, a 0.5 μm low-temperature Si epitaxial layer was grown on the P-type (100) porous Si substrate by a liquid phase growth method. The deposition conditions are as follows.

Solvent: Sn Growth temperature (first temperature): 900 ° C. Growth atmosphere: H ₂ growth time: 5 minutes Next, the fused quartz glass substrate whose surface of the epitaxial layer is optically polished and the Si substrate are stacked. At the same time, by heating at 900 ° C. for 0.5 hour in a nitrogen atmosphere, both substrates were firmly joined.

Next, 0.1 μm of Si ₃ N ₄ as an etching prevention film was deposited by a plasma CVD method to cover the two bonded substrates, and only the nitride film on the porous substrate was reactive. It was removed by ion etching.

Thereafter, the bonded substrates were selectively etched without stirring with a mixed solution (10: 1) of 49% hydrofluoric acid and alcohol. After 82 minutes, only the single crystal Si layer remains without being etched, and the single crystal Si is etched.
As a stop material, the porous Si substrate was selectively etched and completely removed.

The etching rate of the non-porous Si single crystal with respect to the etching solution is extremely low, not more than 50 angstroms even after 82 minutes, and the selectivity with the etching rate of the porous layer reaches not less than tenth power, The etching amount (several tens of angstroms) in the non-porous layer is a thickness reduction that can be ignored in practical use.

That is, the porous Si substrate having a thickness of 200 μm is removed, and after removing the Si ₃ N ₄ layer as an etching preventing film, a 0.5 μm thick film is formed on the fused quartz glass substrate. Was formed.

Next, a 1 μm high quality epitaxial Si single crystal film was deposited on the non-porous silicon single crystal by the ordinary CVD method. The deposition conditions are as follows.

Source gas: SiH ₂ Cl ₂ ··· 1000 sccm Carrier gas: H ₂ ··· 230 1 / min Substrate temperature (second temperature): 1080 ° C. Pressure: 80 Torr Growth time: 2 min Further, Si ₃ N as an etching prevention film The same effect can be obtained when apiesone wax or electron wax is applied instead of the _four layers, and only the porous Si substrate can be completely removed.

As a result of observation of a cross section by a transmission electron microscope, B
No new crystal defects were introduced into the Si layer formed by the S method and the Si layer formed by the CVD method, and it was confirmed that an SOI structure having a thickness of about 1.5 μm was formed, in which good crystallinity was maintained. Was.

On the other hand, there was no difference in hole measurement and other electrical characteristics from those of ordinary bulk silicon. (Example 5) An n-type (10
0) Anodization was performed on the single crystal Si substrate in a 50% HF solution. The current density at this time is 100 mA / cm
^{Was 2} .

At this time, the rate of making porous is 8.4 μm / m
in. And a 200 micron thick n-type (10
0) The entire Si substrate was made porous in 24 minutes.

Next, a 0.5-inch Si epitaxial layer was formed on the n-type (100) porous Si substrate by low-pressure CVD.
Micron grown at low temperature. The deposition conditions are as follows.

Source gas: SiH ₄ 800 sccm Carrier gas: H ₂ 150 1 / min Temperature (first temperature): 850 ° C. Pressure: 1 × 10 ⁻² Torr Growth rate: 3.3 nm / sec Next, this epitaxial layer An optically polished fused silica glass substrate is superposed on the surface of
By heating at 0 ° C. for 0.5 hour, both substrates
Strongly joined.

Next, 0.1 μm of Si ₃ N ₄ as an etching prevention film was deposited by a plasma CVD method to cover the two bonded substrates, and only the nitride film on the porous substrate was reactive. It was removed by ion etching.

Thereafter, the bonded substrates were selectively etched while stirring with 49% hydrofluoric acid. After 78 minutes,
Only the single crystal Si layer remains without being etched, and the single crystal S
Using i as the etch stop material, the porous Si substrate was selectively etched and completely removed.

The etching rate of the non-porous Si single crystal with respect to the etching solution is extremely low and is not more than 50 angstroms even after 78 minutes, and the selectivity with the etching rate of the porous layer reaches not less than tenth power, The etching amount (several tens of angstroms) in the non-porous layer is a thickness reduction that can be ignored in practical use.

That is, the porous Si substrate having a thickness of 200 μm was removed, and after removing the Si ₃ N ₄ layer as an etching preventing film, a 0.5 μm thick film was formed on the fused quartz glass substrate. Was formed.

Next, a high-quality epitaxial Si single crystal film of 1 μm was deposited on the non-porous silicon single crystal by the ordinary CVD method. The deposition conditions are as follows.

Source gas: SiH ₂ Cl ₂ ··· 1000 sccm Carrier gas: H ₂ ··· 230 1 / min Base temperature (second temperature): 1080 ° C. Pressure: 80 Torr Growth time: 2 min Further, Si ₃ N as an etching prevention film The same effect can be obtained when apiesone wax or electron wax is applied instead of the _four layers, and only the porous Si substrate can be completely removed.

As a result of observing the cross section with a transmission electron microscope,
No new crystal defects were introduced into the Si layer formed by the S method and the Si layer formed by the CVD method, and it was confirmed that an SOI structure having a thickness of about 1.5 μm was formed, in which good crystallinity was maintained. Was.

On the other hand, there was no difference in hole measurement and other electrical characteristics from those of ordinary bulk silicon. (Example 6) P-type (10
0) Anodization was performed on the single crystal Si substrate in a 50% HF solution. The current density at this time is 100 mA / cm
^{Was 2} . The porosity rate at this time is 8.4 μm / m
in. And a P-type (10
0) The entire Si substrate was made porous in 24 minutes.

Next, a non-porous single-crystal silicon epitaxial layer was grown at a low temperature of 0.05 μm on the P-type (100) porous Si substrate by bias sputtering.
The deposition conditions are as follows. (Substrate surface cleaning conditions) RF frequency: 100 MHz High frequency power: 5 W Temperature: 380 ° C. Ar gas pressure: 15 × 10 ⁻³ Torr Cleaning time: 5 minutes Target DC bias: −5 V Substrate DC bias: +5 V (deposition conditions) RF frequency : 100 MHz High frequency power: 100 W Temperature (first temperature): 380 ° C. Ar gas pressure: 15 × 10 ⁻³ Torr Growth time: 4 minutes Growth film thickness: 0.05 μm Target DC bias: -150 V Substrate DC bias: +10 V Next Then, an optically polished fused silica glass substrate and a Si substrate are superimposed on the surface of the epitaxial layer, and heated at 600 ° C. for 0.5 hour in an oxygen atmosphere, whereby the two substrates are firmly joined. Was.

Next, 0.1 μm of Si ₃ N ₄ as an etching prevention film was deposited by a plasma CVD method to cover the two bonded substrates, and only the nitride film on the porous substrate was subjected to reactive ion etching. Removed by

Thereafter, the bonded substrates were selected without mixing with a mixed solution (10: 1) of buffered hydrofluoric acid (a mixed aqueous solution of 36% ammonium fluoride and 4.5% hydrofluoric acid) and alcohol. Etched. After 275 minutes,
Only the non-porous silicon single crystal layer remained without being etched, and the porous Si substrate was selectively etched using single crystal Si as the etch stop material, and completely removed.

The etching rate of the non-porous Si single crystal with respect to the etching solution was extremely low, and even after 275 minutes.
Angstrom or less, the selectivity with respect to the etching rate of the porous layer reaches more than ten-fiveth power, and the etching amount (several tens of angstroms) of the non-porous layer is a film thickness decrease that can be ignored in practical use.

That is, the porous Si substrate having a thickness of 200 μm is removed, and after removing the Si ₃ N ₄ layer as an etching preventing film, a 0.05 μm thick film is formed on the fused quartz glass substrate. Was formed.

Next, a high-quality epitaxial Si single crystal film of 1 μm was deposited on the non-porous silicon single crystal by the ordinary CVD method. The deposition conditions are as follows.

Source gas: SiH ₂ Cl ₂ ··· 1000 sccm Carrier gas: H ₂ ··· 230 / min Base temperature (second temperature): 1080 ° C. Pressure: 80 Torr Growth time: 2 min Further, Si ₃ N as an etching prevention film The same effect can be obtained when apiesone wax or electron wax is applied instead of the _four layers, and only the porous Si substrate can be completely removed.

As a result of observation of a cross section by a transmission electron microscope, B
No new crystal defects were introduced into the Si layer formed by the S method and the Si layer formed by the CVD method, and it was confirmed that an SOI structure having a thickness of about 1 μm, in which good crystallinity was maintained, was formed.

On the other hand, there was no difference in hole measurement and other electrical characteristics from those of ordinary bulk silicon. (Example 7) P-type (10
0) Anodization was performed on the single crystal Si substrate in a 50% HF solution. The current density at this time is 100 mA / cm
^{Was 2} . The porosity rate at this time is 8.4 μm / m
in. And a P-type (1
00) The entire Si substrate was made porous in 24 minutes.

Next, a non-porous single-crystal silicon epitaxial layer was grown at a low temperature of 0.05 μm on the P-type (100) porous Si substrate by bias sputtering.
The deposition conditions are as follows. (Substrate surface cleaning conditions) RF frequency: 100 MHz High frequency power: 5 W Temperature: 380 ° C. Ar gas pressure: 15 × 10 ⁻³ Torr Cleaning time: 5 minutes Target DC bias: −5 V Substrate DC bias: +5 V (deposition conditions) RF frequency : 100 MHz High frequency power: 100 W Temperature (first temperature): 380 ° C. Ar gas pressure: 15 × 10 ⁻³ Torr Growth time: 4 minutes Growth film thickness: 0.05 μm Target DC bias: -150 V Substrate DC bias: +10 V Next Then, a fused silica glass substrate having the surface of the epitaxial layer optically polished and a Si substrate were overlaid and heated at 600 ° C. for 0.5 hour in an oxygen atmosphere, whereby the two substrates were firmly joined. .

Next, 0.1 μm of Si ₃ N ₄ as an etching prevention film was deposited by a plasma CVD method to cover the two bonded substrates, and only the nitride film on the porous substrate was subjected to reactive ion etching. Removed by

Thereafter, the bonded substrates were mixed with a mixed solution of buffered hydrofluoric acid (a mixed aqueous solution of 36% ammonium fluoride and 4.5% hydrofluoric acid) and a 30% aqueous hydrogen peroxide solution (1: 1).
Selective etching was performed while stirring in 5). After 190 minutes, only the non-porous silicon single-crystal layer remained without being etched, and the porous Si substrate was selectively etched using single-crystal Si as an etch stop material, and completely removed.

The etching rate of the non-porous Si single crystal with respect to the etching solution is extremely low, even after 190 minutes.
Angstrom or less, the selectivity with respect to the etching rate of the porous layer reaches more than ten-fiveth power, and the etching amount (several tens of angstroms) of the non-porous layer is a film thickness decrease that can be ignored in practical use.

That is, the porous Si substrate having a thickness of 200 μm was removed, and after removing the Si ₃ N ₄ layer as an etching preventing film, a 0.05 μm-thick silicon substrate was placed on the fused quartz glass substrate. A thick single-crystal Si layer was formed.

Next, a 1 μm high-quality epitaxial Si single crystal film was deposited on the non-porous silicon single crystal by the ordinary CVD method. The deposition conditions are as follows.

Source gas: SiH ₂ Cl ₂ １０００1000 sccm Carrier gas: H ₂ 230 1 / min Base temperature (second temperature): 1080 ° C. Pressure: 80 Torr Growth time: 2 min Further, Si ₃ N as an etching prevention film The same effect can be obtained when apiesone wax or electron wax is applied instead of the _four layers, and only the porous Si substrate can be completely removed.

As a result of observing the cross section with a transmission electron microscope,
No new crystal defects were introduced into the Si layer formed by the S method and the Si layer formed by the CVD method, and it was confirmed that a SOI structure having a thickness of about 1 μm was formed, which maintained good crystallinity.

On the other hand, there was no difference in hole measurement and other electrical characteristics from those of ordinary bulk silicon. (Example 8) A P-type (10
0) Anodization was performed on the single crystal Si substrate in a 50% HF solution. The current density at this time is 100 mA / cm
^{Was 2} . The porosity rate at this time is 8.4 μm / m
in. And a P-type (1
00) The entire Si substrate was made porous in 24 minutes.

Next, a non-porous single crystal silicon epitaxial layer was grown at a low temperature of 0.05 μm on the P-type (100) porous Si substrate by bias sputtering. The deposition conditions are as follows. (Substrate surface cleaning conditions) RF frequency: 100 MHz High frequency power: 5 W Temperature: 380 ° C. Ar gas pressure: 15 × 10 ⁻³ Torr Cleaning time: 5 minutes Target DC bias: −5 V Substrate DC bias: +5 V (deposition conditions) RF frequency : 100 MHz High frequency power: 100 W Temperature (first temperature): 380 ° C. Ar gas pressure: 15 × 10 ⁻³ Torr Growth time: 4 minutes Growth film thickness: 0.05 μm Target DC bias: -150 V Substrate DC bias: +10 V Next Then, a fused silica glass substrate having the surface of the epitaxial layer optically polished and a Si substrate were overlaid and heated at 600 ° C. for 0.5 hour in an oxygen atmosphere, whereby the two substrates were firmly joined. .

Then, 0.1 μm of Si ₃ N ₄ as an etching prevention film was deposited by plasma CVD, and the two bonded substrates were covered, and only the nitride film on the porous substrate was subjected to reactive ion etching. Therefore, it was removed.

Thereafter, the bonded substrates were selectively etched with buffered hydrofluoric acid (a mixed aqueous solution of 36% ammonium fluoride and 4.5% hydrofluoric acid) with stirring. 25
After 8 minutes, only the non-porous silicon single crystal layer was left without being etched, and the porous Si substrate was selectively etched using single crystal Si as an etch stop material, and completely removed.

The etching rate of the non-porous Si single crystal with respect to the etching solution was extremely low, even after 258 minutes.
Angstrom or less, the selectivity with respect to the etching rate of the porous layer reaches more than ten-fiveth power, and the etching amount (several tens of angstroms) of the non-porous layer is a film thickness decrease that can be ignored in practical use.

That is, the porous Si substrate having a thickness of 200 μm was removed, and after removing the Si ₃ N ₄ layer as the etching prevention film, a 0.05 μm-thick silicon substrate was placed on the fused quartz glass substrate. A thick single-crystal Si layer was formed.

Next, a high-quality epitaxial Si single crystal film of 1 μm was deposited on the non-porous silicon single crystal by the ordinary CVD method. The deposition conditions are as follows.

Source gas: SiH ₂ Cl ₂ ··· 1000 sccm Carrier gas: H ₂ ··· 230 1 / min Base temperature (second temperature): 1080 ° C. Pressure: 80 Torr Growth time: 2 min Further, Si ₃ N as an etching prevention film The same effect can be obtained when apiesone wax or electron wax is applied instead of the _four layers, and only the porous Si substrate can be completely removed.

As a result of observing the cross section with a transmission electron microscope, B
No new crystal defects were introduced into the Si layer formed by the S method and the Si layer formed by the CVD method, and it was confirmed that an SOI structure having a thickness of about 1 μm, in which good crystallinity was maintained, was formed.

On the other hand, there was no difference in hole measurement and other electrical characteristics from those of ordinary bulk silicon.

[0175]

As described in detail above, according to the present invention,
S with excellent crystallinity on a light transmitting substrate as good as a single crystal wafer
In obtaining the i-crystal layer, there is an effect that an excellent method can be obtained in terms of productivity, uniformity, controllability, and economy.

Further, according to the present invention, it is possible to realize the advantages of the conventional SOI device and propose a method of manufacturing a semiconductor substrate which can be applied.

According to the present invention, even when a large-scale integrated circuit having an SOI structure is manufactured, an expensive SOS or SIM is required.
It is possible to propose a method for manufacturing a semiconductor base material that can be substituted for OX.

Further, according to the present invention, in the etching of porous Si, a wet chemical etching solution having no adverse effect on the semiconductor process can be used, and the etching of porous Si and non-porous Si can be performed. The selectivity is 5 digits or more, and a great effect can be obtained on controllability and productivity.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view for explaining a process of the present invention.

FIG. 2 shows porous and non-porous Si when a mixed solution of hydrofluoric acid, hydrogen peroxide and alcohol is used as an etching solution.
Etching characteristics.

FIG. 3 shows etching characteristics of porous and non-porous Si when a mixed solution of buffered hydrofluoric acid, hydrogen peroxide solution, and alcohol is used as an etching solution.

FIG. 4 shows etching characteristics of porous and non-porous Si when a mixed solution of hydrofluoric acid and aqueous hydrogen peroxide is used as an etching solution.

FIG. 5 shows etching characteristics of porous and non-porous Si when a mixed solution of hydrofluoric acid and alcohol is used as an etching solution.

FIG. 6 shows etching characteristics of porous and non-porous Si when hydrofluoric acid is used as an etching solution.

FIG. 7 shows the etching characteristics of porous and non-porous Si when a mixed solution of buffered hydrofluoric acid and alcohol is used as an etching solution.

FIG. 8 shows porous and non-porous Si when a mixed solution of buffered hydrofluoric acid and hydrogen peroxide solution is used as an etching solution.
Etching characteristics.

FIG. 9 shows etching characteristics of porous and non-porous Si when buffered hydrofluoric acid is used as an etching solution.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Porous Si base 12 Non-porous silicon single crystal layer 13 Light transmissive glass base 14 Epitaxial Si single crystal layer

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-55-55568 (JP, A) Patent 2608351 (JP, B2) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 27/12 H01L 21/02 H01L 21/762

Claims (9)

(57) [Claims] 1. A method for forming a porous single crystal semiconductor layer at a first temperature.
A first member having the formed non-porous single-crystal semiconductor layer.
A step of preparing, the first member, and a second member made of a light-transmitting substrate.
A multilayer in which the non-porous single-crystal semiconductor layer is located inside.
Laminating so as to obtain a structure, removing the porous single crystal semiconductor layer from the multilayer structure
Removing step, and after the removing step, provided on the second member.
On the non-porous single crystal semiconductor layer, the first temperature
Epitaxial growth of single crystal semiconductor layer at high second temperature
Forming a semiconductor by using
How to make a substrate. 2. The method according to claim 1, wherein the method for epitaxially growing the single crystal semiconductor layer at the second temperature is a CVD method. 3. The non-porous semiconductor single crystal layer formed at a first temperature on the porous single crystal semiconductor layer and the second single crystal semiconductor layer .
The total thickness of the single crystal semiconductor layer formed at the temperature of 100
The method for producing a semiconductor substrate according to claim 1, wherein the size is less than or equal to one micron. 4. A non-porous half formed at said first temperature.
The method according to claim 1, wherein the conductor single crystal layer is formed by epitaxial growth. 5. The non-porous half formed at said first temperature.
2. The semiconductor substrate according to claim 1, wherein the conductor single crystal layer is formed by a method selected from a bias sputtering method, a molecular beam epitaxial method, a plasma CVD method, a photo CVD method, a liquid phase growth method, and a CVD method. Method. 6. The method according to claim 1, wherein the second temperature is 900 ° C. or higher. 7. The method according to claim 7, wherein the porous single crystal semiconductor layer is formed by anodization.
The method for producing a semiconductor substrate according to claim 1, which is obtained by a step including : 8. The method according to claim 7, wherein the anodization is performed in an HF solution. 9. A process for removing said porous single crystal semiconductor layer.
2. The method according to claim 1 , wherein, after covering the surface other than the porous single crystal semiconductor with an etching prevention film, an electroless wet chemical etching step is performed.