JP3234318B2 - Video signal processing circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video for writing and reading a digital video signal having an m-bit width to a memory capable of inputting data having an n-bit width (where m> n), and returning it to an original m-bit signal. The present invention relates to a signal processing circuit.

[0002]

2. Description of the Related Art In order to perform a so-called picture-in-picture in which a different channel content can be displayed on a part of a screen (small screen) of a TV receiver, a video signal of the small screen is first transmitted.
It is necessary to store one field or one frame in the memory. In this case, the video signal of the small screen is A / D
(Analog / Digital) conversion and conversion into an m-bit digital signal, and then store in a field memory. If the data input of this field memory is m bits, it can be transmitted as it is, but it may be different. In this case, the m-bit signal must be converted into a number of bits that match the input of the memory.

FIG. 2 shows a video signal processing circuit having such a function of converting the number of bits. An A / D converter (1) converts an input signal into a 6-bit digital signal, The RAM (2) fetches a 4-bit digital signal in parallel. The linear video signal from the input terminal (3) is converted into a 6-bit digital video signal by the A / D converter (1). The sampling signal to the A / D converter (1) is supplied from a PLL circuit (4) synchronized with a synchronization signal of the video signal. PL
The L circuit (4) also generates a timing signal for controlling the timing of the entire circuit of FIG. The arithmetic circuit (5), the first and second line memories (6) and (7), and the first and second selection circuits (8) and (9) constitute a filter in the vertical direction of the image. For example, the filter is 3H (H is one horizontal synchronizing signal period)
Is averaged and converted into a 1H signal to reduce the number of horizontal lines to 1/3.

Now, the first selection circuit (8) selects the output signal of the first line memory (6), and the second selection circuit (9) selects the output signal of the second line memory (7). And The first and second line memories (6) and (7)
It stores video signals for H and has 6 parallel inputs.
The bit data is held in 256 stages. In this case, the arithmetic circuit (5), the first line memory (6), and the first
The selection circuit (8) forms a loop, applies the 1H data stored in the first line memory (6) to the arithmetic circuit (5) via the first selection circuit (8), and performs the next 1H operation. Add the minute data at a certain ratio. The added data is sequentially applied to the first line memory (6), and when 1H is accumulated in the first line memory (6), the loop-back is performed again in the same manner as described above. As a result, the data of the 3H period is compressed into the 1H period in the first line memory (6), and the averaged data is accumulated.

On the other hand, the second line memory (7) forms a loop together with the operation circuit (5) and the first selection circuit (8), and has already performed the above-mentioned operations, so that the compressed and averaged data has already been obtained. have. Therefore, during the operation period of the first line memory (6), the second line memory (7) applies its output to the 6-bit parallel shift register (10) via the second selection circuit (9). The 6-bit parallel shift register (10) has a four-stage configuration. If the first input is (a ₁ , b ₁ , c ₁ , d ₁ , e ₁ , f ₁ ), the fourth input is (a ₄ , b ₄ , c ₄ , d ₄ , e ₄ , f ₄ ) and are stored sequentially as shown. When the 6-bit parallel shift register (10) takes in all the data of the four stages, the four outputs (f ₁ , f ₂ , f ₃ , f ₄ ) on the most LSB side
In parallel with a 4-bit parallel shift register (11)
Is applied. Next, the four outputs (e ₁ , e ₂ , e ₃ , e ₄ ) which are the _second closest to the LSB side are applied to the 4-bit parallel shift register (11).
The signal is applied to the 4-bit parallel shift register (11) from the bit parallel shift register (10).

As a result, 4-bit data can be transferred from the 4-bit parallel shift register (11) to the video RAM (2). When reading data from the video RAM (2), the 6-bit parallel shift register (1
0) and the operation reverse to the operation of the 4-bit parallel shift register (11), and after returning from 4 bits to the original 6 bits, output.

Therefore, according to the circuit of FIG. 2, bit conversion can be performed.

[0008]

However, the circuit of FIG. 2 has a problem that many flip-flops are required only for bit conversion. That is, the 6-bit parallel shift register (10) of FIG. 2 requires 6 × 4 = 24 stages of D-FFs (D-type flip-flops), and the same number of 4-bit parallel shift registers (11). There is a problem that a total of 48 D-FFs are required. In addition, since all of these D-FFs operate based on the clock from the PLL circuit (4), there is a problem that many clocks are required and the circuit design becomes complicated.

[0009]

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and is intended to convert a digital video signal having a width of m bits into n.
(Where m> n) a video signal processing circuit for storing in a memory capable of inputting data having a bit width, wherein
A parallel shift register that stores a digital video signal of a bit width by a plurality of flip-flops, and (mn) -bit data that is an output of the last flip-flop of the parallel shift register is stored in the first stage of the parallel shift register. Means for applying to the (m-n) input terminals of the flip-flop, and (m-n) -bit data of the middle-stage flip-flop of the parallel shift register to (m-n) of the first-stage flip-flop of the parallel shift register. means for applying to n) input terminals, and means for applying data of n-bit width of the last flip-flop of the parallel shift register to the memory.

[0010]

According to the present invention, a 1H line memory for a vertical filter is used, and data having the same number of bits as the number of input bits of the video memory is extracted from the line memory.

[0011]

FIG. 1 is a block diagram showing an embodiment of the present invention. FIG.
A first line memory that operates as a parallel shift register having a width of 6 bits and a length of 256 stages and operating as a parallel shift register having a length of 4 bits and a length of 384 stages when outputting fetched data. This is a second line memory having the same configuration and operation as the first line memory (12).

In FIG. 1, the same circuit elements as those in FIG. 2 are denoted by the same reference numerals, and description thereof will be omitted. As for the first and second line memories (12) and (13), if one of them is operating, the other is outputting data, and this relationship is the same as FIG. FIG. 1 shows a case where the first line memory (12) is performing an arithmetic operation and the second line memory (13) is outputting data.

The second line memory (13) generates 4-bit MSB-side data of the last stage (256th stage) in response to the timing signal from the PLL circuit (4), and outputs the data via the selection circuit (9). Apply to video RAM (2). The M
Simultaneously with the transfer of the 4-bit data on the SB side, the 2-bit data on the LSB side of the final stage data and the 2-bit data on the LSB side of the middle stage (128th stage) data are transferred to the first stage at 6 bits.
The bits are sequentially stored in the four terminals on the MSB side of the D-FF. Then, the second line memory (13) becomes a parallel shift register substantially having a width of 4 bits and a length of 384 steps, and stores all data for one line in the video RAM (2) in a 4-bit format. be able to.

The image data of the child screen stored in the video RAM (2) has an irregular data writing order due to conversion into 4 bits at the time of writing. Therefore, at the time of reading from the video RAM (2), one line is once again stored in the line memory so that the data can be demodulated and then returned to 6 bits. Video RAM
The data transfer from (2) to the third line memory (14) and the D / A converter (15) is performed by the clock from the PLL circuit (16) locked to the synchronization signal in the video signal of the main screen. It is. The third line memory (14) is for adjusting the slow read speed of the video RAM (2) to the fast speed required to display an actual TV screen at a real speed. It exists. The image of the child screen is usually a part of the image of the parent screen, and the generation period of the child image signal is 1H of the parent.
For example, 1/3 of the period. Therefore, the child data is stored in the third line memory (14) using the clock of the video RAM (2) using the parent's 2H / 3 period, and the fast clock is used using the remaining H / 3 period of the parent. (Real speed)
Output. Therefore, unlike the case of writing, the line memory only needs to be the third line memory (14).

As shown in FIG. 3A, the third line memory constitutes a parallel shift register having a width of 4 bits and a length of 384 stages. Therefore, the 4-bit data from the video RAM (2) is used as it is in the third line memory (1).
4) can be applied. And a third line memory (14)
At the time of data reading, as shown in FIG. 3B, the MSB of the 128th stage corresponding to the LSB side 2 bits of the 4-bit data together with the 4-bit data of the final stage (384th stage)
2 bits of data are simultaneously read. Simultaneously with the start of the data transfer, the 128-bit LSB side 2-bit data is sequentially applied to the first-stage MSB side 2-bit D-FF. As a result, data having a width of 6 bits and a length of 256 stages is output from the third line memory (14), and it is clear that the original data has been returned.

FIG. 4 is a specific circuit diagram of the first and second line memories (12) and (13) of FIG.
6-bit data from the arithmetic circuit (5) is applied to 7) to (23). An "H" level signal is applied to the control terminal (23) when the line memory is performing an operation, and an "L" level signal is applied when the line memory is outputting. The parallel shift register switches between a 6-bit width input state and a 4-bit width output state according to a control signal from the control terminal (23).

In the embodiment shown in FIG. 1, a case where 6-bit width data is converted to 4-bit width data has been described. However, the present invention is not limited to this.
Bit-width data can be converted to any n-bit (where m> n) width. Further, in this embodiment, 4-bit data is extracted from the MSB side of the 6-bit data. However, the data may be extracted from the LSB side, at the center or both sides, or at any position. .

[0018]

As described above, according to the present invention, a digital signal having an m-bit width is written into a memory capable of inputting data having an n-bit width (where m> n), read out, and read out. It can be converted back to a digital signal. In particular, according to the present invention, since the conversion of the bit width can be performed using the 1H line memory arranged before and after the video RAM, there is an advantage that the number of elements and the clock are hardly increased.

[Brief description of the drawings]

FIG. 1 is a block diagram of a video signal processing circuit of the present invention.

FIG. 2 is a block diagram of a conventional video signal processing circuit.

FIG. 3 is a block diagram for explaining FIG. 1;

FIG. 4 is a specific circuit diagram of the line memory of FIG. 1;

[Explanation of symbols]

 (2) Video RAM (12) First line memory (13) Second line memory

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 5/45 H04N 5/265 H04N 5/907

Claims (3)

(57) [Claims] 1. An m-bit wide digital video signal is represented by n
(Where m> n) a video signal processing circuit for storing in a memory capable of inputting data of bit width, wherein the digital video signal of m bit width is stored in a plurality of stages of flip-flops and a first output M-bit wide
A digital video signal is output, and in the second output state, n
A digital video signal that forms part of the digital video signal
A first parallel shift register for outputting Tal signal, a flip-flop output of the last stage of the first parallel shift register (m-n) n bit width of the first parallel shift register data bit of the digital output signal
First stage flip-flop that constitutes the bit that generates
First means for applying to some input terminals of the first parallel shift register from the first stage to the last stage.
(M−n).
Bit data of the first parallel shift register
Configures bits to generate bit-width digital output signals
The remaining input terminals of said first stage flip-flop
A second means for applying to the child, the video signal processing circuit for the data of n-bit width of the flip-flop of the last stage of the first parallel shift register, characterized in that it comprises a third means for applying to said memory. 2. An m-bit-wide digital video signal is represented by n
(Where m> n) a video signal processing circuit for storing in a memory capable of inputting data of bit width, wherein the digital video signal of m bit width is stored in a plurality of stages of flip-flops and a first output M-bit wide
A digital video signal is output, and in the second output state, n
A digital video signal that forms part of the digital video signal
A first parallel shift register for outputting Tal signal, the LSB side output of the flip-flop at the last stage of the first parallel shift register (m-n) of the n-bit width of the first parallel shift register data bit Digital
Of the first stage that constitute the bit that generates the
First applied to some input terminals on the MSB side of the flop
Means, from the first stage to the last stage of the first parallel shift register
(M−n).
Bit data of the first parallel shift register
Configures bits to generate bit-width digital output signals
The remaining input terminals of said first stage flip-flop
A second means for applying the data to the memory, and a third means for applying to the memory n-bit wide data which is the MSB side output of the last flip-flop of the first parallel shift register. Signal processing circuit. 3. A n and second parallel shift register for storing a data bit width in a plurality of stages of flip-flops, n-bit data which is the output of the flip-flop at the last stage of the second parallel shift registers from said memory And the second parallel
The output of the flip-flop that makes up the shift register
A part of the m-bit wide digital video signal
To have (m-n) a video signal processing circuit according to claim 1, characterized in that the fourth means obtaining Bei <br/> for generating a bit data at the same time as m-bit digital video signal.