JP3202846B2 - Image processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus used for broadcasting television signals and video signals and the like, and more particularly to an overall structure of the apparatus and an image processing circuit.

[0002]

2. Description of the Related Art An operation often used in image processing is a product-sum operation. Further, in the moving image processing, two frames (a frame is one frame included between vertical synchronizing signals of a video signal).
In many cases, data between the sections is compared, and a product-sum operation is performed on the result. For example, a product-sum operation is performed in a discrete cosine transform (DCT) used for calculating a frequency spectrum with respect to an inter-frame difference value.

Conventionally, as a technique in such a field, there is a technique described in the following document, for example. Document: Japanese Patent Application Laid-Open No. 4-252385 The above document describes an image processing apparatus for performing high-speed operations required for image processing with one pipeline.

FIG. 2 is a schematic block diagram showing an example of a configuration of a conventional image processing apparatus described in the above document. This image processing apparatus includes one image processing operation circuit, and the image processing operation circuit includes a pre-stage operation unit 1, a selector 2, a register 3, a register 4, a multiplier 5, a register 6, and an adder 7
And a register 8. The pre-stage arithmetic unit 1 is a circuit that includes an adder, a subtractor, and an absolute value circuit, receives the first image data IN1 and the second image data IN2, and calculates, for example, a difference and its absolute value. is there. The selector 2 is a circuit that selects and outputs one of the second image data IN2 and the output signal of the preceding-stage arithmetic unit 1. The register 3 connected to the preceding stage computing unit 1 is a circuit for storing the output signal of the preceding stage computing unit 1. Selector 2
Is a circuit for storing the output signal of the selector 2. A multiplier 5 is connected to the registers 3 and 4. The multiplier 5 is a circuit that performs multiplication by inputting the output signals of the registers 3 and 4. The multiplier 5 is connected to the register 6. The register 6 is a circuit that stores an output signal of the multiplier 5. The adder 7 connected to the register 6 is a circuit that adds the output signal of the register 6 and the output signal OUT1. The register 8 connected to the adder 7 is a circuit that stores the output signal of the adder 7 and outputs the output signal OUT1. Next, the operation of the image processing apparatus will be described. For example,

(Equation 1) When the first image data IN1 and the second image data IN2 are input to the preceding stage arithmetic unit 1,
The pre-stage operation unit 1 performs a comparison operation on the first image data IN1 and the second image data IN2, and outputs an output signal thereof, for example, a
0 is input to the selector 2 and the register 3. Selector 2
Selects one of the second image data IN2 and the output signal of the preceding-stage arithmetic unit 1 and inputs the selected signal to the register 4. The multiplier 5 inputs the output signal a0 of the register 3 and the output signal of the register 4, for example, the multiplication result a0 · b0 of b0 to the register 6. The adder 7 outputs the output signal a of the register 6
0 · b0 and the output signal OUT1 of the image processing apparatus are added and input to the register 8. Output signal OU from register 8
T1 (= Σai · bi, i = 0, 1, 2, 3...) Is output.

Using the above image processing apparatus, ΔA
(A ± b), ΣA | a ± b |, Σ (a ± b) ² , Σ | a
± b | ² (where A is a coefficient, a and b are parameters) and the like, which is repeatedly performed in image processing, can be freely switched by programmably switching the operation parameters of this image processing operation circuit using a microcomputer or the like. Can be changed to In addition, because of the single pipeline configuration, high-speed operations can be performed smoothly. However, when an image having a large amount of data, such as a moving image, is to be processed, the image processing operation circuit is required to perform an image processing operation in real time on a moving image input continuously in a time series. The processing speed is often insufficient with only one. Therefore, a method of operating a plurality of image processing operation circuits simultaneously to increase the processing speed has been performed. FIG. 3 is a block diagram showing a configuration example of another conventional image processing device when four image processing operation circuits shown in FIG. 2 are used. This image processing apparatus includes a plurality of first image data sets IN10 to IN1.
3 and a plurality of second image data IN20 to IN23 to input and perform arithmetic processing. The image processing operation circuits 10-0 to 10-3 are connected to the result storage memories 11-0 to 11-3, respectively. The result storage memories 11-0 to 11-3 store the image processing operation circuits 10-0 to 10-1.
This is a memory for inputting and storing output signals 0-3. Each of the result storage memories 11-0 to 11-3 includes a selector 1
2-0 to 12-3. Selector 12-0
To 12-3, the output signals of the result storage memories 11-0 to 11-3 are programmably selected by using a microcomputer or the like, and the image processing operation circuits 10-0 to 10-3 are selected.
This is a circuit to input to.

Next, the operation of the image processing apparatus will be described. The plurality of first image data IN10 to IN13 and the plurality of second image data IN20 to IN23 are input to the image processing arithmetic circuits 10-0 to 10-3, respectively. For example, dividing image data into blocks of equal size,
This is performed by a method in which image data of blocks obtained by dividing blocks in different areas are input simultaneously, or image data of different lines are input simultaneously. In the image processing arithmetic circuits 10-0 to 10-3, image processing arithmetic corresponding to predetermined parameter settings is performed. The calculation results are output at the same time and written to the result storage memories 11-0 to 11-3. Output signals of the result storage memories 11-0 to 11-3 are programmably selected by selectors 12-0 to 12-3 using a microcomputer or the like, and input to the image processing operation circuits 10-0 to 10-3. . By repeating the above operation, a plurality of image processing apparatuses can be operated in parallel to increase the processing speed.

[0007]

However, the image processing apparatus shown in FIG. 3 has the following problems. Image processing operation circuits 10-0 to 10-3 and result storage memory 11-0
To 11-3 correspond one-to-one. Therefore, when an operation result of a certain image processing operation circuit is input to another image processing operation circuit and an operation different from the previous operation is performed, an output signal of the result storage memories 11-0 to 11-3 is output to the selector 12-. Image processing operation circuit 1 via 0-12-3
It is necessary to adopt a configuration for inputting to 0-0 to 10-3. Therefore, the image processing operation circuit 10- is connected from the result storage memories 11-0 to 11-3 via the selectors 12-0 to 12-3.
The wiring from 0 to 10-3 is complicated. Selector 1
Since 2-0 to 12-3 are programmably controlled using a microcomputer or the like, the wiring and programs of the control system are also complicated. The present invention solves the problem of the prior art that the peripheral circuits and control of the selectors 12-0 to 12-3 are complicated, and solves the problem of the peripheral circuits and control of the selectors 12-0 to 12-3. Is provided.

[0008]

According to the present invention, in order to solve the above-mentioned problems, a plurality of first selecting means for respectively selecting one of a total operation result and a plurality of first image data, One of the plurality of second image data and the output signal of the first selecting means are respectively input to perform a product-sum operation, and the result of the product-sum operation is sequentially input to the next stage. A memory for storing a product-sum operation result of the image processing operation circuit and the last-stage image processing operation circuit, outputting the stored contents in the form of the total operation result, and supplying the result to the plurality of first selecting means. Means. Further, each of the image processing operation circuits includes a multiplier for multiplying the output signal of the first selecting means and the second image data, and accumulating the multiplication result of the multiplier to obtain the product-sum operation result. An accumulator to be output, and second selecting means for selecting one of the output signal of the accumulator and the output signal of the preceding image processing operation circuit and inputting the selected signal to the accumulator. ing.

[0009]

According to the present invention, since the image processing apparatus is configured as described above, the plurality of first selecting means respectively select one of the total operation result and the plurality of first image data, A plurality of stages of cascaded image processing arithmetic circuits respectively input one of the plurality of second image data and the output signal of the first selecting means, perform a product-sum operation, and calculate the product-sum operation result. Input sequentially to the next stage. Further, storage means stores the product-sum operation result of the final stage image processing operation circuit, and outputs the stored content in the form of the total operation result to supply the plurality of first selection means. Further, the image processing operation circuit multiplies the output signal of the first selecting means by the second image data, accumulates the multiplication result and the output signal of the second selecting means, and outputs the result. The second selecting means selects one of the output signal of the accumulator and the output signal of the preceding image processing operation circuit and inputs the selected signal to the accumulator. Therefore, the above problem can be solved.

[0010]

FIG. 1 is a schematic block diagram of an image processing apparatus according to an embodiment of the present invention. This image processing device
The total operation result S40 and the plurality of first image data IN10
To IN13, selectors 20-0 to 20-3, which are first selecting means for selecting one of them. The selectors 20-0 to 20-3 are connected to the image processing operation circuits 30-0 to 30-3. The image processing operation circuits 30-0 to 30-3 include selectors 20-0 to 20-3.
Output signals and a plurality of second image data IN20 to IN20
23 is a circuit for performing arithmetic processing by inputting each of them.
The image processing operation circuits 30-0 to 30-3 are cascaded so that the operation results are sequentially input to the next stage. The output side of the result storage memory 40 is connected to the selectors 20-0 to 20-
3 is connected. The result storage memory 40 is a circuit that inputs and stores an output signal of the image processing operation circuit 30-3. FIG. 4 is a block diagram of the image processing operation circuit 30-0 shown in FIG.
It is a schematic block diagram of 30-3. This image processing operation circuit includes a pre-stage operation unit 31, a selector 32, a register 33, and a register 34. Pre-stage arithmetic unit 31
Is a circuit composed of an adder, a subtractor, and an absolute value circuit, which receives the first image data IN1 and the second image data IN2, and performs, for example, a calculation of a difference and its absolute value. The selector 32 is a circuit that selects and outputs one of the second image data IN2 and the output signal of the preceding-stage arithmetic unit 31. A register 33 is connected to the preceding stage arithmetic unit 31. A register 34 is connected to the selector 32. The register 33 is a circuit that stores an output signal of the pre-stage operation unit 31. The register 34 stores the selector 3
2 is a circuit for storing the output signal. A multiplier 35 is connected to the registers 33 and 34. The multiplier 35 is a circuit that receives the output signals of the registers 33 and 34 and performs multiplication. The multiplier 35 is a register 3
6 is connected. The register 36 is a circuit for storing the output signal of the multiplier 35. The adder 37 is a circuit that adds the output signal of the register 36 and the output signal of the selector 39. The adder 37 is connected to the register 38. The register 38 is a circuit that stores the output signal of the adder 37 and outputs the output signal OUT2. The selector 39, which is the second selection means, is a circuit that selects one of the output signal OUT2 and the output signal IN3 of the preceding image processing operation circuit and inputs the selected signal to the adder 37.

FIG. 5 is a diagram showing a procedure of a filtering process performed using the image processing apparatus of FIG. The processing procedure of the product-sum operation by the image processing apparatus of FIG. 1 will be described with reference to FIG. As an example of the processing operation, consider a case in which a fourth-order filtering process is performed on one piece of image data in the horizontal direction, and a fourth-order filtering process is performed on the result in the vertical direction. First, the following calculation is performed in the horizontal direction. In the cycle T0, x (0,0), which is the first image data IN10, and the second image data I via the selector 20-0.
N20 _{a 0} is is input to the image processing arithmetic circuit 30-0. The pre-stage operation unit 31 performs an operation by inputting x (0,0) and a _0, and inputs the result to the selector 32 and the register 33. The selector 32 selects and outputs either the output signal of a ₀ and the previous stage arithmetic unit 31. Register 3
Reference numeral 3 stores the output signal of the preceding-stage arithmetic unit 31. The register 34 stores the output signal of the selector 32. Multiplier 3
5 receives the output signals of the register 33 and the register 34 and performs multiplication. The register 36 stores the output signal of the multiplier 35. The adder 37 adds the output signal of the register 36 and the output signal of the selector 39. Register 3
8 stores the output signal of the adder 37 and outputs the output signal OUT
2 is output. The output signal OUT2 is input to the next stage image processing operation circuit 30-1.

Similarly, in cycle T1, selector 2
X which is the first image data IN11 through 0-1
(1, 0) and a which is the second image data IN21
₁ is input to the image processing operation circuit 30-1, and the operation result is input to the next stage image processing operation circuit 30-2.
In cycle T2, _{a 2} second 1 x (2,0) is image data IN12 and of a second image data IN22 via the selector 20-2 is input to the image processing arithmetic circuit 30-2, the The operation result is the next stage image processing operation circuit 30
-3 is input. In cycle T3, the selector 20-3
X (3,0) which is the first image data IN13 via
And a 2 a ₃ is image data IN23 of is inputted to the image processing arithmetic circuit 30-3, a calculation result of the multiplication result and the previous stage of the image processing arithmetic circuit 30-2 is added. In cycle T6, the operation result y (0,0) represented by the following equation is output from the image processing operation circuit 30-3 and stored in the result storage memory 40.

[0013]

(Equation 2) Here, a _k (k = 0 to 3) is the second image data IN20
To IN23, x (k, 0) (k = 0 to 3) are the first image data IN10 to IN13, y (0, k) (k = 0 to
3) is an output signal of the image processing operation circuit 30-3. Similarly, from the cycle T7 to the cycle T9, y (0,1), y expressed by the following equation from the image processing operation circuit 30-3:
(0, 2) and y (0, 3) are output and stored in the result storage memory 40.

[0014]

(Equation 3) Further, the following calculation is performed in the vertical direction. As in the case of the horizontal direction, in the cycle T7, the y (0, 0) stored in the result storage memory 40 via the selector 20-0.
0) and _{b 0} is the second image data IN20 is input to the image processing arithmetic circuit 30-0, the calculation result is input to the next stage of the image processing arithmetic circuit 30-1. Cycle T
8, _{b 1} is the y (0, 1) and the second image data stored in the result storage memory 40 through the selector 20-1 IN21 is input to the image processing arithmetic circuit 30-1, The calculation result is output to the next-stage image processing calculation circuit 30-
2 is input. In cycle T9, the y stored in the result storage memory 40 via the selector 20-2.
(0, 2) and b which is the second image data IN22
₂ is input to the image processing operation circuit 30-2, and the operation result is input to the next-stage image processing operation circuit 30-3.
In cycle T10, the y (0,3) and the second y (0,3) stored in the result storage memory 40 via the selector 20-3 are output.
B ₃ is an image data IN23 of is inputted to the image processing arithmetic circuit 30-3, a calculation result of the calculation result and the preceding image processing operation circuit 30-2 is added. Cycle T
In step 13, the operation result z (0,0) expressed by the following equation is output from the image processing operation circuit 30-3, and the result storage memory 40
Is stored in

[0015]

(Equation 4) Here, b _k (k = 0 to 3) is the second image data IN20
To IN23, y (k, 0) (k = 0 to 3) are the first image data IN10 to IN13, z (0, k) (k = 0 to
3) is an output signal of the image processing operation circuit 30-3. As described above, in the present embodiment, the image processing operation circuit 30-0
30-2 are cascade-connected to form an image processing apparatus, so that a plurality of image data are simultaneously input to perform a parallel operation, and at the same time, the operation result of the preceding image processing operation circuit is used as the next image processing operation circuit. It is also possible to perform a series operation of inputting to the. Further, the configuration is such that the operation result of the image processing operation circuit 30-2 at the last stage is input to all the image processing operation circuits, so that two-dimensional image processing operation can be performed smoothly.

The present invention is not limited to the above embodiment,
Various modifications are possible. For example, there are the following modifications. (A) In FIG. 1, the image processing operation circuits 30-0 to 30-2
Although the memory for storing the result is not connected, it is also possible to connect and output each operation result. Further, a configuration of a parallel operation circuit as shown in FIG. 3 can be adopted. (B) Although one input signal of the selector 39 in FIG. 4 is used as an output signal of another image processing operation circuit, the present invention is not particularly limited to this, and any data may be used unless the data exceeds the input bit length of the adder 37. Types of data can be entered. (C) The pre-stage arithmetic unit 31, the selector 32, the register 33, the register 34, and the register 36 in FIG. 4 may be omitted depending on the data processing method.

[0017]

As described above in detail, according to the present invention, since the image processing apparatus is constituted by a plurality of cascade-connected image processing arithmetic circuits, a plurality of image data are simultaneously inputted to operate in parallel. At the same time, the serial operation of inputting the operation result of the preceding image processing operation circuit to the next image processing operation circuit can be performed. Therefore, high-speed arithmetic processing can be performed with a simpler configuration than the conventional image processing apparatus having a parallel configuration.

[Brief description of the drawings]

FIG. 1 is a configuration block diagram of an image processing apparatus according to an embodiment of the present invention.

FIG. 2 is a configuration block diagram of a conventional image processing apparatus.

FIG. 3 is a configuration block diagram of another conventional image processing apparatus.

FIG. 4 is a block diagram illustrating a configuration of an image processing operation circuit in FIG. 1;

FIG. 5 is a diagram showing a filtering process calculation procedure in FIG. 1;

[Explanation of symbols]

 20-0 to 20-3 Selector 30-0 to 30-3 Image processing operation circuit 31 Pre-stage operation unit 35 Multiplier 37 Adder 39 Selector 40 Result storage memory

Claims (1)

(57) [Claims] 1. A plurality of first selecting means for respectively selecting one of a total operation result and a plurality of first image data; one of a plurality of second image data and said first selecting means And a multistage cascaded image processing operation circuit for sequentially inputting the product sum operation result to the next stage, and a product of the final stage image processing operation circuit. Storage means for storing a sum operation result, outputting the stored content in the form of the total operation result, and supplying the result to the plurality of first selecting means, wherein each of the image processing operation circuits A multiplier for multiplying the output signal of the selection means by the second image data; a cumulative adder for cumulatively adding the multiplication result of the multiplier to output the product-sum operation result; and an output of the cumulative adder. Signal and the output signal of the preceding image processing operation circuit. And a second selecting means for inputting selects either the 該累 product adder, an image processing apparatus characterized by having.