JP3183441B2 - Instantaneous interruption switching method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an SDH (Synchronus D)
Digital Hierarchy) The present invention relates to a transmission line switching device of a transmission system.

[0002]

2. Description of the Related Art In order to ensure the reliability of communication, in a conventional transmission system, one spare system is prepared for one or N systems on the same route, and when a failure occurs in an active system or for maintenance and operation purposes. In the case where the transmission line is cut off, a redundant system configuration is adopted in which the system is manually or automatically switched to a standby system. However, at the time of actual switching from the active system to the standby system, notification of failure information from the receiving side to the transmitting side, checking of the idle status and normal operation state of the standby system, switching operation, synchronization recovery operation, switching back, etc. Since a complicated process is required and the signal is cut off during the recovery time from the failure to the normal operation due to the respective protection times, the data loss due to the instantaneous interruption occurs. As the transmission rate increases, the amount of lost data also increases.

A transmission line switching method which solves the above-mentioned problem by performing switching without instantaneous interruption has already been proposed (Japanese Patent Application No. Hei 6-165573 "Transmission line switching device" proposed by the present inventors). "reference). FIG. 3 shows a transmission line switching means according to the prior application. Switching without instantaneous interruption is possible by matching the phases of the active system and the standby system and performing switching within one bit. However, the frame phases of the two incoming signals do not always pass through the same transmission path and the same path. Therefore, a time difference, that is, a phase difference occurs between the two input signals arriving at the transmission line switching device on the receiving side.

In the above-described transmission line switching method, the multi-frame phases of the active system and the standby system are synchronized with each other by synchronizing the J1 byte. FIG. 4 shows the configuration of the VC-3 frame stored in the STM0 frame. J1 byte is ITU (International Telecommunication Union)
-TG. STM (Synchronous Synchronous) conforming to the synchronous digital hierarchy recommended in 707, 708, and 709.
POH (Path Over He) in Transport Module (Frame)
ad). In the method according to the above-mentioned prior application, this byte repeatedly transmits a signal of a fixed pattern with a multi-frame configuration in order to confirm a VC (Virtual Container) path continuity. Therefore, by synchronizing the J1 bytes of both systems, the head of the multiframe can be matched. For example, unique data is inserted in advance into the 63rd and 64th frames in a 64 multi-frame configuration in the J1 byte. Therefore, by detecting this, it is possible to obtain a delay time difference, that is, a phase difference, between the system 0 and the system 1 due to passing through different paths. For example, in the case of a 64 multi-frame configuration, one frame is 125 μs, so that a phase difference of 8 ms can be absorbed.

[0005] When adjusting the frame phase, the effect of adding a delay can be obtained by adjusting the timing of writing to and reading from the memory once. For that purpose, an elastic store memory capable of performing a write operation and a read operation independently is required. FIG. 5 shows the configuration of the elastic store memory. f _i represents the write clock, f ₀ denotes the read clock. MEM is a memory circuit, DAT
A-IN is a data input, DATA-OUT is a data output, WAC is a write address counter (Write Addr).
ess Counter), RAC is the read address counter
(Read Address Counter, hereinafter referred to as RAC).
Delay indicates a delay. ITU-TG. 707, 708,
In the SDH transmission method conforming to 709, the head of the VC path is AU-PTR (Admi-PTR) in the STM-0 frame shown in FIG.
nistrative Unit Pointer). Since the elastic store memory is generally used to replace an input signal coming from a transmission line with an intra-station clock, even in a synchronous network, the averages of the clock speeds of f _i and f ₀ are usually the same, but they are mutually equal. Changes over time. However, in general, a signal that has been once subjected to termination processing and has been reloaded to the intra-station clock has already been subjected to pointer termination processing indicating the beginning of the VC path, so that f _i = f ₀ and is synchronized with the intra-station clock. ing. A write address counter (hereinafter, referred to as a WAC) counts each time writing is performed,
The control can be performed independently of the RAC. Conversely, R
AC counts each time a read is performed, and its control is WA
Can be performed independently of C. Here, the WAC of system 0 is represented as "WAC0", and if the memory address pointed to is address 0, it is represented as "= 0". Hereinafter, the same applies to RAC. However, in the case where the memory addresses of both the 0/1 system are written to the same memory address at the same time, since they can be realized by one WAC, they are expressed as “WAC”.

[0006]

In order to absorb the phase difference between two inputs in the elastic store memory, it is necessary to adjust the RAC of the phase matching system to match the read phases of both systems. However, in order to detect the phase difference between the 0 system and the 1 system and adjust the RAC of the system that matches the phases, it is necessary to add or subtract the value of the phase difference to or from the current RAC value. For that purpose, processing must be performed by an arithmetic circuit including an adder. In addition, when performing the calculation, it is necessary to consider the overflow and the underflow of the calculation result at the same time, which further increases the circuit scale.

FIG. 6 shows a conventional example that considers the operation result.
For example, since the adjustment of the phase difference is performed by the memory circuit, if the memory amount is 12240 bytes (16 frames in the VC-3 pass), if the address is displayed in byte units, the RAC indicating the data stored therein is displayed. Is also 0-1
Up to 2239. Considering that the phase difference changes, J1 # 1, which is the head of the VC path, is not always stored from RAC = 0. Therefore, J
1 # 1 data is stored.

The left side of FIG. 6 shows a conventional example in which an overflow is taken into consideration. For example, data of J1 # 1 of the first system is read from RAC = 12000, the relative delay with respect to the switching source is 500 μs, and the data is converted into bytes. If we delay by 3060 bytes, RAC = 150 with 12000 + 3060
If reading from RAC = 12000 at 60, 3
This means that a delay of 060 bytes, that is, 500 μs has been added. However, since the actual RAC value is only up to 12239, if the value is read from RAC = 12000 when RAC = 2820 by subtracting 12240 from 15060, a delay of 500 μs is added. That is, it is necessary to consider overflow.

The right side of FIG. 6 shows a conventional example in which an underflow is taken into consideration. For example, data of JI # 1 of system 1 is read from RAC = 2820, and the relative delay with respect to system 0 is 500 μs, byte. If the conversion is advanced by 3060 bytes, reading from RAC = 2820 when RAC = −240 at 2820-3060 adds a delay of 3060 bytes, that is, 500 μs.
However, there is no negative address in the actual address. Therefore, by subtracting 240 from 12240 and reading RAC = 2820 when RAC = 12000, a delay of 500 μs is added. That is, it is necessary to consider underflow.

Therefore, an object of the present invention is to obtain the amount of delay by operation because the operation circuit itself, its peripheral circuits necessary for considering overflow or underflow, and a calculation algorithm are required, and accordingly, the hardware is correspondingly required. It is an object of the present invention to provide an instantaneous interruption switching method capable of adjusting the phase difference between the active system and the standby system by solving the problem that the scale of the wear increases.

[0011]

SUMMARY OF THE INVENTION The present invention provides an ITU-T
G. FIG. A receiving unit including a delay unit configured to include a memory circuit including an elastic store memory, which is adapted to a synchronous digital hierarchy recommended in 707, 708, and 709 and receives a signal arriving from two transmission paths including different paths; In the non-stop switching method in which switching is performed without loss of bits, the system that can match the frame phase is the working system, and the remaining 1
One is a standby system that matches the frame phase with the active system,
Assuming that the difference between the memory addresses for storing the frame synchronization patterns of both systems read by C is the phase difference α between the active system and the standby system, both the active system and the standby system memory circuits are sequentially stored at the same time from the same memory address in the same time If it is desired to advance α to the RAC to be written and adjusted, when the memory address of the active or standby system read by the RAC is 0, the value of the memory address α of the standby system read by the RAC is changed. If the load is to be adjusted and α is to be delayed, when the memory address of the active or standby system read by RAC is α, the value of memory address 0 of the standby system read by RAC is loaded and adjusted. It is characterized by the following.

In the non-interruptible switching system, a system in which the frame phase can be matched is a working system, and the other one is a spare system in which the frame phase is matched with the working system. Write to different memory addresses at the same time and adjust for
If it is desired to proceed, when the memory address of the standby system read by the RAC is 0, the value of the memory address α of the standby system read by the RAC is loaded and adjusted. When the memory address of the standby system is α, the adjustment is performed by loading the value of the memory address 0 of the standby system read by the RAC.

[0013]

According to the frame phase difference adjusting method of the present invention, RAC
Since the addition or subtraction is not performed using an arithmetic circuit when adjusting, the arithmetic circuit itself and its peripheral circuits and calculation algorithms required to consider overflow or underflow are not required. It is possible to make it smaller.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings, with a system capable of matching phases as a working system and a system matching phases as a standby system. FIG. 1 and Table 1 show and explain Embodiment 1 of the present invention.

[0015]

[Table 1]

FIG. 1 and Table 1 show an example in which the system 0, which is the active system, is ahead of the system 1 which is the standby system by 4 bytes on the memory. By writing the memory addresses of the system 0 and the system 1 sequentially from the same memory address, the memory addresses of the WAC at the same time are the same. That is, as shown in Table 1, "address 0/1" in the table indicates the memory address of both systems, and "data 0" or "data 1" indicates that the WAC or RAC 0/1 indicates each memory address. An example of data is shown. For example, this means that data of the system 0 indicates "M" when the RAC of the system 0 reads the memory address "E" at a certain time.
Therefore, the phase difference is detected, for example, when the 0-system RAC, whose phase is advanced using the counter circuit, reads the memory address “2” at which the frame synchronization pattern is detected, that is, 1 byte from RAC0 = 2. When the one-system RAC having the delayed phase reads the memory address “6” at which the frame synchronization pattern is detected, that is, stops at RAC1 = 6, the phase difference α
Can be requested.

According to the contents described above, when the delayed standby system is adjusted to the active system, the RAC1 of the standby system may be advanced by the phase difference α.
By loading C1 = 4 (α value), the phase of the standby system can be matched with that of the active system. Similarly, when the phase is adjusted by the standby system itself, the standby system RAC1 is also used.
Can be advanced by the phase difference α, and by loading RAC1 = 4 (α value) when RAC1 = 0, the phase of the standby system can be matched to that of the active system. Therefore, when the memory address of the active system or the standby system read by the RAC is 0, the phase of the signal read from the memory can be matched by loading the value of the memory address α of the standby system read by the RAC. is there.

FIG. 2 and Table 2 show a second embodiment according to the second aspect of the present invention. FIG. 2 and Table 2 show an example in which the active system is 4 bytes behind the standby system on the memory.

[0019]

[Table 2]

In the same way as in the first embodiment, when the standby system is advanced to match the working system, RAC0 may be delayed by the phase difference α, so that data is already written when RAC1 = 4 (α value). If the data of RAC0 = 0 is loaded, the phases can be matched. Similarly, when the phase is adjusted by the standby system itself, the RAC0 of the standby system is also used.
Should be delayed by the phase difference α, so that RAC0 = 4 (α
If the data of RAC0 = 0 already written at the time of (value) is loaded, the phases can be matched. Therefore, when the memory address of the active or standby system read by the RAC is α, the phase of the signal read from the memory can be matched by loading the value of the memory address 0 of the standby system read by the RAC. is there.

Table 3 shows a third embodiment according to the third aspect of the present invention.

[0022]

[Table 3]

Table 3 shows an example in which the working system is ahead of the spare system by 4 bytes on the memory. In the first and second embodiments, an example is shown in which writing is sequentially performed from the same memory address at the same time to the working system and the protection system memory circuit. An example will be described in which phase adjustment can be performed even when writing is sequentially performed on memory circuits from different memory addresses at the same time. The phase difference can be detected by detecting the RAC0 = 2 using the counter circuit as in the first and second embodiments, counting one byte at a time, and stopping when the RAC1 = 6 is detected, thereby obtaining the phase difference α. . next,
As described in the first and second embodiments, the phase difference can be adjusted by the means for adjusting the phase by the standby system itself. That is, when the delayed standby system is matched with the working system, RAC1 may be advanced by the phase difference α.
If the memory address of RAC1 = 4 (α value) is loaded when C1 = 0, the phases can be matched.

Table 4 shows a fourth embodiment of the present invention.

[0025]

[Table 4]

Table 4 shows an example in which the working system is 4 bytes later than the spare system on the memory. Similarly to the third embodiment, when the standby system that is in progress is matched with the active system, RAC0 of the standby system may be delayed by the phase difference α, so that data is already written when RAC0 = 4 (α value) of the standby system. The phase can be adjusted by loading the memory address of RAC0 = 0 of the standby system. As described above, even when writing to the working memory system and the standby memory circuit sequentially from different memory addresses at the same time, if it is desired to advance α to the RAC to be adjusted, RAC
When = 0, the data of the standby system RAC = α is loaded and adjusted, and when it is desired to delay α, the standby system RAC = α
At this time, the data of RAC = 0 in the standby system is loaded and adjusted, and the phase can be adjusted by performing the adjustment by the standby system itself.

[0027]

As described above, according to the present invention, it is possible to match the phases of the two systems without directly performing calculations. This eliminates the need for the arithmetic circuit itself and its peripheral circuits and calculation algorithms necessary for considering overflow or underflow, thereby making it possible to reduce the scale of hardware accordingly.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first embodiment corresponding to claim 1;

FIG. 2 is a view showing a second embodiment corresponding to claim 2;

FIG. 3 is a block diagram of a transmission path switching unit according to the prior application.

FIG. 4 is a diagram showing a frame configuration of STM0 and VC-3 according to CCITT recommendation.

FIG. 5 is a diagram showing a configuration example of an elastic store memory.

FIG. 6 is a diagram showing an example in which an overflow or an underflow is considered.

[Explanation of symbols]

RAC read address counter WAC write address counter f _i write clock f ₀ read clock MEM memory circuit DATA-IN data input DATA-OUT Data output

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Tadanobu 1-14-5 Kichijoji Honmachi, Musashino City, Tokyo Inside NTT Electronics Technology Co., Ltd. (72) Motoharu Ikeda 1-chome, Kichijoji Honcho, Musashino City, Tokyo No. 14 No. 5 within NTT Electronics Technology Co., Ltd. (56) References JP-A-4-291532 (JP, A) JP-A-6-132944 (JP, A) JP-A-64-50627 (JP, A) JP-A-5-183469 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04J 3/00-3/26 H04B 1/74 H04L 1/00 H04L 1/08-1 / twenty four

Claims (4)

(57) [Claims] 1. An ITU-TG. 707, 708, 70
9. Compatible with the synchronous digital hierarchy recommended in 9 and is constituted by a memory circuit including first and second elastic store memories for respectively receiving frame signals transmitted through two transmission paths including different paths. A non-instantaneous interruption switching method for switching between first and second receiving means including delay means without loss of bits, wherein one of the first receiving means and the second receiving means is operated at present. The working system and the remaining one are set as a spare system for adjusting the frame phase to the working system, and the memory circuits of the working system and the spare system are sequentially assigned at the same time from the same memory address. Writing, and when the working system is advanced in frame phase from the protection system, the working system frame synchronization pattern read by a read address counter And a memory address for storing the frame synchronization pattern of the standby system, and when the memory address difference is defined as a phase difference α, the working system or the standby system read by the read address counter is obtained. When the memory address of the system is 0, the frame phase of the signal read from the memory is adjusted by loading the value of the memory address α of the standby system read by the read address counter. Instantaneous interruption switching method. 2. The method according to ITU-T G. 707, 708, 70
9. Compatible with the synchronous digital hierarchy recommended in 9 and is constituted by a memory circuit including first and second elastic store memories for respectively receiving frame signals transmitted through two transmission paths including different paths. In a hitless switching method for switching between first and second receiving means including delay means without loss of bits, one of the first receiving means and the second receiving means may be set to a frame phase. The working system to be matched and the remaining one are set as a spare system for adjusting the frame phase to the working system. The memory circuits of the working system and the spare system are sequentially written at the same time from the same memory address in the same time. And when the working system is behind the protection system in frame phase, the frame synchronization pattern of the working system read by the read address counter is read. When a memory address for storing a turn and a memory address for storing the frame synchronization pattern of the standby system are obtained, and the memory address difference is defined as a phase difference α, the working system or the working system read by the read address counter is used. When the memory address of the standby system is α, by loading the value of the memory address 0 of the standby system read by the read address counter, the frame phase of the signal read from the memory is matched. Instantaneous interruption switching method. 3. The method according to ITU-T G. 707, 708, 70
9. Compatible with the synchronous digital hierarchy recommended in 9 and is constituted by a memory circuit including first and second elastic store memories for respectively receiving frame signals transmitted through two transmission paths including different paths. In a hitless switching method for switching between first and second receiving means including delay means without loss of bits, one of the first receiving means and the second receiving means may be set to a frame phase. The working system to be matched and the remaining one are set as spare systems for adjusting the frame phase to the working system, and the memory circuits of the working system and the spare system are written sequentially from different memory addresses at the same time. And when the working system is ahead of the protection system in frame phase, the frame synchronization of the working system is read by a read address counter. When a memory address for storing a pattern and a memory address for storing the frame synchronization pattern of the standby system are obtained, and the memory address difference is defined as a phase difference α, the standby memory read by the read address counter A non-instantaneous interruption switching method, wherein when the address is 0, the frame phase of a signal read from the memory is matched by loading the value of the memory address α of the standby system read by the read address counter. . 4. The method according to ITU-TG. 707, 708, 70
9. Compatible with the synchronous digital hierarchy recommended in 9 and is constituted by a memory circuit including first and second elastic store memories for respectively receiving frame signals transmitted through two transmission paths including different paths. In a hitless switching method for switching between first and second receiving means including delay means without loss of bits, one of the first receiving means and the second receiving means may be set to a frame phase. The working system to be matched and the remaining one are set as spare systems for adjusting the frame phase to the working system, and the memory circuits of the working system and the spare system are written sequentially from different memory addresses at the same time. And when the working system is behind the protection system by a frame phase, the frame synchronization of the working system read by the read address counter is performed. When a memory address for storing a pattern and a memory address for storing the frame synchronization pattern of the standby system are obtained, and the memory address difference is defined as a phase difference α, the memory address of the standby system read by the read address counter is obtained. When α is α, the read address
A non-instantaneous interruption switching method, wherein a value of a memory address 0 of the standby system read by a counter is loaded to match a frame phase of a signal read from the memory.