JPH01263566A - System for measuring transmission delay difference - Google Patents

Abstract

PURPOSE:To measure transmission delay difference by reduced memory quantity, by adding phase control quantity due to synchronism and controlled delay quantity. CONSTITUTION:The same digital data train is transmitted from the apparatus on a transmission side by present and preparatory transmission lines 5, 6. With respect to two data trains received at this time, a transmission unit wherein a time shorter than the difference in delay quantity is one unit, that is, a frame phase is allowed to coincide and synchronize by the bit synchronous circuit 8, frame synchronous circuit 24 and elastic store memory 41 of a synchronous means. The phases of two data trains are shifted by the time corresponding to a frame by two variable delay circuits 28 and controlled by the bit comparing circuit 21 and control circuit 29 of a control means so that the outputs of two circuits 28 comes same. The phase control quantity due to the synchronous means and the delay quantity controlled by the control means are added by the frame pulse phase difference and delay difference detection circuits 25, 26 of an adding means and an adder circuit 27 to output the difference between the delay quantities of two transmission lines 5, 6.

Description

[Detailed description of the invention] [Industrial application field] The present invention is utilized for time division multiplexed digital transmission.

In particular, the present invention relates to a transmission delay difference measurement method for measuring the difference in the amount of delay between two transmission paths. The present invention is suitable for use in optical fiber communication equipment.

[Conventional technology]

In the field of information transmission, transmission line switching has traditionally been performed to switch a working transmission line to a backup transmission line when a line or transmission device fails or when switching back after failure switching. At this time, in order to switch the transmission path without any loss of information and without interruption, it is necessary to measure the transmission delay difference and match the amount of delay between the working and backup transmission paths.

In addition, in order to increase the efficiency of line usage, we will utilize the vacant lines of the two working transmission lines installed between the two 71s.
A transmitting device divides one information string into two parts per frame and transmits them in parallel, and a receiving device combines the information strings. In this case as well, it is necessary to measure the delay difference and match the delay amounts of the two transmission paths.

FIG. 5 is a block diagram of a conventional digital transmission device.

In the transmitting device 1, the multiplexing conversion device 2 multiplexes the digital information string into frames, and transmits the frame through the transmission path changeover switch 4 to the working transmission path 5 and the backup transmission path 6 in parallel.

In the receiving side device 7, the working transmission line 5 and the backup transmission line 6
A bit synchronization circuit 8 performs bit synchronization for each of the clocks 11 and 12, respectively. The phase-locked loop 15 absorbs the phase fluctuations of the clocks 11 and 12, and, under the control of the control circuit 16, generates a clock 1 that is phase-synchronized with one of the clocks.
Generates 7. The flip-flop 18 takes in the output information string of the bit synchronization circuit 8 using the clock 17, and makes both bit phases coincide. The variable length delay memory 19 is
Information strings with matching bit phases are stored, and the stored information strings are output after respective predetermined times have elapsed according to control signals 22 and 23 from the control circuit 20. Bit comparison circuit 2
1 is the information string read from the variable length delay memory 19.
Compare bit by bit. The control circuit 20 controls so that the plane input to the bit comparison circuit 21 always has the same bit sign (for example, when the bit comparison circuit 21 is an exclusive OR circuit,
The variable length delay memory 19 is controlled bit by bit so that the output 40 is always "0".

In this way, when the two inputs of the bit comparison circuit 21 always have the same bit code, the delay amounts of the two variable length delay memories 19 become the transmission delay difference between the outputs of the two flip-flops 18. At this time, the two information strings at the outputs of the two variable length delay memories 19 are completely the same.

[Problem that the invention seeks to solve]

However, in the conventional example described above, it is necessary to change the amount of delay by the variable length delay memory 19 for each bit.
This method has the disadvantage that measurement requires time, and since all received information bits must be delayed, the amount of memory in the variable length delay memory 19 becomes large.

For example, consider a case where the difference in transmission path length is 300 km.

Generally, it takes about 5μ for information to propagate through a transmission path of lk+n.
There will be a delay of 1.5m at 300km.
This results in a delay of s. In the case of a 400Mb/s transmission line,
Two variable length delay memories with a capacity of 600 kbit are required.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems and provide a transmission delay difference measurement method that can measure transmission delay differences with a small number of memo UIs.

[Means for solving problems]

The transmission delay difference measuring method of the present invention includes a synchronizing means for matching the phase of a transmission unit in which one unit is a time shorter than the difference in delay amount for two information streams respectively received from two transmission paths, and A delay means for shifting the phase of the column for each transmission unit time, a control means for controlling the amount of delay of the delay means so that two outputs of the delay means have the same value, and an amount of phase adjustment by the synchronization means. The present invention is characterized by comprising an adding means for adding the delay amounts controlled by the control means and outputting the difference between the delay amounts of the two transmission lines.

To determine whether the outputs of the delay means are the same, one or more arbitrary bits within the transmission unit are compared.

This comparison is performed for bits at the same position in each transmission unit.

INDUSTRIAL APPLICATION This invention is utilized for a frame mass transmission apparatus and a cell multiplex transmission apparatus. A frame multiplex transmission device is a device that allocates information sequences from multiple terminals to predetermined bit positions within a frame and multiplex transmits them. To implement the present invention in such a device, a frame is used as a transmission unit. That is, the synchronizing means matches the frame phases of the information strings received from the two transmission paths, and the delaying means delays the information strings in units of frames. In addition, the cell multiplex transmission equipment divides the information string into certain lengths and establishes synchronization between these cells and cells (these are especially referred to as "main information cells"), each of which has a bit indicating the destination added. In order to
This is a device that multiplexes and transmits To implement the invention in such a device, cells are used as transmission units. That is, the synchronization means matches the cell phases of the information strings received from the two transmission paths, and the delay means delays the information strings in units of cells.

[For production]

Using the frame configuration or cell configuration required for normal digital transmission, the delay difference in frame units or cell units,
The intra-frame or intra-cell delay differences are measured and added. Thereby, the transmission delay difference can be measured with a small amount of memory.

〔Example〕

FIG. 1 is a block diagram of a digital transmission device according to a first embodiment of the present invention. In this embodiment, the present invention is implemented in a frame multiplex transmission device.

This device consists of a transmitting device 1 that transmits the same digital information string to a working transmission path 5 and a protection transmission path 6, and a receiving device 7 that calculates the difference in delay amount caused by the working transmission path 5 and protection transmission path 6. and a measuring means for measuring within.

The measurement means is a synchronization means for matching the phases of the two information streams received from the working transmission path 5 and the backup transmission path 6, respectively, in a transmission unit in which one unit is a time shorter than the difference in delay amount, that is, the frame. Bit synchronization circuit 8
, a frame synchronization circuit 24, an elastic store memory 41, and a delay means for shifting the phases of these two information sequences by frames, that is, two variable delay circuits 2.
8, a control means for controlling the delay amount of these two variable delay circuits 28 so that the outputs of these two variable delay circuits 28 have the same value, that is, a bit comparison circuit 21 and a control circuit 29, and a synchronization means. Adding means for adding the phase adjustment amount and the delay amount controlled by the control means and outputting the difference between the delay amounts of the two transmission paths, that is, an inter-frame pulse phase difference detection circuit 25, a delay difference detection circuit 26, and An addition circuit 27 is provided.

In the transmitting device 1, the multiplexing/converting device 2 multiplexes the digital information string into frames, and transmits the frame through the transmission path changeover switch 4 to the working transmission path 5 and the backup transmission path 6 in parallel.

In the receiving side device 7, the working transmission line 5 and the backup transmission line 6
A bit synchronization circuit 8 performs bit synchronization for each of the clocks 11 and 12, respectively. The frame synchronization circuit 24 generates frame pulses 30.31 for frame synchronization of the output information string of the bit synchronization circuit 8 using clocks 11.12. The elastic store memory 41 uses the phase of the frame pulse 30.31 as a reference and stores the received information sequence using the clock 11.12. The elastic store memory 41 also uses the station frame pulse 32 generated by the common station clock source 42 as a reference, and outputs the stored information string using the station clock pulse 33 generated by the station clock source 42 . As a result, the information string received from the working transmission line 5 and the protection transmission line 6
The frame phase matches that of the information sequence received from .

The two variable delay circuits 28 are each supplied with information sequences having the same frame phase. The output of this variable delay circuit 28 is supplied to the bit comparison circuit 21.

The control circuit 29 refers to the output 40 of the bit comparison circuit 21 and controls the variable delay circuit 28 using control signals 37 and 38.
The bit comparison circuit 21 is controlled so that the bit comparison circuit 21 always has the same bit code.

That is, the delay amount of one variable delay circuit 28 is set to the minimum, and the delay amount of the other variable delay circuit 28 is increased in units of frame length so that the two bit comparators 21 always have the same bit code. (For example, the bit comparison circuit 21
When an exclusive OR circuit is used as
0 is always "0"). Even if the delay amount of the other variable delay circuit 28 is the maximum, if the two inputs of the bit comparison circuit 21 do not always have the same bit sign, the delay amount of this variable delay circuit 28 is set to the minimum, and one of the above Similarly, the delay amount of the variable delay circuit 28 is increased.

When the two inputs of the bit comparison circuit 21 always have the same bit code, the control circuit 29 determines the difference in the amount of delay of each variable delay circuit 28 as a transmission delay difference in units of frame length.

Since the delay amount of the variable delay circuit 28 is changed in frame phase units, the time required for determination is short.

The frame hustle phase difference detection circuit 25 detects the phase difference between the frame pulses 30 and 31 from the phase of the frame pulses 30 and 31, respectively.
The delay difference detection circuit 26 detects the delay difference obtained by subtracting the phase of
Output to. The delay difference detection circuit 26 detects the delay difference between the inter-frame pulse delay signals 34 and 35. The adder circuit 27 sums the transmission delay difference after frame phase synchronization detected by the control circuit 29 and the delay difference in the elastic store memory 41 detected by the delay difference detection circuit 26.

As a result, the transmission path delay difference at the output of the bit synchronization circuit 8 is determined.

FIG. 2 shows the format of the information string. This information column is
The only difference is the amount of delay, which is common between the working transmission line and the protection transmission line.

This information string is made up of frames, and each frame is made up of a frame synchronization pin F and main information I. The bit comparison circuit 21 compares one or more arbitrary bits D in the main information I.

However, the bits D to be compared must be at the same bit position in each frame. All bits in the main information I can also be compared.

In the embodiment described above, the receiving side device 7 includes two variable delay circuits 28 with a small memory capacity, their control circuit 29, a bit comparison circuit 21, and a frame without changing the frame configuration necessary for normal digital transmission. By simply adding the inter-pulse phase difference detection circuit 25, the transmission delay difference between the working transmission line 5 and the protection transmission line 6 can be detected. Note that the bit synchronization circuit 8, frame synchronization circuit 24, station clock source 42, and elastic store memory 41 are necessary circuits even in a normal digital transmission device.

FIG. 3 is a block diagram of a digital transmission apparatus according to a second embodiment of the present invention. In this embodiment, the present invention is implemented in a cell multiplex transmission device.

This device consists of a transmitting device 1 that transmits the same digital information string to a working transmission path 5 and a protection transmission path 6, and a receiving device 7 that calculates the difference in delay amount caused by the working transmission path 5 and protection transmission path 6. and a measuring means for measuring within.

The measurement means is a synchronization means for matching the phase of the two information streams received from the two transmission paths, the working transmission path 5 and the protection transmission path 6, in a transmission unit in which one unit is a time shorter than the difference in delay amount, that is, the phase of the cell. , that is, bit synchronization circuit 8,
Cell synchronization circuit 45 and elastic store memory 4
1, a delay means for shifting the phase of these two information strings by the time of a cell, that is, two variable delay circuits 28, and a delay means for shifting the phase of these two information sequences by the time of a cell, and A control means for controlling the amount of delay of the variable delay circuit 28, that is, a bit comparison circuit 21 and a control circuit 29, adds the amount of phase adjustment by the synchronization means and the amount of delay controlled by the control means, and calculates the amount of delay between the two transmission lines. Adding means for outputting the difference in delay amounts, that is, the cell phase pulse-to-cell phase difference detection circuit 48, the delay difference detection circuit 26, and the addition circuit 2
Equipped with 7.

In the transmitting device 1, the cell synchronization button insertion circuit 44 inserts a cell synchronization button into the empty cell output by the cross-connect switch 43, that is, the cell that does not contain main information. If an empty cell does not arrive even after exceeding a certain number of cells, a cell synchronization button is forcibly inserted. The transmission path selector switch 4 connects the output of the cell synchronization button insertion circuit 44 to both the working transmission path 5 and the protection transmission path 6, and transmits the same information string in parallel.

In the receiving side device 7, the working transmission line 5 and the backup transmission line 6
A bit synchronization circuit 8 performs bit synchronization for each of the clocks 11 and 12, respectively. Cell synchronization circuit 45 reproduces cell phase pulses 46.47 using clock 11.12. The elastic store memory 41 uses the phase of the cell phase pulse 46.47 as a reference, and stores the received information sequence using the clock 11.12. The elastic store memory 41 also outputs the stored information sequence in response to local clock pulses generated by a common local clock source 42. As a result, the cell phases of the information string received from the working transmission path 5 and the information string received from the protection transmission path 6 match.

The two variable delay circuits 28 are each input with information strings in which the cell phases match. The operations of the variable delay circuit 28, bit comparison circuit 21, and control circuit 29 are the same as in the first embodiment except that the delay amount of the variable delay circuit 28 is changed in units of cell phases.

In this way, the control circuit 29 can detect the transmission delay difference in cell phase units between the working transmission line 5 and the protection transmission line 6.

The inter-cell phase pulse phase difference detection circuit 48 operates in the same manner as the inter-frame pulse phase difference detection circuit 25 of the first embodiment, except that the cell phase pulse is supplied instead of the frame pulse.

The delay difference detection circuit 26 is connected to the elastic store memory 4
The delay difference between the active side and the backup side at 1 is detected. The adder circuit 27 sums the transmission delay difference after cell phase synchronization detected by the control circuit 29 and the delay difference in the elastic store memory 41 . As a result, the bit synchronization circuit 8
The transmission path delay difference at the output of is determined.

FIG. 4 shows the format of the information string. This information column is
The only difference is the amount of delay, which is common between the working transmission line and the protection transmission line.

This information string is composed of main information cells and synchronization cells. The main information cell is a logical channel number LCN indicating the destination.
, an area V including a route identifier for selecting an outgoing route in the cross-connect switch, and main information (2). Logical channel number LCN and area V constitute header H. A synchronization cell is composed of a synchronization bit string F and an area S containing monitoring information and the like. Each cell has the same bit length.

The bit comparison circuit 21 compares one or more bits D included in the main information (2) of the main information cell and one or more bits D in the synchronization cell at the same bit position. However, the bits D to be compared must be at the same bit position in each cell.

It is also possible to compare all the bits in the main information ■.

The embodiment described above allows two variable delay circuits 28, 4 with small memory capacity to be installed in the receiving side device, without changing the cell configuration necessary for normal digital transmission.
9. The transmission delay difference between the working transmission line 5 and the protection transmission line 6 can be detected by simply adding the bit comparison circuit 21 and the cell position +th pulse phase difference detection circuit 48. In addition,
The cell synchronization button insertion circuit 44, the bit synchronization circuit 8, the cell synchronization circuit 45, the local clock source 42, and the elastic store memory 41 are necessary circuits even in a normal digital transmission device.

〔Effect of the invention〕

As explained above, the transmission delay difference measurement method of the present invention is
Delay differences in transmission paths can be measured with less hardware effort and shorter measurement time without changing the frame configuration or cell configuration required for normal digital transmission.

INDUSTRIAL APPLICATION This invention is utilized for the switching of a transmission path, and has the effect of being able to perform transmission path switching without momentary interruption by correcting the measured delay difference. Furthermore, it is possible to maintain the transmission quality by using the vacant lines of the two working transmission lines for divided transmission of the information example.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a digital transmission device according to a first embodiment of the present invention. FIG. 2 is a diagram showing the format of an information string. FIG. 3 is a block diagram of a digital transmission device according to a second embodiment of the present invention. FIG. 4 is a diagram showing the format of the information string. FIG. 5 is a block diagram of a conventional digital transmission device. 1... Sending side device, 2... Multiplexing conversion device, 4...
・Transmission line selection switch, 5... Current transmission line, 6...
Backup transmission line, 7... Receiving side device, bit synchronized circuit, 15... Phase locked loop, 16.20.29.
...Control circuit, 18...Flip-flop, 19...
・Variable length delay memory, 21...Bit comparison circuit, 24
... Frame synchronization circuit, 25... Phase difference detection circuit between frame pulses, 26... Delay difference detection circuit, 27...
Addition circuit, 28... Variable delay circuit, 41... Elastic store memory, 42... Station clock source, 4
3...Cross connect switch, 44...Cell same X
ll pattern insertion circuit, 45... cell synchronization circuit, 48.
...Cell phase pulse-to-cell phase difference detection circuit. Patent applicant: Nippon Telegraph and Telephone Corporation Representative Patent attorney: Naotaka Ide

Claims (1)

[Claims] 1. A device comprising: means for transmitting the same digital information string over two transmission paths; and measuring means for measuring, on the receiving side, the difference in the amount of delay between the information strings caused by the two transmission paths. In the transmission delay difference measurement method, the measuring means includes synchronizing means for matching the phases of transmission units in which one unit is a time shorter than the difference in the amount of delay for the two information streams respectively received from the two transmission paths; a delay means for shifting the phases of the two information streams by a transmission unit; a control means for controlling the amount of delay of the delay means so that the two outputs of the delay means have the same value; A transmission delay difference measuring method comprising: an adding means for adding the phase adjustment amount by the means and the delay amount controlled by the control means and outputting the difference between the delay amounts of the two transmission paths.