JP3178910B2 - Layout design equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout and wiring design system for arranging layout elements such as cells on an integrated circuit or a printed circuit board and wiring the layout elements, and more particularly, to a simulated annealing method. And a layout design apparatus that determines the layout of layout elements related to layout wiring.

[0002]

2. Description of the Related Art Arranging elements such as cells on an integrated circuit or a printed circuit board must be arranged so that the arranging elements of cells are integrated at a high density as much as possible, and further, wiring cost is as low as possible. There is a demand for a system that can quickly perform layout design that satisfies such complicated requirements even for large-scale integrated circuits. A simulated annealing method is a method for performing such an arrangement as quickly and optimally as possible.

In the simulated annealing method, the state of the system is changed while reducing a parameter called a temperature parameter with reference to the energy defined for the state of the system, and the energy is reduced as much as possible. This is a method to determine the state of the system.

As described above, the placement of the placement elements must be performed in a desirable manner in consideration of the degree of integration of the placement elements and the cost of wiring. The arrangement state of all the placement elements is called a configuration, and the amount to be minimized, which is calculated from the degree of integration of the placement elements in a certain configuration, the cost of wiring, and the like, is defined as the energy of the configuration. By defining such a definition and using a simulated annealing method so as to reduce the energy, a layout design desirable for wiring can be performed.

According to the simulated annealing method,
How to obtain a desirable configuration will be described in more detail. First, in step S1, an initial value is set for a temperature parameter. Second, step S
2 gives the placement element a suitable initial placement. Further, in step S3, virtual wiring is performed based on the current configuration, and in step S4, energy is calculated using the configuration and virtual wiring. Then, in step S5, an energy change when the arrangement of one arrangement element is changed is calculated.

Subsequently, in step S6, based on the energy change, it is determined whether or not to accept the new configuration by a procedure used for the simulated annealing method, and if it is accepted in step S7, If the new configuration is not accepted, the original configuration is made the current configuration. Then, the temperature parameter is decreased in step S8, and it is checked in step S9 whether the termination condition is satisfied. If not satisfied, the process returns to step S3. If satisfied, the current configuration is adopted as the layout design result. I do.

In the above-described processing, steps S4, S
5, S6, and S7 perform only one calculation for one movement. However, in most cases, this is performed a plurality of times, and the process S4. S5. S
6. S7. Is executed each time the movement is performed, the configuration accepted in the movement is obtained, and the temperature parameter is further reduced, whereby the arrangement that is the most efficient and efficient wiring can be obtained.

[0008]

According to the above procedure,
A layout design suitable for layout on an IC or a printed board and wiring is performed by the layout design method of layout elements of the simulated annealing method. However, in order to perform the layout design by such a layout design method, it is necessary to move one layout element to calculate the energy as described above, and it is necessary to move all layout elements to a target position. There was a problem of having a lot of time.

On the other hand, with the recent increase in the density of integrated circuits, a placement and routing design system is required to handle a large number of placement elements. Therefore, it takes more time for such a request, and there is a problem that the request cannot be practically used.

An object of the present invention is to provide an arrangement design apparatus for executing a simulated annealing method at a high speed.

[0011]

FIG. 1 is a block diagram of the present invention. The present invention relates to an apparatus for designing arrangement of arrangement elements by a simulated annealing method.

The main processing means 1 includes a plurality of auxiliary processing means (2-
In response to 1-n), information on selecting an arrangement element and moving it is sent to the plurality of auxiliary processing means to calculate the energy change in parallel, and the arrangement design result is obtained from the returned result. decide.

For example, the plurality of auxiliary processing units (2-1)
... 2-n), all of those that have been accepted as a result of the simultaneous processing are moved, and the processing is continued as a new arrangement. The plurality of auxiliary processing means (2-1 to 2-n) perform virtual wiring based on the configuration of the placement element and the placement change, and obtain an energy change with respect to the placement change. Further, if the energy change is negative or the energy change is positive, a random number r between 0 and 1 is generated. When r <exp (−ΔE / T), the arrangement element, for example, the LSI The movement of the constituent cell is received. Further, the result is sent to the main processing means 1.

[0014]

The information moved by selecting a cell as an arrangement element by the main processing means 1 is transferred to a plurality of auxiliary processing means (2
-1 to 2-n). The movement of the selected cell is different depending on the auxiliary processing means. The auxiliary processing means (2-1 to 2-n) receiving this performs virtual wiring based on the configuration of the placement element including the movement, obtains an energy change thereof, and returns it to the main processing means 1.

When the main processing means 1 sends a result indicating that the auxiliary processing means (2-1 to 2-n) has accepted the cell movement based on the result, for example, it performs all the movements. The information obtained by selecting and moving the cells corresponding to the other arrangement elements corresponding to the respective elements is transmitted, and the processing of the auxiliary processing device described above is executed again.

By this repetition, the auxiliary processing means can perform operations relating to the processing of the simulated annealing method in parallel, and the processing can be speeded up.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings. FIG. 2 is a configuration diagram of an embodiment of the present invention. This embodiment is an apparatus for designing the arrangement of cells in a gate array. It should be noted that the cells of the gate array performed by the layout design apparatus are arranged on the gate array so as not to eventually overlap each other. Each of these cells has several terminals, which are connected to terminals and input / output terminals of other cells by wiring.
Further, since cells are not allowed to overlap each other at the end of the layout design, the overlapping of cells is a large cost.
Also, there is a desirable distance in the wiring connecting the terminals, and a deviation from the distance is a cost of the wiring. Further, it is impossible to perform wiring that is too crowded, and the wiring density is also a cost. Under the above conditions, in the embodiment of FIG. 2, the energy of a specific configuration can be obtained from these costs.

The main processing unit 10 includes auxiliary processing units 20a and 20a.
. 0b,... The main processing unit 10 includes an arithmetic unit 11, a wiring element storage unit 12, a configuration storage unit 13, a virtual wiring storage unit 14, a temperature parameter storage unit 15, and a virtual wiring unit 16. In addition, although not shown, a control unit for controlling the auxiliary processing device is additionally provided. The auxiliary processing units 20a and 20b include arithmetic units 21a and 21b, arrangement element storage units 22a and 22b, configuration storage units 23a and 23b, virtual wiring storage units 24a, and
24b, temperature parameter storage means 25a and 25b, and virtual wiring means 26a and 26b. The devices and means in the auxiliary processing devices 20a and 20b are the same as the devices and means in the main storage device 10. Although not shown, the main processing unit has a control means (not shown), which controls all the auxiliary processing units.

When the information of the placement request is added via the communication line 30, the main processing unit 10 and the auxiliary processing units 20a and 20a
The arrangement element storage means 12, 22a, and 22b in b stores the arrangement information of all the input cells. Subsequently, the initial configuration is stored in the configuration storage unit 13 in the main processing device 10 in the temperature parameter storage unit 15.
Stores the value of the initial temperature parameter (T). The control means sends all the contents of the configuration storage means 13 and the temperature parameter storage means 15 in the main processing device 10 to the auxiliary processing devices 20a and 20b via the communication line 30, and the respective configuration storage means 23
a, 23b and the temperature parameter storage means 25a, 25b store the same information. Each auxiliary processing device 20a, 20b
In addition, the main processing unit 10 reads the information, that is, the configuration information stored in the configuration storage units 13, 23a, and 23b, and the virtual wiring units 16, 26a perform virtual wiring. Then, the results are stored in the virtual wiring storage means 14, 24a, 24b, respectively. Since this is the same information, the result obtained via the communication line may be sent to the virtual wiring storage means 24a, 24b in the auxiliary processing devices 20a, 20b.

The control means in the main processing unit 10 is a communication line 30
Are arbitrarily selected as many as the number of auxiliary processing devices 20a, 20b,... Connected to each other, and a destination of each cell is generated. Then, the information is transmitted to the auxiliary processing devices 20a, 20b,... Corresponding to the selected one cell.

The auxiliary processing unit is generated when the cells transferred from the main processing unit 10 to the configuration currently stored in the configuration storage units 23a and 23b are moved to the destination and virtual wiring is performed. Calculate the energy change ΔE. This change in energy is an operation corresponding to the simulated annealing method. If these energy changes ΔE are negative, they are accepted as a new configuration. Otherwise, a uniform random number γ in the (0, 1) section is generated, and γ <exp (−ΔE / T). Accept if not, otherwise not. And
These results are sent to the processing device 10 via the communication means 30.

The main processing unit 10 includes a plurality of auxiliary processing units 20.
a, 20b... The next configuration is determined from the results input from. The configuration to be performed next is, for example, the auxiliary processing devices 20a and 20b.
.. May be accepted, or the movement of the highest weighted cell may be accepted. Furthermore, a plurality may be accepted. For example, one having the least energy difference is received. Alternatively, the actual movement is performed only for a certain number of the wiring elements of the wiring elements that have been received at the same time. As a result, it is possible to sufficiently reduce the error with respect to the amount of energy change caused by considering the movement of a plurality of wiring elements at the same time.

Then, again, the same number of cells as the auxiliary processing device are selected, the destination is generated, and the information of the selected cell and the destination is individually stored in the auxiliary processing device 20a, 20a in the same manner as described above.
.. through the communication line 30 and the above-described operation is repeated. When these processes are completed for all the cells by this repetition, the control means in the main processing device 10 stores the newly determined configuration corresponding to the previously determined temperature parameter T in the configuration storage means 13. I do. Then, αT is stored in the temperature parameter storage unit 15 as a new temperature parameter T. Here, α is a value satisfying 0 <α <1. Here, performing a new temperature parameter T is the content of the T _{fina l} than again if a large configuration storage unit 13 auxiliary processor 20a, 20b, and sent to ... again above the same process. The temperature parameters become lower than T _final by sequentially calculating in this manner. At this time, the contents stored in the configuration storage unit 13 become the layout design results. Note that this temperature parameter T
Is used when seeking energy.

In the above-mentioned operation, the arithmetic unit 11 and the virtual wiring means 16 in the main processing unit 10 are the same as the auxiliary processing units 20a and 20b. It is also possible to perform parallel operation of one device.

The above-described cell selection is performed for a random number or a cell that is more than a specified distance from the current position and the position after the movement. That is, the cells are selected so that cells smaller than a certain distance are not included.

FIG. 3 is a more detailed block diagram of the embodiment of the present invention. The main processing unit 100 includes an arithmetic unit 101, a cell list storage unit 102, a pin list storage unit 103, a net list storage unit 103, a connection list storage unit 104, a cell arrangement list storage unit 106, a temperature parameter storage unit 107, and a moving cell storage unit. 108, a cell selection unit 109, a cell destination generation unit 110, and a cell arrangement change unit 111. Also, the auxiliary processing devices 200a, 20
0b denotes arithmetic devices 201a, 201b, cell list storage means 202a, 202b, pin list storage means 203a,
203b, netlist storage means 204a, 204b,
Connection list storage means 205a, 205b, cell placement list storage means 206a, 206b, placement and wiring storage means 207a, 207b, temperature parameter storage means 20
8a and 208b, virtual wiring means 209a and 209b, and cell arranging means 210a and 210b.

In the embodiment shown in FIG. 3, the arrangement at the time of arrangement and wiring of the gate array is determined. The gate array is composed of an IO terminal area PX and an arrangement wiring area LX as shown in FIG. The layout wiring area LX includes a cell C composed of a plurality of basic cells BC, a pin P to be connected to another cell provided in the cell, and a wiring L connecting those pins. In the placement and routing, a list showing the structure of those cells and a cell list, a pin list, a net list, a connection list,
It is composed of a cell arrangement list.

FIG. 5 is a diagram showing a cell list, FIG. 6 is a diagram showing a pin list, FIG. 7 is a diagram showing a net list, FIG. 8 is a diagram showing a connection list, and FIG. 9 is a diagram showing a cell arrangement list. . The cell list stores the pin number and the number of pins of the pin corresponding to the cell number.

The pin list stores the pin numbers, net numbers, and cell numbers corresponding to the cell numbers described above in association with each other. If the cell number is 1, the pin number is 1, and the number of pins is 3, the numbers 1, 2, and 3 in the pin list are the pins of cell 1.

The net list stores the net number, the connection number, and the number of pins in association with each other, and indicates the connection number and the number of pins for one net number 1. By finding the number in the connection list corresponding to this connection number, the pin to be connected to is found. The connection numbers are the same as the above-mentioned net numbers. For example, if the net number is 1, the connection number is 1, and the number of pins is 3, the connection numbers 1, 2, and 3 in the connection list correspond to the net number 1. This is a connection, and the connection list indicates the pin numbers of the pin list. These represent the connections of each cell. Further, the cell arrangement list indicates the arrangement position of the cell number by the X coordinate and the Y coordinate.

The above cell list, pin list, net list, connection list, and cell arrangement list are stored in the main storage device 100, the cell list storage means 102, 202a, 202b, and the pin list storage means 103, 203a of the auxiliary processing devices 200a, 200b. , 203b, net list storage units 104, 204a, 204b, connection list storage units 105, 205a, 205b, and cell arrangement list storage units 106, 206a, 206b. For example, cells C1, C2,
The pins P1, P2, and P3 are provided on C3, and when they are connected, the pin number P1 is provided corresponding to the cell number C1 on the cell list. FIG. 10 is an explanatory diagram of the virtual wiring. If the cell C1 has, for example, only P1, the number of pins is 1. This is the cell number C1, C
3, the pin numbers P2 and P3 are similarly set.
The values of the pin numbers P1, P2, and P3 correspond to the pin list, and by finding the net numbers corresponding to the pin numbers of P1, P2, and P3, it becomes clear that the order of the net is. . For confirmation, the cell number can also be obtained in reverse from the pin. And
When the net number is designated from the net list, the connection number and the number of pins are clarified, and the relationship between the pin number and the connection is clarified by obtaining the connection numbers for the number corresponding to the connection number. It can be seen that pins P1, P2, and P3 are connected. Then, the positions of those cells are known from the cell arrangement list.

FIG. 11 is a processing flowchart of the main processing unit, and FIG. 12 is a flowchart of the auxiliary processing unit. 1
The main processing unit 100 first executes the process of designing the layout of the LSIs of one gate array. Main processor 100 stores the cell list sent in response to the request in cell list storage means 10.
2 is stored in step S30. Subsequently, the pin list is stored in the pin list storage unit 103 in step S31.
Subsequently, the netlist is stored in the netlist storage means 10.
4 is stored in step S32. Then, the connection list is stored in the connection list storage means 105 in step S33. For example, such information is stored in the communication line 300.
It is added through. At this time, the auxiliary processing device simultaneously stores the cell list, the pin list, the net list, and the connection list in steps S50 to S53, respectively, in the cell list storage units 202a and 202b, the pin list storage units 203a and 203b, and the net list storage unit 2.
04a, 204b, connection list storage means 205
a, 205b.

The main processing unit 100 then proceeds to step S34
Random arrangement of cells in the cell arrangement list storage means 10
6 is stored. This is a completely initial arrangement, and the movement of the cell is performed sequentially thereafter. In the initial state, the initial temperature is stored in the temperature parameter storage means 10 in step S35.
7 is stored.

Subsequently, each of the auxiliary storage devices 200a, 200
b to the cell arrangement stored in step S34 in step S3.
Send at 6. This is the auxiliary processing device 200a, 200b
At step S54. Note that FIG.
Terminals A1 to A4 in FIG. 12 are terminals representing the flow of data between the drawings.

Then, main processing unit 100 proceeds to step S3.
In step 7, the contents of the temperature parameter storage means 107 are transferred to the auxiliary processing device, and the auxiliary processing devices 20a and 20b execute step S5.
At 5, the value of the temperature parameter is received via the communication line 300 and recorded in the temperature parameter storage means 208a, 208b. Further, in order to obtain a change in energy in the auxiliary device, a cell to be operated for each cell is determined in step S38.
Choose by. This selection is made by the cell selection means 109.

The destination of the selected cell is obtained by the cell destination generating means 109 in step S39. The cell selection means 108 and the cell movement destination generation means 109 instruct the movement of cells related to the conventional cell list, pin list, net list, and connection list.
These are generated for the number of auxiliary processing devices 200a, 200b,. Then, in step S40, the communication line 300
, The information on the cell and its destination is sent one by one to each of the auxiliary processing devices 200a, 200b,.

Each auxiliary processing device 200a, 200b to which the contents of the temperature parameter storage means have been transferred in step S37.
Is the parameter storage means 208a, 20 in step S55.
8b. Subsequently, the cell placement means 210a, 210
b executes the cell arrangement in step S56, the virtual wiring storage means 209a and 209b execute the virtual wiring for that position in step S57, and
The obtained virtual wiring results are stored in a and 207b.

Thereafter, when the destination cell and the information of the destination obtained in the processing of step S40 of the main processing unit 100 are received in step S58, the flow proceeds to step S5.
In step S59, the energy change ΔE is recorded in the placement and wiring storage means 207a and 207b, and the virtual wiring is performed in the virtual wiring means 209a and 209b and the energy change ΔE when the cell is moved to the destination is calculated in step S59. This calculation is performed by the arithmetic unit 2 in the auxiliary processing units 200a and 200b, respectively.
01a and 201b. The energy change in step S50 is the difference between the energy up to now and the energy at the destination, and the energy is obtained as follows.

If the energy of a certain arrangement is E,
E becomes _{E = E0 + L 1 E 1} + L 2 E 2. Here, E0 is the contribution due to the overlapping of cells, and the cost when k cells overlap in one basic cell when the cells are arranged is ε _k (i> j → ε _i > ε _j ).
It is obtained by summing up this cost over all overlapping basic cells.

E1 is obtained by performing virtual wiring in terms of the wiring length. E2 is a contribution due to the degree of congestion of the wirings. Virtual wiring is performed to divide the arrangement wiring area into certain cells, and in each small area, the number of wirings in the vertical direction and the number of wirings in the horizontal direction are counted. The cost is determined by adding a predetermined cost according to. L1, L
2 is a value empirically adjusted with a positive coefficient.

FIGS. 13 and 14 are diagrams for explaining the energy calculation. As described above, the calculation of the contribution to the energy due to the overlapping of the cells and the calculation of the contribution by the wiring length and the degree of congestion of the wiring by the virtual wiring are described. FIG.
When the cells overlap as shown in (1), the cost is changed corresponding to the overlap. That is, the weighting is changed. Further, each block is divided into squares as shown by the dotted line in FIG. 14, and the number of wirings in the vertical direction and the number of wirings in the horizontal direction are counted and obtained in each small area.

As described above, the energy is obtained, and the energy change ΔE upon further movement is obtained. Then, the arithmetic units 201a, 201 of the auxiliary processing units 200a, 200b
In step 1b, if ΔE is negative in step S60, the cell movement is accepted. If not, a uniform random number r in the [0, 1] section is generated. If r <exp (−ΔE / T), Accepted, otherwise perform unaccepted processing. Then, the result is transmitted in step S61.

After this step S61, the auxiliary processing devices 200a and 200b send a signal from the main processing device 100 to step S3.
If the cell arrangement list is newly received in step S6, step S54 is performed, and if information on the cell and its destination is received in step S40 of the main processing unit 100, step S58 is executed.

On the other hand, when the auxiliary processing device transmits whether or not it has been received due to a change in energy in step S61, the main processing device receives the result in step S41, and the movement is received by the mobile cell storage means 108. Record the cell and its destination. Then, it is determined in step S42 whether the movement has been completed for all cells. If not, the process is executed again from S38. It should be noted that the cell arrangement is changed by the cell arrangement changing means 110 with respect to the received cell arrangement. By repeating this, the auxiliary processing devices 200a, 200
In b, steps S58 to S61 are repeated. Then, when the examination of all the movements is completed (YES), the contents of the storage means 106 storing the cell arrangement list are changed by the cell arrangement change means 111 based on the record in the storage means 108 of the moving cell in step S43. .

Subsequently, the temperature parameter T used so far is
αT multiplied by α as a new temperature parameter T
It is stored in the parameter storage means 108 in step S44.
Then, in step S45, the temperature parameter T becomes T
_finalTo determine if it is greater than
Step S36 is executed. If larger, repeat from S36
Since the execution is executed, the contents and temperature
Parameters are sent out, as described above.
Cell processing and auxiliary processing equipment
It is done. This processing is sequentially performed on the main storage device 1
00 and the auxiliary storage devices 200a, 200b
The temperature parameter finally becomes T _finalLess than
, And the entire process ends. The arrangement obtained at this time is the best
The arrangement is low in energy.

Although the present invention has been described in detail, the present invention is not limited to FIGS. 11 and 12. For example, the main processor 100 performs the same operation as the auxiliary processors 200a and 200b, and Parallel processing may be performed with n + 1. Further, the main storage device 100 and the auxiliary storage devices 200a and 200b each include one computer, and are connected to the main processing device 1 via a network which is a communication line.
00 may transfer data to each computer, perform those operations by the computer, and return the data to the computer as the main processing unit 100, thereby performing the target processing in parallel.

[0047]

As described above, according to the present invention, the movement of a plurality of wiring elements can be considered simultaneously by a plurality of auxiliary processing devices, and the time required for layout design can be greatly reduced as compared with the related art. can do. Further, if the actual movement is performed only for a certain number of wiring elements among the wiring elements that have been received at the same time, the error with respect to the energy change amount caused by considering the movement of a plurality of wiring elements at the same time can be sufficiently reduced. Can be small.

[Brief description of the drawings]

FIG. 1 is a block diagram of the present invention.

FIG. 2 is a basic configuration diagram of an embodiment of the present invention.

FIG. 3 is a more detailed explanatory view of the embodiment of the present invention.

FIG. 4 is a configuration diagram of a gate array.

FIG. 5 is a configuration diagram of a cell list.

FIG. 6 is a configuration diagram of a pin list.

FIG. 7 is a configuration diagram of a net list.

FIG. 8 is a configuration diagram of a connection list.

FIG. 9 is a configuration diagram of a cell arrangement list.

FIG. 10 is an explanatory diagram of virtual wiring.

FIG. 11 is a processing flowchart of a main processing device.

FIG. 12 is a processing flowchart of an auxiliary processing device.

FIG. 13 is an explanatory diagram of energy calculation (calculation of contribution by overlapping cells to energy).

FIG. 14 is an explanatory diagram of energy calculation (wiring length by virtual wiring and contribution by the degree of congestion of wiring).

[Explanation of symbols]

 1 main processing means 2-1, 2-2, 2-n auxiliary processing means

Continuation of the front page (56) References JP-A-3-82056 (JP, A) JP-A-2-162465 (JP, A) JP-A 1-273179 (JP, A) Seiichi Koakutsu, Hironori Hirata, " Parallel Processing of Improved Annealing Method with VLSI Block Placement Problem as an Example ”, Proceedings of the 1994 IEEJ National Convention, March 1994, p. 13-19 to 13-20 (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 17/50 H01L 21/82 H05K 3/00 JICST file (JOIS)

Claims (4)

(57) [Claims] 1. An apparatus for designing placement of placement elements by a simulated annealing method, wherein each auxiliary processing means performs virtual wiring from one configuration of the placement elements, and independently performs processing for obtaining a change in energy. A plurality of auxiliary processing means (2-1 to 2-n) to be performed in parallel; and a layout element selected by selecting different layout elements corresponding to the plurality of auxiliary processing means (2-1 to 2-n) And a main processing means (1) for sending information on the movement to the plurality of auxiliary processing means to cause each of the auxiliary processing means to calculate an energy change in parallel, and determining a layout design result from the returned result. An arrangement design apparatus characterized by comprising: 2. The auxiliary processing means (2-1 to 2-n).
If the energy change is negative or the energy change is positive, a random number between 0 and 1 is generated and the value is the value obtained by dividing the energy change obtained above by the temperature parameter and inverting the sign. 2. The layout design apparatus according to claim 1, wherein when the result is smaller than the result of taking the sensual, the movement of the cell is accepted and transmitted as a result to the main processing means (1). 3. The main processing means (1) moves all or at least one of the plurality of auxiliary processing means (2-1 to 2-n) which have been accepted as a result of simultaneous processing and moves the auxiliary processing means (2-1 to 2-n). 3. The arrangement design apparatus according to claim 2, wherein the processing is continued as a new arrangement. 4. The method according to claim 1, wherein the current and post-movement positions of the respective arrangement elements which are to be considered by the auxiliary processing device for movement are not included below a certain distance. 4. The layout design apparatus according to 2 or 3.