JP3422839B2 - Logic cell division processing method for semiconductor integrated circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout design of a semiconductor integrated circuit designed by a gate array system or a standard cell system, in which cells or blocks are formed by using a computer. The present invention relates to a method for dividing a logic cell of a semiconductor integrated circuit to be automatically arranged. 2. Description of the Related Art In a semiconductor integrated circuit device, cells or blocks having a logical function or a memory function are arranged in a chip so that a desired circuit operation can be obtained, and wiring between input and output terminals is performed. It is configured. FIG. 5 shows a schematic configuration of a semiconductor integrated circuit chip using a general gate array system.
On the chip, an area 51 where cells are arranged, an area 52 where wiring between cells is provided, and an area 53 where peripheral input / output circuits are arranged are arranged. In general, a plurality of wiring layers can be used for wiring, and different layers are generally assigned to horizontal and vertical wirings. In such a layout design of a semiconductor integrated circuit, the usual design technique is to automatically optimize the arrangement of cells and the wiring between terminals by using a computer, and perform an arrangement process using a computer. When the cell arrangement is determined by the fact, it is necessary to determine the cell arrangement position so that the subsequent wiring processing becomes easy. For example, an appropriate evaluation function is set for the purpose of minimizing the virtual wiring length and equalizing the degree of wiring congestion, and optimizing the cell arrangement position. In a placement process by a computer, a final placement position of a cell is usually determined by an initial placement phase for determining an initial state of placement and a subsequent sequential placement improvement phase. [0005] In the initial placement phase, a process of dividing a set of logic cells to be placed on a chip and allocating the set to a chip area is required. At present, various layout optimization methods are used in such a process. Among them, assuming that relatively good performance can be obtained, the division into two parts is advanced from the top down to divide the logic cells. There is a way to decide. This involves setting a cut line on the chip, dividing and assigning a set of logic cells to be placed so that the number of nets passing through the cut line is minimized, and determining the final cell placement position. This is a typical arrangement method of the logic cells by the cut arrangement, and it is generally said that good performance is obtained. Also,
In the mini-cut placement method for determining the division of a logic cell by proceeding such a two-partitioning process from the top down, Termi
nal Propagation (IEEE Tran
Sactions on Computer-Aide
dDesign, Vol. CAD-4, No. 1, Ja
Nuary 1985, "A Procedure f
or Placement of Standard-
Cell VLSI Circuits ”) is propagated to the terminal to the lowest division level to improve the final division performance. However, as can be seen from the division example in FIG. There are many issues to consider, such as variations in the size of each cell and the number of cells in the division, and the occurrence of imbalance in resources that can be a cell allocable area on a chip matrix. Even if terminal propagation is provided, when a set of divided logic cells is further recursively divided, a set of mutually interfering logic cells is optimally divided as long as each division is handled independently. That is, there was a problem that the state was locally optimized depending on the initial solution and no further improvement could be expected. Use will be described more specifically. FIG. 2 is already set of cells allocated is divided into four divided regions, and further divided into two based on the cutting line that is set on the chip shown in dashed lines,
The figure shows a state in which cells are divided and allocated to eight divided areas. In this figure, circles indicate cells, and solid lines connecting them indicate connection relationships between cells. In this example, it is actually possible to obtain an optimal division result as shown in FIG. 3 from a global perspective, and the number of nets passing through the cut line indicated by the dotted line should be minimized to four. is there. However, in such a division process, for example, the uppermost two-division process is performed first, and the lower-stage two-division process is repeated one after another while propagating the terminal. As a final result after the two divisions of (2) have been completed, a locally optimum arrangement state as shown in FIG. 2 is obtained. That is, it is difficult to optimize the division of each set of logical cells that interfere with each other even if the adjacent information of the already divided areas is inherited, and even if the constraints are propagated, the arrangement result as shown in FIG. After convergence, the optimal arrangement state as shown in FIG. 3 could not be obtained. [0007] As described above,
Conventional division method already proposed for automatic placement,
In other words, in an optimization method such as a mini-cut placement method in which the layout is optimized by repeating top-down of two divisions of a logical cell, as the division proceeds, the number of cells to be divided halves in a geometric progression, There is an advantage that the processing time generally decreases as the number of later divisions increases,
If the lower level division does not inherit the restrictions imposed by the upper level division, the performance deteriorates remarkably, and even if inherited, there is a problem that global optimization over the entire chip cannot be achieved. The present invention has been devised in order to solve such a problem, and provides a method of globally optimizing by mutually adjusting a division process of a set of logical cells that interfere with each other. It is an object. According to the present invention, there is provided a logic circuit to be arranged on an LSI chip when automatically arranging cells using a computer in a layout design of a semiconductor integrated circuit. In dividing and assigning a set of cells to a plurality of regions in a chip, a computer divides the LSI chip into two divided regions by a cut line, and the computer divides the two divided regions by a cut line. Dividing into a plurality of divided holding areas in a direction perpendicular to the direction, and holding a divided state and a provisional arrangement state between these divided holding areas, and a computer, while holding the divided state, the divided holding area Is performed for each of the cells, the cell is divided into two cells by moving the cell in which the number of nets passing between the divided areas is the smallest. Updating the placement state, and the computer repeating the two-partitioning process based on the updated placement state, wherein the two-partitioning process is performed by the computer by arranging cells in a target area on a chip. Calculating the possible area, the computer calculating the sum of the areas of the allocated cells, and calculating the cell filling rate in the target area by the computer based on the sum of the cell allocable area and the area of the cells. And the computer selects the target region on the side with the higher cell filling factor. The computer determines that the number of nets passing between the divided regions from the cells in the selected region is reduced most by the movement of the cell. Moving the cell to be performed, and wherein the computer selects the target area on the side with a higher cell filling rate, the computer performs the following steps: cell Cell filling factor of the divided holding region is characterized by selecting a region higher than Hamaritsu. In a method of automatically arranging a plurality of cells on a semiconductor substrate by using a computer, by providing a means defined by the present invention, a set of logical cells which interfere with each other is divided. It is possible to adjust the processing well with each other to achieve global optimization. An embodiment of the present invention will be described below. FIG. 1 is a flowchart showing a schematic processing procedure of the present invention. The detailed processing procedure for realizing this is described in the form of detailed processing steps step0 to step14 at the end of the embodiment. Hereinafter, an embodiment of the present invention will be described in accordance with the flow of the flowchart of FIG. 1 using the above-described FIGS. 2 and 3 and the detailed processing procedures step0 to step14. After (START), first, the chip area of the LSI is divided into two by a cut line to form a left area and a right area of the cut line. This is hereinafter referred to as a divided area. Further, these two divided areas are decomposed into divided holding areas opposed to each other with the cut line interposed therebetween, cells in each of the divided holding areas are temporarily determined, and registered as an initial arrangement state. Such an initial arrangement state may employ, for example, a random cell arrangement. For example, the example of FIG. 2 shows that a divided area divided into two by a cut line indicated by a dotted line is divided into four in the horizontal direction and decomposed into four divided holding areas. Then, when performing the two-division improvement process based on the cut line of interest, the division state between the divided holding areas is preserved. [0012] Then, resulting cells each on both sides of the divided holding region of the initial divide based on cut line calculates the resource R _n of possible arrangement area (st
ep0), the degree of improvement G from the registered arrangement state is set to 0
(Step 1). The degree of improvement is, for example, the number of nets passing through the cut line. [0013] Next, to calculate the sum S _n of the area of cells assigned for each sides of the divided holding area of the cut line (step2). Next, step0, s
both sides of the divided holding regions each cell filling factor of the sum S _n cut from the line of the area of the calculated cell the cell is allocated with the resource R _n of the possible placement area tep2 F _n
Is calculated by the following equation (step 3). [0014] Equation 1] by summing the F _n = S _n / R _n then the cell filling factor F _n compares the both sides of the divided regions of the cut line, obtains a high cell fill factor of the divided region side H (Step 4). According to the above procedure, it is determined which cell of the cut line is a movement target candidate when performing division improvement (S1). Here, for example, in the example of FIG. 2, the area on the left side of the cut line is selected. [0015] Then the cell fill factor of between opposing divided holding regions across the cutting line respectively compared obtains the divided holding area A _m of higher (step5), ste from this
Those existing on the side H with the higher filling factor of the divided regions obtained in p4 are extracted and set as divided improved region candidates C _k (step
6). In this way, which divided holding area on which side of the cut line is a target candidate for performing the division improvement is determined (S2). Here, for example, in the example of FIG. 2, the divided holding areas of the first row (Y1 in the figure) and the second row (Y2 in the figure) from the top on the left side of the cut line are the target candidates. Next, from among the cells allocated to the division-improved area candidate C _k extracted in step 6, the cell M in which the number of nets passing between the areas to be divided decreases most by the movement of the cell is selected. (Step 7). By selecting such a cell, it is determined which divided holding region on which side of the cut line is a target region for performing division improvement, and the degree of reduction in the number of cuts (gain G) is also determined (S3, S4). Here, for example, in the example of FIG. 2, the division holding area (Y2 in the figure) in the second row from the top of the area on the left side of the cut line is determined as the target area for division improvement. Next, assuming the movement of the cell M selected in step 7, the number of nets passing between the areas to be divided from the cells in the division improvement area candidate C _k connected to this cell by a net. Selects a cell that decreases the most due to the movement of the cell, and recursively repeats a series of steps of assuming the movement of the cell, thereby obtaining a group N of cells assumed to move (step 8). This is a means for strengthening the improvement effect by moving the cells as a group when the division improvement effect is small by the single movement of the cell. Next, the cell M selected in step 7 or the cell group N obtained in step 8 is moved to the corresponding divided holding area with the cut line interposed therebetween to create a provisional arrangement state, and the reduction value of the number of cuts is created. Is accumulated G (step
9). Here, for example, in the example of FIG. 2, the cell 2 in the divided holding area (Y2 in the drawing) in the second row from the area on the left side of the cut line is divided and held in the second row from the area on the right side of the cut line. It will be moved into the area (Y6 in the figure). Next, if the cut number reduction cumulative value G of the arrangement state representing the degree of improvement in the division improvement process is equal to or greater than the maximum value of G in the improvement process up to the present, the registered arrangement state. Is updated (step 10). Thus, arrangement of the divided holding region as the object is updated is improved (S 5). Here, for example, in the example of FIG.
The movement of the cell 2 performed at p9 is determined and registered as a new arrangement state. Therefore, according to the present invention, the inside of the corresponding divided holding area in the second stage from the top in FIG.
The cell division state (in the area of No. 6) is improved to the cell arrangement result in the corresponding division holding area in the second stage from the top in FIG. Next, the above-described processing procedure step2-s
Step 10 is repeated until all the cells have been moved or until the accumulated value G falls below the lower limit of the preset value (step 11).
Thereby, for example, in the example of FIG. 2, the cell 1 in the divided holding area (Y1 in the drawing) in the first row from the top, and the cells in the third row (Y7 in the drawing) and the fourth row (Y8 in the drawing) from the top Cell 3 and cell 4
Are also moved into the opposing divided holding areas on the opposite sides of the cut lines, respectively, and are finally improved to the cell arrangement results as shown in FIG. That is, according to the present invention, even in the arrangement state as shown in FIG. 2, while maintaining the already divided horizontal division information, the four divisions in the vertical direction interfere with each other.
It can be optimized at the same time while reflecting. As a result, an ideal division result as shown in FIG. 3 is finally obtained. Finally, the convergence of this division processing is determined (S
6). First, if the maximum value of the number-of-cuts reduction cumulative value G in the arrangement state indicating the degree of improvement in the division improvement process is positive, the process returns to step 1 and the above processing procedure is repeated to further advance the division improvement (step 12). . Also, when the maximum value of the accumulated value G is 0 and there is a moving cell, and there is a cell having a positive gain among all the cells in the division improvement area candidate C _k , the stee is also set.
Returning to p1, the above processing procedure is repeated to further improve the division (step 13). The convergence determination in step 12 is performed, for example, according to W. KERNIGHAN and S.K.
LIN's “AnEfficient Heuristic
c Procedure for Partition
ing Graphs ", THE BELL SYST
EM TECHNICAL JOURNAL, FEBR
UARY 1970. May be adopted. When the convergence of the division improvement is confirmed by these convergence determinations, the division improvement processing ends (step 1).
4) (END). As described above, in the present embodiment, while retaining the already divided information, and further subdividing the set of the logic cells, the respective division improvement states are mutually reflected between the already divided areas. Optimization can be performed at the same time, and the quality of layout design can be improved. Note that the present invention is not limited to the above-described embodiment, and can be implemented with various modifications without departing from the spirit of the present invention. As described above, according to the present invention, in a layout design of a semiconductor integrated circuit, a logic cell is divided into two and a cell arrangement position is automatically determined using a computer. When performing the optimization, the subdivision processing of the cell set in each divided area should be optimized at the same time while interfering with each other between the divided areas, while maintaining the division state between the plurality of divided areas. This makes it possible to globally optimally divide a logic cell by mutually reflecting the optimization progress of the two-division process in each area, thereby realizing an improvement in the degree of integration of a semiconductor integrated circuit.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a flowchart showing a processing procedure according to an embodiment of the present invention. FIG. 2 is a schematic diagram for explaining a problem of the related art. FIG. 3 is a schematic diagram for explaining one embodiment of the present invention. FIG. 4 is a schematic view showing an example of division of a semiconductor integrated circuit. FIG. 5 is a plan view showing a schematic configuration of a semiconductor integrated circuit chip. [Explanation of Signs] S1 to S6 ... Processing step names. 51: Cell placement area. 52: Wiring area for signal lines. 53 ... I / O circuit arrangement area.

────────────────────────────────────────────────── ─── Continuation of the front page (56) References Takao Uehara and two other authors, Hiroshi Yamada, CAD of VLSI computer, Sangyo Tosho Co., Ltd., October 31, 1983, p. 77-80 Toshiaki Ueda, New Allocation Optimization Algorithm Based on Look-Ahead Search, Information Processing Society of Japan Research Report, Information Processing Society of Japan, October 8, 1990, Vol. 90, no. 81 (DA-54), p. 85-91 (58) Field surveyed (Int. Cl. ⁷ , DB name) G06F 17/50 658

Claims (1)

(1) When automatically determining a cell arrangement position using a computer in a layout design of a semiconductor integrated circuit, a logic cell to be arranged on an LSI chip is determined. In dividing the set into a plurality of regions in the chip and allocating the divided regions, a computer divides the LSI chip into two divided regions by a cut line; Dividing into a plurality of divided holding areas in a vertical direction, and holding a divided state and a provisional arrangement state between these divided holding areas; and a computer holding the divided state while holding the divided state. , A two-division process is performed to move the cell in which the number of nets passing between the divided regions is reduced by the movement of the cell, and the arrangement state is updated by the movement of the cell. And a computer that repeats the two-division processing based on the updated arrangement state. In the two-division processing, the computer calculates a cell allocable area in a target area on a chip. A step in which a computer calculates the sum of the areas of the assigned cells; and a step in which the computer calculates the cell filling factor in the target area based on the sum of the cell allocable area and the area of the cells. Is a step of selecting a target area on the side with a high cell filling rate,
A step of moving a cell in which the number of nets passing between the divided areas from the cells in the selected area is reduced most by the movement of the cell, wherein the computer has a higher cell filling rate. In the step of selecting the target area, the computer selects, from among the divided holding areas, an area having a higher cell filling rate in the divided holding area than the cell filling rate in the corresponding divided holding area in the two-split processing. A method for dividing a logic cell of a semiconductor integrated circuit.