JP3176313B2 - PLL synthesizer circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL synthesizer circuit used in a mobile communication device such as a cellular phone.

[0002]

2. Description of the Related Art Conventionally, a PLL synthesizer circuit has been used for a small base station or the like as a countermeasure for a blind spot in a mobile communication system. For example, Japanese Patent Application Laid-Open No. 5-335944 discloses a technique related to this kind of PLL synthesizer circuit. In this PLL synthesizer circuit, in a transmitter loop, an output signal output from a voltage controlled oscillator is input to a transmitter and a phase comparator, respectively, and a control voltage is input to a voltage controlled oscillator via a filter unit emphasizing transmission characteristics. To control the oscillation frequency.

Further, in the base station electric field monitoring receiver loop, power is always applied to the voltage controlled oscillator, consuming wasteful power, even though the base station electric field monitoring receiver is not operating. . Similarly, during operation of the base station electric field monitoring receiver, the output signal output from the power supply voltage controlled oscillator is input to the base station electric field monitoring receiver and the phase comparator, respectively, and the filter emphasizing the characteristics of the base station monitoring receiver is input. The control voltage is input to the voltage-controlled oscillator via the section to control the oscillation frequency.

[0004]

In the case of a mobile communication device that handles a plurality of frequencies as described above, a plurality of PLL synthesizer circuits are required, so that there are the following problems. The circuit scale becomes large. Since the power supply voltage is also applied to the non-operation-side voltage-controlled oscillator, wasteful power consumption is consumed. Interference due to spurious components or the like occurs between the PLL synthesizer circuits. When no operation is performed, the control voltage is not applied to the voltage control oscillator, so that the PLL cannot immediately follow the predetermined frequency.

The present invention has been made in view of the above-mentioned problems, and has the following objects. Reduce the circuit scale. Reduce power consumption. Reduces interference due to spurs. The convergence time of the oscillation frequency at the time of frequency switching is reduced.

[0006]

Means for Solving the Problems In order to achieve the above-mentioned object, as a first means, there is provided a first means in which one of them is brought into an operating state.
And a PLL synthesizer circuit provided with a second PLL loop, wherein a first voltage-controlled oscillating section and a second filter section constituting a first PLL loop are connected to a second voltage control section constituting a second PLL loop. By switching between the oscillating unit and the second filter unit, means for sharing the phase comparator and the reference oscillator between the first PLL loop and the second PLL loop is employed. As a second means, a means having excellent S / N characteristics is used for the first filter part, and a means having excellent high-speed switching characteristics is used for the second filter part. As a third measure,
When the first PLL loop is in operation, power supply to the second voltage controlled oscillator is stopped. When the second PLL loop is in operation, power supply to the first voltage controlled oscillator is stopped. A means of stopping the operation is adopted. 4th
Means for applying a control voltage to the inactive first or second filter section so as to improve the rising characteristics of the first or second voltage controlled oscillator when the apparatus shifts to the operating state. Means of including a generator is employed. As a fifth means, the control signal generator stores in advance a control voltage corresponding to a frequency to be set next in the inactive first or second voltage controlled oscillator, and stores the control voltage in the inactive state. Means for outputting to the first or second filter unit. As a sixth means, a means is employed in which the control signal generator outputs a control voltage of a pressure control oscillator to be set next based on information from a higher-level device. As a seventh means,
The control signal generation unit holds the control voltage output in the previous non-operation state, and outputs the control voltage held in the next non-operation state to the first or second filter unit in the non-operation state. Is adopted. As an eighth means, means applied to a mobile communication device is employed. As a ninth means, a means is adopted in which the first PLL loop is activated when the mobile communication device is in the receiving state, and the second PLL loop is activated when the mobile communication device is in the transmitting state. .

[0007]

With this configuration, the circuit scale is reduced by forming two PLL loops with one phase comparator, and the power supply voltage of the non-operating side voltage controlled oscillator is turned off by the control signal of the control unit to reduce power consumption. This has the effect of reducing power consumption, preventing interference due to spurious components or the like, and shortening the convergence time during switching.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of a PLL synthesizer circuit according to the present invention will be described with reference to the drawings. Note that the present embodiment relates to a PLL synthesizer circuit applied to a mobile communication device.

[1] Description of Configuration First, the functional configuration of the present embodiment will be described with reference to FIG. In this embodiment, a signal from a first oscillator is used as a local oscillator for a transmitter, and a signal from a second oscillator is used for a base station electric field monitoring for searching electric field levels of a plurality of uplink received waves at high speed. It is related to the case where it is used as a local oscillator of a receiver.

In the transmitter PLL loop 1 (first PLL loop), the phase comparator 2 always compares the phase difference between the reference signal 3 oscillated from the reference oscillating section 8 and the output of the voltage control oscillating section 4, The output signal 5 corresponding to the phase difference is switched to the switching unit 6
Is input to the filter unit 7 via. Filter part 7
Is a filter having excellent S / N characteristics, filters the output signal 5 switched by the switching unit 6, and inputs the filtered output signal 5 to the voltage control oscillation unit 4 as a control voltage 9. The voltage controlled oscillator 4 is an oscillator whose frequency is controlled by the control voltage 9, and its output signal 11 is input to the phase comparator 2 via the switching unit 12 and also to the transmitter 13.

On the other hand, the base station electric field monitoring receiver loop 19
When the mode is switched to the (second PLL loop), the phase comparator 2 always compares the phase difference between the reference signal 3 oscillated from the reference oscillating unit 8 and the output of the voltage control oscillating unit 16, and The corresponding output signal 5 is input to the filter unit 14 via the switching unit 6. The filter unit 14
Excellent filter with high-speed switching characteristics.
Is filtered and input to the voltage controlled oscillator 16 as the control voltage 17.

The voltage controlled oscillator 16 is an oscillator whose frequency is controlled by a control voltage 17, and its output signal 18
Are input to the phase comparator 2 via the switching unit 12 and are also input to the base station electric field monitoring receiver 20.

The power supply 31 applies a voltage for operating the switching unit 32, and the switching unit 32 receives a control signal 33 output from the control unit 22 and supplies a power supply 2 to each oscillation unit.
Control signals 26, 2 for turning ON / OFF the terminals 4, 25
7 is switched according to the operations of the transmitter 13 and the base station electric field monitoring receiver 20. The control unit 22 includes a control signal 23 for switching the switching unit 6 and the switching unit 12 to the operation side,
Control signal 37 for switching switching unit 38 to the non-operation side
And outputs a control signal 33 for switching the switching unit 32.

On the other hand, the control signal generator 40
8 is divided by resistors 29 and 30 to obtain a reference voltage 1
0 is output to the switching unit 38 as the control voltage of the non-operating oscillation unit.

FIG. 2 shows the control signal generator 40.
FIG. 13 is a block diagram showing another example of the configuration. In this figure, the control signal generator 40a includes a storage 35, a signal generator 36, and a D / A converter 39.
In the storage unit 35, for example, as shown in FIG. 3 or FIG. 4, the relationship between the frequency within the allowable range of the oscillation unit and the control voltage is stored in advance as data. Signal generator 36
Reads a voltage value corresponding to a frequency to be set next from the storage unit 35. The D / A converter 39 outputs a reference voltage 10 (analog value) based on a voltage value (digital value) corresponding to the frequency.
Is generated and charged by the non-operating side filter unit,
The rising characteristic of the oscillation unit after the switching operation is improved.

FIG. 5 is a diagram showing a modification of the control signal generator 40a. The control signal generating section 40b gives the CH information 34 from the host device to the storage section 35, reads out the voltage value corresponding to the frequency to be set next based on the data stored in the storage section 35, and performs the non-operation. To the oscillation unit on the side.

FIG. 6 is a block diagram showing still another example of the configuration of the control signal generator 40. As shown in FIG. As shown in this figure, the control signal generation unit 40c includes a signal generation unit 36
And a sample hold unit 41. The signal generator 36 reads the previously set voltage value after switching again. The sample hold unit 41 holds the previously set reference voltage 10 and outputs the same reference voltage 10 to the switching unit 38 after re-operation.

[2] Description of Operation Next, the operation of the PLL synthesizer circuit having such a configuration will be described. First, when the transmitter 13 operates, the switching unit 6 and the switching unit 12 are switched to the transmitter PLL loop 1 by the control signal 23 output from the control unit 22 to form a loop. In addition, the switching unit 32 controls the control signal 26 for turning on the power supply 24 of the voltage controlled oscillation unit 4 and the control signal for turning off the power supply 25 of the voltage controlled oscillation unit 16 by the control signal 33 output from the control unit 22. Signal 2
7 are output, and the voltage controlled oscillator 4 is operated and the voltage controlled oscillator 16 is stopped. By setting the operation state in this way, interference such as spurious noise can be avoided and power consumption can be reduced.

Further, in this state, on the non-operation side, that is, on the base station electric field monitoring receiver side, a fixed voltage 28 (for example, +5 V) constituted by the control signal generator 40 is provided so that the frequency can follow the frequency instantaneously during operation. The resistor 29 (for example, 2
By generating a reference voltage 10 (for example, +3 V) divided by a resistor 30 (for example, 3 kΩ) and a resistor 30 (for example, 3 kΩ) and applying the generated reference voltage to the switching unit 38, a use frequency (for example, f 4 to f 6: 900 MHz to At a point (for example, f5 = 910 MHz) within 920 MHz), it becomes possible to follow the frequency used instantaneously during operation.

On the other hand, when the base station electric field monitoring receiver 20 is operating, a control signal 23 output from the control unit 22 is output.
Accordingly, the switching unit 6 and the switching unit 12 are switched to the base station electric field monitoring receiver PLL loop 19 side to form a loop. Further, the switching unit 32 turns on the power supply 25 of the voltage controlled oscillation unit 16 by the control signal 33 output from the control unit 22.
Signal 27 for powering and the power supply 24 of the voltage control oscillator 4
A control signal 26 for turning off the signal is output to operate the voltage controlled oscillator 16 and stop the operation of the voltage controlled oscillator 4. Also in this state, it is possible to avoid interference such as spurious noise and reduce power consumption.

Further, in this state, on the non-operating side, that is, on the transmitter side, a fixed voltage 28 constituted by a control signal generator 40 so that the frequency can follow the frequency instantaneously during operation.
(For example, +5 V) and a resistor 29 (for example, 2 kΩ) and a resistor 3
By obtaining a reference voltage 10 (for example, +3 V) divided by 0 (for example, 3 kΩ) and applying it to the switching unit 38,
The operating frequency (for example, f1 to f3: 810) as shown in FIG.
MHz to 830 MHz) (for example, f2 = 8).
(21 MHz) at the time of operation.

When the PLL synthesizer circuit includes the control signal generator 40a, when the transmitter 13 is operating, the reception electric field monitoring receiver 20 on the non-operation side from the storage unit 35 sets the frequency to be set next. (For example, f8 = 912
MHz) (for example, V8 = 3.
By applying and charging 3V) to the filter unit 14 via the switching unit 38, it is possible to instantaneously follow the frequency used for convenience after the operation is switched.

In this case, when the base station electric field monitoring receiver 20 operates, the non-operating side transmitter 13 stores the next frequency (for example, f 7 = 820 M) from the storage unit 35.
Hz) (for example, V7 = 2.8).
V) is applied to the filter unit 14 via the switching unit 38.
By charging, the frequency used after the operation is switched can be instantaneously followed.

Further, when the PLL synthesizer circuit includes the control signal generator 40b, when the transmitter 13 operates, the CH information from the higher-level device (for example, the setting is performed when the base station electric field monitoring receiver operates). By setting the frequency to be performed to, for example, f10 = 905 MHz, the reference voltage 10 (for example, V10 = 2.6) shown in FIG.
V) can be input to the voltage controlled oscillator 16 via the switching unit 38 so that it can instantaneously follow the frequency to be used in the next operation.

Similarly, when the base station electric field monitoring receiver 20 operates, the CH information from the higher-level device (for example, the frequency set when the transmitter operates is f9 = 818 MHz).
z. ), The reference voltage 10 (for example, V9 = 2.6 V) shown in FIG. 3 is input from the storage unit 35 to the voltage control oscillation unit 4 via the switching unit 38, and instantaneously reaches the frequency to be used in the next operation. It is possible to follow.

Further, when the PLL synthesizer circuit includes the control signal generator 40c, when the transmitter 13 operates, as shown in FIG. 3, when the operating frequency is f7 (for example, f7 = 820 MHz). When the control voltage (e.g., V7 = 2.8 V) becomes inactive, the sample-and-hold unit 41 holds the voltage, and when operating again, the control voltage (e.g., V7 = 2.8 V) is switched. Part 3
8, it is possible to instantaneously follow the desired frequency.

Similarly, during the operation of the base station electric field monitoring receiver 20, as shown in FIG. 4, the control voltage (for example, V11 = 3.6 V) at the operating frequency (for example, f11 = 915 MHz), as shown in FIG. ) Is inactive, the sample-and-hold unit 41 holds the voltage, and when it operates again, the control voltage (for example, V11 = 3.6 V) is applied to the switching unit 38, thereby instantaneously. It is possible to follow the frequency to be used.

[0028]

As described above, according to the present invention, P
According to the LL synthesizer circuit, the following effects can be obtained. (1) Since the first or second filter section that satisfies each characteristic is selected using one phase comparator and a reference oscillator, the circuit scale can be reduced. (2) The power consumption of the non-operating side voltage controlled oscillator can be reduced by setting the power supply to a stopped state. (3) Interference due to spurious components between the first and second PLL loops can be suppressed. (4) Since the control voltage is applied to the PLL loop in the non-operating state, it is possible to instantaneously follow the used frequency when shifting to the operating state.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a functional configuration of an embodiment of a PLL synthesizer circuit according to the present invention.

FIG. 2 is a block diagram showing another configuration example of the control signal generator in FIG. 1;

FIG. 3 is a characteristic diagram showing Vf characteristics of the voltage controlled oscillator 4 in FIG.

FIG. 4 is a characteristic diagram showing Vf characteristics of the voltage controlled oscillator 16 in FIG.

FIG. 5 is a block diagram showing another configuration example of the control signal generator in FIG. 1;

FIG. 6 is a block diagram showing another configuration example of the control signal generator in FIG. 1;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Transmitter loop (1st PLL loop) 2 ... Phase comparator 3 ... Reference signal 4 ... Voltage control oscillation part (first voltage control oscillation part) 5, 11, 18 ... Output signal 6 , 12, 32, 38 Switching section 7 Filter section (first filter section) 8 Reference oscillator 9, 17 Control voltage 10 Reference voltage 13 Transmitter 14 Filter section ( Second signal filter 15 Signal 16 Voltage-controlled oscillator (second voltage-controlled oscillator) 19 Base station electric field monitoring receiver loop (second PLL)
(Loop) 20 base station electric field monitoring receiver 22 control unit 23, 26, 27, 33, 37 control signal 24, 25, 31 power supply 28 fixed voltage 29, 30 resistor 34 ... CH information 35... Storage section 36... Signal generation section 39... D / A converters 40, 40 a, 40 b, 40 c... Control signal generation section 41.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03L ⁷ /06-7/23 H04B 1/02-1/04 H04B 1/26 H04B 1/38-1 / 58 H04B 7/24-7/26

Claims (9)

(57) [Claims] 1. A first and a second one of which is set to an operation state.
A PLL synthesizer circuit having a PLL loop according to any one of the preceding claims, comprising: a first voltage-controlled oscillator forming a first PLL loop;
By switching the first filter unit to the second voltage controlled oscillator and the second filter unit forming the second PLL loop, the phase comparator and the reference oscillator are connected to the first PLL.
A PLL synthesizer circuit shared by an L loop and a second PLL loop, wherein the first filter section has excellent S / N characteristics and the second filter section has excellent high-speed switching characteristics. 2. When the first PLL loop is in operation, power supply to the second voltage controlled oscillator is stopped,
2. The PLL synthesizer circuit according to claim 1, wherein the power supply to the first voltage controlled oscillator is stopped when the second PLL loop is in an operating state. 3. A first and a second one of which is set to an operation state.
A PLL synthesizer circuit having a PLL loop according to any one of the preceding claims, comprising: a first voltage-controlled oscillator forming a first PLL loop;
By switching the first filter unit to the second voltage controlled oscillator and the second filter unit forming the second PLL loop, the phase comparator and the reference oscillator are connected to the first PLL.
A first or second filter in a non-operating state, shared by the L loop and the second PLL loop, so as to improve a rising characteristic of the first or second voltage controlled oscillator when the operating state is shifted to an operating state; Comprising a control signal generating section for applying a control voltage to the section.
L synthesizer circuit. 4. A control for applying a control voltage to a first or second filter unit in a non-operating state so as to improve a rising characteristic of the first or second voltage-controlled oscillating unit when shifting to an operating state. 3. The PLL synthesizer circuit according to claim 1, further comprising a signal generator. 5. The control signal generating section stores in advance a control voltage corresponding to a frequency to be set next in the non-operating first or second voltage controlled oscillator, and sets the control voltage to the non-operating state. 5. The PLL synthesizer circuit according to claim 3, wherein the output is outputted to a certain first or second filter unit. 6. The PL according to claim 3, wherein the control signal generator outputs a control voltage of a voltage control oscillator to be set next based on information from a host device.
L synthesizer circuit. 7. The control signal generator holds a control voltage output in a previous non-operation state and a first or second filter in a non-operation state of a control voltage held in a next non-operation state. 5. The PLL synthesizer circuit according to claim 3, wherein the signal is output to the PLL synthesizer. 8. The PLL synthesizer circuit according to claim 1, wherein the PLL synthesizer circuit is applied to a mobile communication device. 9. When the mobile communication device is in a receiving state, the
Second PLL loop is an operational state, PLL synthesizer circuit according to claim 8, wherein the first PLL loop is characterized in that it is an operating state when in the transmitting state.