JP3119027B2 - Coding method and decoding method and coding / decoding method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an encoding system, a decoding system, and an encoding / decoding system for suppressing a redundant portion of data such as character data and image data by using arithmetic coding.

[0002]

2. Description of the Related Art Arithmetic coding is known as one method applicable to data coding and data decoding. Generally, in arithmetic coding, an operation is performed in which an effective area is provided on a number line from 0 to less than 1 to divide the input symbol sequence into input symbol appearance probability ratios, and an effective area is assigned and updated for a new sequence. By using a binary decimal value in the effective area corresponding to the input symbol sequence as a code, it is possible to obtain high encoding efficiency as close as possible to entropy when the appearance frequency of the symbol is known or predictable.

[0003] For example, a description will be given using "JP-A-4-277933, data compression and decompression method". In the above publication, the encoding is compressed, the decoding is decompressed, the input symbol sequence is called input data or original data, the code sequence is called compressed data, and the output symbol sequence is called output data or decompressed data, but they are the same. In the conventional example, an appearance symbol obtained by inputting an input symbol sequence is a symbol that is difficult to appear (hereinafter referred to as a less probable symbol LPS: Less Probable Symbol; an appearance probability p of LPS) and a symbol that is likely to appear (hereinafter a superior symbol). MPS: More Probable Symbol
Called. The appearance probability of MPS is 1-p. ). False input when inferior symbol appears
(F), True input when dominant symbol appears
In the binary arithmetic coding of (T), the code is the lower limit value coordinate of the effective area. Also, the appearance probability p of inferior symbol 2 negative powers (= 2 ^-SK; SK is SKEW numbe
Here, it is assumed that r takes integers 1, 2, 3, and 4 here. )
In the effective area, the area for the inferior symbol is arranged lower than the area for the superior symbol.

[0004] Arithmetic coding is to repeat the following arithmetic operation up to the last input symbol, where A is the effective area width for the input symbol sequence s already coded and the input (T or F) to be coded, and C is the code. As a result, a code based on the lower bound of the effective area is obtained. Initial state A (null) = 1.0 C (null) = 0.0 Area operation (multiplication can be realized by shift operation) Inferior symbol area width: A (s, F) = A (s) × 2 ^-SK superior Symbol area width: A (s, T) = A (s) −A (s, F) Coding operation Less-than symbol encoding: C (s, F) = C (s) Dominant symbol encoding: C (s, T) = C (s) + A (s, F)

FIG. 8 shows the flow of the algorithm of arithmetic coding.
Shown in In the figure, C is a code register, B is an output buffer register for storing a code to be sent, A is an effective area width register, and MIN is a match between an input symbol and a predicted value (T).
SK is SKew number (1,
2, 3, 4). The SK value is compared with the input symbol and the predicted value, and is updated according to the number of times of matching. shl indicates a 1-bit left logical shift, shl ^N indicates an N-bit left logical shift (N is an integer value or an integer variable value), and the lower bits emptied as a result of the shift processing contain bit '0'. The B register and the C register (5 bits) are arranged on the same register, and the least significant bit of the B register is followed by the most significant bit of the C register. The code output unit is a byte.

The description will be made according to the numbers shown in the figure. Processing S1
Is the initialization of the B, C and A register values, and B, C
Clear the register and set the A register value to 1.0. The process S2 takes in the input symbol and sets a predicted SK value (initial value is 1). In the process S3, a match (T) / mismatch (F) between the input symbol and the predicted value is determined, and the process is switched according to the MIN value that is the result.

The process in S4 is a case where it is determined that the values do not match (F) in the process S3, and indicates a process of encoding the inferior symbol. In the process S4, the B and C registers are logically shifted left by SK bits, and the sign bit overflowing from the most significant bit of the C register is shifted to the least significant bit of the B register arranged at the higher level. A register value is always 1.0 Since SK-bit left logic shift 2 ^-SK. The process of expanding the A register value to 1.0 or more by the shift process when the value of the A register becomes less than 1.0 is called normalization process. After the end of the normalization process in step S4, the process proceeds to step S8.

[0008] The processing of S5 to S7 is a case where it is determined that they match (T) in the processing S3, and indicates the encoding processing of the dominant symbol. The process S5 is performed on the lower bound B of the effective area,
The C register and the A register, which is the effective area width, are updated, and the effective area for the superior symbol is located higher than the effective area for the inferior symbol. Therefore, the effective area width of the inferior symbol is 2 in the B and C registers. ^{Add -SK} and subtract 2 ^-SK from the A register. 2 in the C register
^{The carry} generated when ^-SK is added is propagated to the B register from the least significant bit to the most significant bit. In step S6, the A register value is compared with 1.0. If the A register value is equal to or greater than 1.0, the process proceeds to step S8.
Proceed to. In the process S7, after performing a normalization process of shifting the B, C and A registers left by one bit, the process proceeds to a process S8.

In step S8, it is determined whether or not encoding processing has been performed for all input symbol sequences. If data input has not been completed, each processing from step S2 is repeated. If data input has been completed, processing proceeds to step S9. The process S9 is a unit of output after performing a left logical shift process of 5 bits, which is the width of the C register, to output the codes remaining in the C register to the B register after the encoding process is completed for all input symbol sequences. Dummy bit '0' up to byte boundary
, And outputs a code to end the arithmetic coding.

In arithmetic decoding, the effective area width for the decoded output symbol sequence s and the decoded output symbol (T or F) is A, and the code is D (the code initial value is the code C in arithmetic coding). The decoding based on the lower bound of the effective area can be performed by repeating the arithmetic operation shown in (1) until the final output symbol. The code D is always updated sequentially from the lower bound of the effective area to the code C (initial value) by the following arithmetic operation. Initial state A (null) = 1.0 D (null) = C Area operation (multiplication can be realized by shift operation) Inferior symbol area width: A (s, F) = A (s) × 2 ^-SK superior symbol area Width: A (s, T) = A (s) -A (s, F) Decoding operation (output X) If D (s, X) <A (s, F), decoding of less-probable symbol X = F; D (S, F) = D (s) If D (s, X) ≧ A (s, F), dominant symbol decoding X = T; D (s, T) = D (s) −A (s, F) )

FIG. 9 shows the flow of the algorithm of arithmetic decoding. In the figure, D is a decoding register, B is an input buffer register for storing a received code, A is an effective area width register, MOUT is a determination result (T) / mismatch (F) between an output symbol and a predicted value, and SK is a determination result. SKew number
(1, 2, 3, 4). The SK value is updated according to the number of times of decoding as a match (T). shl is a 1-bit left logical shift, shl ^N is an N-bit left logical shift (N
Indicates an integer value or an integer variable value), and the next sign bit is supplied from the B register to the lower bits of the D register vacated as a result of the shift processing. The B register and D register (5 bits) are arranged on the same register.
Following the least significant bit of the D register, the most significant bit of the B register comes. The code input unit is a byte.

The description will be made according to the numbers shown. Processing S1
Is the initialization of the D, B and A register values. The D register is logically shifted left by 5 bits from the B register to fill the D register with the sign bit, and the A register value is shifted by 1.0.
And Process S2 is a process in which the predicted SK value (initial value is 1)
Is set. In the process S3, the decoded MOUT value is the result of the determination of the match (T) or mismatch (F) between the output symbol and the predicted value, but the code D which is the displacement from the lower bound of the effective area.
Is switched depending on whether the symbol is located in the region for the superior symbol or the inferior symbol. Symbol D is located in the area for the inferior symbol if less than 2 ^-SK region width against inferior symbol is determined to be located within the region for MPS if 2 ^-SK more.

The processing of S4 and S5 is the case where it is determined in the processing S3 that the code D is located within the area for the inferior symbol, and indicates the decoding processing of the inferior symbol. The process S4 sets that the MOUT value does not match (F). In the process S5, the D and B registers are logically shifted left by SK bits, and the sign bit overflowing from the most significant bit of the B register is shifted to the least significant bit of the D register arranged at a higher position, thereby taking in the sign bit. Always because the A register value is SK-bit left logic shift 2 ^-SK 1.0
Becomes After the normalization process in step S5 is completed, the process proceeds to step S10.

The processing of S6 to S9 is a case where it is determined in the processing S3 that the code D is located within the area for the dominant symbol, and indicates the decoding processing of the dominant symbol. The process S6 sets that the value matches (T) the MOUT value. The process S7 is performed in the D and B registers and the effective area width A
Since the register is updated and the effective area for the superior symbol is arranged higher than the effective area for the inferior symbol, the effective area width of the inferior symbol, 2- ^SK, is subtracted from the B, C, and A registers. The process S8 compares the A register value with 1.0. If the A register value is 1.0 or more, the process proceeds to the process S10, and if the A register value is less than 1.0, the process S9
Proceed to. A process S9 performs a normalization process of logically shifting the D, B, and A registers left by one bit, and then performs a process S10
Proceed to.

In step S10, it is determined whether or not decoding processing has been performed on all output symbol sequences. If decoding of output symbols has not been completed, each processing from step S2 is repeated. If decoding has been completed, arithmetic decoding is terminated. I do.

As shown in FIG. 10, a code sequence 2 for an input symbol sequence 1 (input data) is composed of an arithmetic code 3 and a terminal code 4 added to the end thereof. In the conventional arithmetic coding method, a control signal for the purpose of arithmetic coding transmission control is used, and a bit pattern that cannot appear in the output code sequence 2 is secured as a terminal code 4 to secure the code sequence 2. In the conventional arithmetic decoding method, the terminal code 4 is detected to detect the end of the code sequence 2 and terminate the decoding. In the arithmetic coding applied in this conventional example, a byte X'FF '(hexadecimal notation.
'? ? '. ) Appears, it is assumed that transmission control is performed to insert X'00 'as a control signal in the byte immediately after it, and the decoding side determines byte X'00' immediately after byte X'FF 'as a control signal. It just needs to be deleted. By performing such transmission control on the code sequence 2, the bytes X'FF '(hereinafter, the first byte of the end code 4 is referred to as an end code 5) and X'00'.
(Hereinafter, the second byte of the terminating code 4 is referred to as a control code 6), and a terminating code 4 consisting of 2 bytes is secured. Is added, it becomes possible for the decoding side to detect the end of the code sequence 2 by the end code 4. In the conventional example, the control code 6 which is the second byte of the terminal code 4 is replaced with the byte X'0
The most significant bit must always have the bit value '1' to distinguish it from '0'.
In addition, an input symbol sequence length 7 input as an encoding target is added to the lower 7 bits. Since there are only 128 possible values that can be represented by 7 bits, the encoding side indicates the control code 6 as a remainder obtained by dividing the number of bytes of the input symbol sequence length by 128, and adds it as a termination code 4. Further, the decoding side detects the terminal code 4 and knows the output symbol sequence length from the control code 6 of the second byte, and terminates the arithmetic decoding process when decoding is performed up to the detected output symbol sequence length.

FIG. 11 shows the configuration of a conventional encoding apparatus. In the figure, 40 is a modeling converter,
Reference numeral 41 denotes an arithmetic encoder for performing arithmetic coding while performing control for inserting a control signal, 42 denotes an end detector of an input symbol sequence, and 43 denotes a multiplexer (MPX).
1 to select one of the output of the counter 44 (described later) and the output of the end code generator 45 (described later), 44 is a counter for counting the input symbol sequence length, and 45 is an end code X'FF. 'Is an end code generator, 46 is an input symbol sequence such as character data, and 47 is a code sequence including a termination code.

The operation of the configuration shown in FIG. The input symbol sequence 46 is input to the modeling converter 40, and based on the T / F determination output from the modeling converter 40, the arithmetic encoder 41 outputs a code sequence 47 while performing control to insert a control signal. When detecting that the encoding process of the input symbol sequence of a predetermined fixed number of bytes has been completed, the end detector 42 supplies an end detection signal to the arithmetic encoder 41 and the multiplexer 43. The counter 44 counts the number of bytes of the input symbol sequence, and the multiplexer 43 first sends the end code X'FF '(the first code of the end code 4) to the end code generator 45 based on the end detection of the end detector 42.
Byte), outputs the end code 5 following the output of the arithmetic encoder 41, and then outputs the control code 6 (the second code of the terminal code 4) consisting of the lower 7 bits of the counter value and the most significant bit value '1'. Byte).

FIG. 12 shows the configuration of a conventional decoding apparatus. In the figure, reference numeral 50 denotes an input code sequence 5
6 (described later), an arithmetic decoder for performing arithmetic decoding while performing control to delete a control signal, 51 is a modeling inverse converter,
An output symbol sequence is converted based on the output of the arithmetic decoder 50. An end detector 52 detects the end code 4 in the code sequence. A register 53 is a second register of the end code 4. Stores the output symbol sequence length (7 bits) included in the control code 6 which is a byte, 5
4 is a counter for counting the output symbol sequence length, 55
Is an end detector composed of a comparator for comparing the value stored in the register 53 with the counter value of the counter 54, 56 is an input code sequence (including the terminal code 4), and 57 is an output symbol sequence.

The operation of the configuration shown in FIG. Code sequence 56
Is input to the arithmetic decoder 50 while the control signal is deleted, and is decoded into one of T / F. The decoded output is input to the modeling inverse transformer 51, and an output symbol sequence 57 is obtained. The counter 54 counts the output symbol sequence length. The termination detector 52 detects the termination code 4. The register 53 stores the lower 7 bits of the control code 6 (the second byte of the end code 4) detected by the end detector 52. The end detector 55 stores the value stored in the register 53 and the counter 54.
Are compared, and when they match, the arithmetic decoder 50 and the modeling inverse converter 51 are notified of the end of decoding.

In the above conventional example, the byte X is included in the code sequence.
Immediately after the appearance of 'FF', transmission control is performed by inserting byte X'00 'as a control signal to secure the terminal code 4, and arithmetic coding added to the end of the code sequence and added terminal code 4 are performed. The arithmetic decoding for detecting and terminating the arithmetic decoding has been described.

As described above, in order to determine the end of the output symbol sequence decoding process, the encoding side needs to notify the decoding side of the output symbol sequence length. For example, when the output symbol sequence length is handled at a fixed size, the encoding side does not need to notify the decoding side. Need to be notified. When the output symbol sequence length is of an arbitrary size, header notification cannot be applied when the input symbol sequence length cannot be known in advance due to restrictions on the data storage means on the encoding side, and so footer notification, that is, notification using the termination code 4 is used. Will be done. As described above, in the conventional example, when the input symbol sequence length cannot be known in advance on the encoding side, it is necessary to notify the decoding side including the output symbol sequence length in the termination code 4 added to indicate the end of the code sequence. To determine the end of the arithmetic decoding process.

[0023]

According to the conventional "data compression and decompression method" as described above, according to the conventional example,
A bit pattern that does not appear in the code sequence secured by the transmission control is added as a termination code, and the output symbol sequence length is determined by indicating the encoded (compressed) input symbol sequence length in the termination code with 7 bits. Decryption (restoration)
Is terminated, but the maximum number of symbols (data) that can be decoded after the detection of 7-bit information notified as the remainder of the number of bytes of the input symbol sequence length divided by 128 is 1024 bits (= 128 × 8 bits = 2 ¹⁰ bits), the code register length and decode register length are 1
When it is larger than 0 bits, there is a problem that the output symbol sequence may be decoded shorter than the input symbol sequence length while leaving the undecoded code in the decoding register, and the decoding may be terminated. When encoding an input symbol sequence composed of a plurality of blocks, it is necessary to provide a bit for notifying whether or not the block is the last block in the control code 5 of the end code 4 added to each block. End code 5 which must be a fixed value to be recognized as end code 4
(Byte X'FF '), the most significant bit' 1 'of the control code 6 and a bit for notifying whether or not the block is the last block. Only 6 bits can be used for the notification of the symbol sequence length, and there is a problem that the possibility of erroneously terminating decoding is increased.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has an encoding method and a decoding method capable of terminating decoding without erroneous output symbol sequence length.
It is an object to provide a decoding scheme and an encoding / decoding scheme .

[0025]

Means for Solving the Problems] engagement Ru marks Goka scheme to a first aspect of the present invention, for outputting the arithmetic encoded code sequence by entering the input symbol sequence of blocks of a constitutional unit of data units Has the following elements. (A) receives the input symbol sequence, performs coding by the arithmetic coding technique, the arithmetic coding means for outputting code sequences, you detect data unit is a structural unit of a block from the (b) the input symbol sequence units detection means, (c) the coding side unit detected detected data unit by means coding end determining unit determines whether the last data unit of the block, (d) the arithmetic coding unit And a terminating code adding means for adding a specific bit pattern that cannot appear in the code sequence output by the terminal as a terminating code to the end of the code sequence for the block determined by the coding end determining means.

The engagement Ru marks Goka scheme to a second aspect of the present invention is inserted immediately after the bit pattern control signals of a predetermined length when a predetermined pit pattern appeared on the output code sequence by arithmetic coding means It is characterized by having control signal insertion means.

A third decrypt scheme engaged Ru to the invention, in order to output an output symbol sequence by entering a code sequence of blocks of a constitutional unit data unit is arithmetic decoding, those having the following elements It is. (A) as an input code sequence, performs decoding by the arithmetic decoding method, the arithmetic decoding means for outputting an output symbol sequence, (b) detection to Ruyu knit detect data unit is a structural unit of a block of output symbol sequence means, based on (c) termination code detecting means for detecting a specific bit pattern that can not appear in the code sequence as a termination code, (d) a detection result of the termination code according to the termination code detecting means, the upper Kiyu knit Decoding end determination means for determining whether the data unit detected by the detection means is the last data unit of the block.

The decrypt method engaged Ru to the fourth invention, the control signal of a predetermined length just after the bit pattern is inserted when the predetermined bit pattern appeared to code sequence input in the arithmetic decoding means And a control signal processing means for deleting the inserted control signal having a predetermined length.

The fifth decrypt scheme engaged Ru to the present invention, in the above termination code detecting means detects termination code, by the upper Kiyu knit detecting means, an output symbol to be decoded continuously by the arithmetic decoding means of the following When it is detected that the data unit cannot be satisfied, the decoding end determination means sets the last data unit filled with the output symbol as the last data unit of the block, and discards the output symbol that cannot satisfy the data unit. I do.

[0030] The decoding method according to the sixth invention is characterized in that the terminal code
Signal detecting means detects the terminal code, and the arithmetic decoding means
Input to the decoding register, and the value of the decoding register is
By detecting that a predetermined value is reached, the decoding end is detected.
Termination determination means determines the end of decoding.

The encoding / decoding method according to the seventh invention is as follows.
It has the following elements. (A) An input symbol sequence is input, and the
Arithmetic coding that outputs a code sequence
Stage, (b) code sequence to be output in the arithmetic coding means
A predetermined length when a predetermined bit pattern appears in
Control signal for inserting the control signal of
Insertion means, data unit is a structural unit (c), the input symbol sequence
Encoding side unit detecting means for detecting the bets, blow represented by (d) Data unit length an integral multiple of the length of the
The encoding unit by the encoding unit detection means.
If the issued data unit is the last data unit
Whether to terminate arithmetic coding
Coding end determination means for determining, with respect to the code sequence output from the (e) the arithmetic coding unit
By using the control signal insertion means,
Bit pattern is detected by the encoding end detecting means.
Indicates whether the last block is at the end of the code sequence of the
Terminal code addition method to add as a terminal code including
Stage, as input (f) code sequence, decoding by the arithmetic decoding method
And (g) an arithmetic decoding unit that outputs an output symbol sequence.
When a predetermined bit pattern appears, the bit pattern
As a control signal of a predetermined length inserted immediately after
Control signal processing means for deleting after a data unit is a structural unit of (h) output symbol sequence
Decoding side unit detecting means for detecting the door, control signals to be processed in (i) the control signal processing means
Signal is inserted into the code sequence,
A specific bit pattern that cannot appear in
End code detecting means for detecting, Bro represented by (j) Data Unit, an integral multiple of the length of the
The terminal code in the terminal code detection means.
Is detected, and the arithmetic decoding means
The updated code (register value) and the decoding side
Is the data unit detected by the unit detection means?
Et al., Output symbols to be decoded continuously following de Tayuni'
If the data unit cannot be filled, the last
Is determined as a block with the last data unit,
Discard output symbols that cannot fill the data unit, and
From the terminal code detected by the terminal code detection means.
Obtain information on whether the block is the last block and perform arithmetic decoding
Decoding end determining means for determining whether or not to end the decoding.

The encoding / decoding method according to the eighth aspect of the present invention
Code series (arithmetic
Sign) is either the superior symbol or the inferior symbol
Input symbol sequence (coding symbol) or output
For the power symbol sequence (decoded symbol),
Lower the area corresponding to the inferior symbol in the effective area
Place and select the lower bound of the final area (decoding register
Value) as a code sequence, and adding a termination code in the coding method
The means is between the code sequence and the terminal code added to the end.
Damage of a number that does not affect the end code detection of the end code detection means
A bit '0' is inserted.

[0033] The encoding / decoding method according to the ninth invention is characterized in that
Code series (arithmetic
Sign) is either the superior symbol or the inferior symbol
Input symbol sequence (coding symbol) or output
For the power symbol sequence (decoded symbol),
Up the area corresponding to the inferior symbol in the effective area
Place and select the lower bound of the final area (decoding register
The closest value to the upper limit value and the code sequence values) and at the same accuracy, marks
The terminating code adding means in the encoding method includes a code sequence and its
Termination of termination code detection means between termination codes added to termination
Insert a number of dummy bits '1' that do not affect code detection
It is characterized by that.

The encoding / decoding system according to the tenth invention is
In the above encoding / decoding method, the control in the encoding method is used.
The control signal insertion unit outputs a code sequence output from the arithmetic coding unit.
Is propagated, and all bits '1'
The output unit (such as bytes) of the occupied code sequence is output.
The most significant bit or al a predetermined output unit immediately after each time it is force
Control signal consisting of bits '0' of length
Control signal processing means for performing transmission control and decoding method
Is the input unit (code) of the code sequence input to the arithmetic decoding means.
Are all occupied by bit '1'
From the most significant bit of the input unit immediately after
Judge bit '0' as inserted control signal and delete
Transmission control is performed.

The encoding / decoding method according to the eleventh invention is:
In the above encoding / decoding method, the end of the encoding method is used.
The end code adding unit is determined by the encoding end determining unit.
The final block including information indicating whether the block
The end code is added to the end of the code sequence for the block condensate
Decoding end determination means in the signal system,
Block is the last block from the terminal code detected by
To obtain the information indicating whether
Features.

The encoding / decoding method according to the twelfth invention is:
In the above encoding / decoding method, the end of the encoding method is used.
End code adding means adds to the code sequence and its end
Terminator between terminator consisting of code and control code
Number of dummy bits that do not affect the detection of
And the last part of the code sequence with dummy bits inserted
When the minute matches the end code, the last part of the code sequence is
Omitted by also using the end code, ending with the control code
An end containing information indicating the omission of the same bit pattern as the sign.
The end code is added to the end of the code sequence, end the decoding scheme
End code detection means detects a terminal code at the end of the code sequence,
The arithmetic decoding means takes a code sequence of the number of bits of the end code.
Until the end code is detected.
It is characterized by being delayed.

The encoding / decoding method according to the thirteenth invention is as follows:
Encode the length of the data unit, which is the unit of data
With shared side as the decoding side, the encoding side, the input data
One or more blocks at the boundaries of any data unit
Means for encoding by dividing into
An end code that can identify the end of the block
Means for adding arithmetic codes to the decoding side.
And the end of the block from the end code.
Means for ending the decryption process by issuing
And features.

[0038]

As described above, the encoding method and decoding method of the present invention
Signal system and encoding / decoding system are input / output symbol sequences
Since processing is performed in data unit units, which are constituent units of
Output symbol sequence length expressed as a multiple of the data unit length
The decoding process can be terminated without error.

[0039]

[Embodiment 1] In the first embodiment, the encoding side and the decoding side share a data unit length, which is a constituent unit of an input symbol sequence and an output symbol sequence, in advance, so that an arithmetic coding algorithm flow similar to the conventional example (FIG. 8) According to the flow of the arithmetic decoding algorithm (FIG. 9), control is performed to insert a control signal into a generated code sequence, and if an end code is added to the end of the code sequence at the end of encoding, the input symbol sequence length is notified. A description will be given of a data encoding and decoding method that can end decoding without erroneous output symbol sequence length without performing the above.

The input symbol sequence and the output symbol sequence have a data unit as a constituent unit, and are further divided into blocks formed by an arbitrary number of data units. The data unit is a data configuration unit such as an 8-bit input / output symbol sequence for character data and a horizontal pixel count for image data, and the input / output symbol sequence length can be represented by a multiple of the data unit length. While it is difficult to know the input / output symbol sequence length in advance, the data unit length is information that can be easily shared between the encoding side and the decoding side. For example, when the encoding side and the decoding side handle only data in units of 8 bits, the data unit length is 8 bits. Also, in the case of fixed-length data other than 8 bits, a common data unit length can be shared by setting the length in advance on the code side and the decode side. If the length is not a fixed length, unification can be achieved by notifying the data unit length in advance by header communication or the like before data transmission.

In order to cope with the encoding and decoding of the input / output symbol sequence divided into blocks, two types of terminal codes are prepared by distinguishing whether or not they are the last blocks. If the input / output symbol sequence is composed of a single block, a termination code indicating the last block is added to the end of the code sequence. A terminal code indicating that it is not the last is added, and a terminal code indicating that it is the last is added to the last block. FIG. 1 is a conceptual diagram of a code sequence output by input of an input symbol sequence composed of two blocks. A continuation block indicating that the block is not the last block is denoted by X'FFC0 ', and a continuation indicating the last block. X'F for the non-block termination code 10b
F80 '. However, control codes 11a,
Although 11b is indicated by X'C0 'and X'80', a specific bit does not need to have a meaning, and can be freely selected from values within a range of a reserved terminal code.

Hereinafter, the input / output unit of the code sequence is byte (8
) Will be described using the names used in the flow of the arithmetic coding algorithm (FIG. 8) and the flow of the arithmetic decoding algorithm (FIG. 9).

In the encoding and decoding processes, the updating algorithm of the effective area is the same as that of FIGS. 8 and 9, so that the position and width of the effective area on the number line are the same. The encoding side corrects and generates a code sequence as a lower bound of an effective area updated using addition in the encoding operation. The code sequence finally generated in this way indicates the lower bound of the final effective area. The decoding side uses the code sequence as an initial value, and corrects the code sequence as a displacement from the lower limit of the effective area updated using subtraction in the decoding operation. At the end of decoding, the lower bound value of the final effective area matches the code sequence initial value, and therefore the code sequence corrected as a displacement from the lower bound value of the final effective area always becomes 0. Here, the number of bits of the code sequence taken into the D register in the decoding process is:
It becomes equal to the number of bits of the code sequence swept out of the C and S registers in the encoding process.

Before the end code is added to the end of the code sequence, dummy bits '0' of 0 to 7 bits are packed up to the byte (= 8 bits) boundary which is the output unit. If it is not clear how many dummy bits are packed in the byte immediately before the terminal code, even the dummy bits are fetched and the output symbol sequence may be decoded long. The code sequence corrected as a displacement from the lower bound value of the final effective area where the decoding process should be completed, that is, the value of the D register is 0, and even if the dummy bit '0' is taken in and the decoding process is continued, , Only the inferior symbol can be decoded. Since decoding of the inferior symbol always involves normalization processing, a dummy bit '0' is further taken in. Since the maximum number of dummy bits is 7 bits and the minimum number of shift digits for normalization is 1 bit, there is a possibility that a maximum of 7 extra symbols may be decoded. By performing the above shift, the bits after the terminal code are fetched, so that it can be reliably determined that the decoding must be completed. Therefore, when the encoding side and the decoding side share and share the data unit length, which is a constituent unit of the input / output symbol sequence, when the encoding and decoding processes are performed, the shared data unit length must be 8 or more, which is the input / output unit length of the code sequence. Then, it can be seen that even if decoding is performed 7 bits (symbol) extra, a data unit cannot be formed, and the decoding process of the output symbol sequence should have been completed in the immediately preceding data unit. Setting the minimum data unit length to 8 in this way indicates that it can sufficiently handle not only image data but also data in units of bytes such as character data.

As described above, arithmetic coding that shares the data unit length (≧ 8; the input unit length is a byte), which is a constituent unit of an input / output symbol sequence, and that is notified of the end of the code sequence by a terminal code In addition, in arithmetic decoding, by following the processing procedure 1 described below, the end of the decoding process can be accurately determined without decoding extra symbols. Processing procedure 1. (Procedure 1) The terminal code is detected in advance from the code sequence. (Procedure 2) The code bit is taken into the D register from the input unit (last byte) immediately before the terminal code and decoded, and it is detected that the D register becomes 0. (Procedure 3) The end of the data unit is detected, and the decoding process ends.

Similarly, it is possible to determine the data unit for which the decoding process should be terminated according to the following procedure 2. In this case, although the extra symbols are decoded, the data units cannot be filled, so that they may be discarded. Processing procedure 2. (Procedure 1 ′) The terminal code is detected in advance from the code sequence. (Procedure 2 ') Up to the code bit (including the dummy bit) immediately before the terminal code is taken into the D register and decoded. (Procedure 3 ′) If there is an incomplete data unit, it is discarded, and the decoding process ends.

In the arithmetic coding and arithmetic decoding in which the input / output symbol sequence is divided into blocks composed of an arbitrary number of data units, the decoding of the blocks is completed by any of the above-described processing procedures. The presence / absence of a continuation block may be determined from the terminal code thus obtained, and if there is a continuation block, the decoding of the next block may be started. If there is no continuation block, the decoding process of the output symbol sequence may be terminated.

The configuration of the encoding apparatus according to the first embodiment is shown in FIG.
Is shown as In the figure, the modeling converter 4
0, arithmetic encoder 41, multiplexer (MPX) 43,
The input symbol sequence 46 and the code sequence 47 have the same functions as those having the same names in the configuration of the conventional encoder shown in FIG. A unit end detector 20 detects the end of a data unit which is a constituent unit of the input symbol sequence 46. Reference numeral 21 denotes an encoding end determiner which detects the end of a block which is a unit of division of an input symbol sequence and determines whether or not the block is the last block. Reference numeral 22 denotes a terminal code generator, which is notified of the end of the block and whether or not the block is the last block from the coding end determiner 21, and generates a terminal code.

The operation of the configuration shown in FIG. The input symbol sequence 46 is input to the modeling converter 40, and based on the T / F determination output from the modeling converter 40, the arithmetic encoder 41 outputs a code sequence 47 while performing control to insert a control signal. Each time the unit end detector 20 detects that an input symbol sequence has been input for one data unit, it notifies the coding end determiner 21 of a unit detection signal. Each time the encoding end determiner 21 is notified of the unit detection signal and detects that one block has been input,
The arithmetic encoder 41 and the terminal code generator 22 are notified of the block detection signal and whether or not the block is the last block. Multiplexer 4
3 causes the arithmetic encoder 41, which has been notified of the block detection signal, to output a code sequence 47. The multiplexer 43 first sends the end code end code X'FF 'to the end code generator 22.
Next, control code X'C0 '(with continuation) or X'80'
Select (No continuation) to output. In this way, the multiplexer 43 adds a termination code including the presence or absence of a continuation block to the end of the code sequence 47 for the block based on whether or not the block is the last block. If there is a continuation block, the coding end determiner 21 newly starts the coding process of the next block, and ends the coding process of the input symbol sequence when there is no continuation block.

The configuration of the decoding apparatus according to the first embodiment is shown in FIG. In the figure, an arithmetic decoder 50, a modeling inverse transformer 51, an end detector 52, a code sequence 55, and an output symbol sequence 57 have the same functions as those having the same names in the conventional encoding device configuration shown in FIG. . Reference numeral 30 denotes a unit end detector for detecting the end of a data unit. Reference numeral 31 denotes a decoding end judging unit which detects the end code determined, the decoding register value in the arithmetic decoder 50, and the detected data unit end. The end of the decoding process of the block is detected, and whether or not the block is the last block is determined based on the terminal code. If the block is the last block, the decoding process of the output symbol sequence is ended.

The operation of the configuration shown in FIG. Code sequence 56
Is input to the arithmetic decoder 50 while the control signal is deleted, and is decoded into one of T / F. The decoded output is input to the modeling inverse transformer 51, and an output symbol sequence 57 is obtained. The termination detector 52 detects a termination code. Each time the unit end detector 30 detects that the output symbol sequence has been output by one data unit, the decoding end determiner 31
To the unit detection signal. The decoding end determiner 31 is notified of the detection of the terminal code from the terminal detector 52, and thereafter, when the unit detection signal is first notified after the decoding register value in the arithmetic decoder 50 becomes 0, or The decoding is continued until immediately before the terminal code is taken in, the extra symbols that cannot fill the data unit are discarded, the block is terminated, and the arithmetic decoder 50 and the modeling inverse converter 51 are notified of the block detection signal and whether or not the block is the last block. I do. The block end detector 21 determines whether or not the last block is the last block based on the detected terminal code. If there is a continuous block, the decoding process of the next block is newly started. Otherwise, the decoding process of the output symbol sequence is ended. .

In the first embodiment, the input symbol sequence is obtained by encoding the input symbol sequence by referring to the data unit length and the decoding register value which are the constituent units of the input / output symbol sequence which were not referred to in the conventional example. The decoding is terminated from the code sequence without error in the output symbol sequence length.
Since the input / output unit is byte (8 bits), if the data unit length is 8 or more, the input / output symbol sequence, block, and data unit do not need to end at byte boundaries, and dummy bits are packed up to the byte boundaries for each. It suffices if measures such as whether or not are unified on the encoding side and the decoding side. The input / output unit need not always be a byte, but may be a word, but the data unit length is limited according to the input / output unit length (number of bits).

As described above, in the first embodiment, the data unit length (≧ 8) is shared between the arithmetic encoding side and the arithmetic decoding side, and the input / output symbol sequence is the same as that shown in the conventional example. By using a code sequence (arithmetic code) in which a control signal is inserted and a termination code is added to the end, even if the input symbol sequence length to be encoded is arbitrary, the output symbol sequence length can be decoded without error. A data encoding and decoding method that can cope with encoding and decoding of an input / output symbol sequence divided into blocks of an arbitrary length has been described.

Embodiment 2 FIG. In the first embodiment, in the effective area distributed to the judgment values T and F indicating the match / mismatch with the prediction value, the judgment value T is arranged at the upper position and the judgment value F is arranged at the lower position. (Arithmetic code) was calculated and obtained as the lower bound of the effective area on the number line. Next, in the second embodiment, a case will be described in which the judgment value T is arranged in the lower part and the judgment value F is arranged in the upper part in the effective area distributed to the judgment values T and F (inverse arrangement with the conventional example). I do. In this case, the code sequence is calculated as the lower limit value of the effective area as in the conventional example, but when the lower limit value is used as the code, the upper limit value cannot be converted into a code. It will be described that a similar function can be realized by encoding.

Arithmetic coding is to repeat the following arithmetic operation up to the last input symbol, where A is the effective area width for the input symbol sequence s already coded and the input (T or F) to be coded, and C is the code. Gives a code based on the lower bound. Initial state A (null) = 1.0 C (null) = 0.0 Area operation (multiplication can be realized by shift operation) Inferior symbol area width: A (s, F) = A (s) × 2 ^-SK superior Symbol area width: A (s, T) = A (s) -A (s, F) Encoding operation Inferior symbol encoding: C (s, F) = C (s) + A (s, F) Superior symbol code Formula: C (s, T) = C (s)

FIG. 4 shows the flow of the algorithm of arithmetic coding.
Shown in Various settings and notations in the figure are the same as those in FIG. Also, in order to make the code the value closest to the upper bound value of the final effective area, before sweeping out the C register value, A-2- ^(5-1) (5-1 = 4 in the exponent part is the SK maximum value, 5 is the coding register length) and after sweeping out,
Dummy bit '1' is packed to byte boundary.

Hereinafter, description will be made in accordance with the numbers in the figure. Processing S
1 is the initialization of the B, C and A register values.
Clear the C register and set the A register value to 1.0.
The process S2 takes in the input symbol and calculates the predicted SK
Set a value (initial value is 1). In the process S3, a match (T) / mismatch (F) between the input symbol and the predicted value is determined, and the process is switched according to the MIN value that is the result.

The process of S4 is a case where it is determined that the values do not match (F) in the process S3, and indicates the encoding process of the inferior symbol. The process S4 is performed for the lower bounds B and C of the effective area.
Update the register and A register which is the effective area width,
Since the effective area for the inferior symbol is located higher than the effective area for the superior symbol, A-2- ^SK which is the effective area width of the superior symbol is added to the B and C registers. The carry generated when 2- ^SK is added to the C register is propagated to the B register from the least significant bit to the most significant bit. The B and C registers are logically shifted left by SK bits, and the sign bit overflowing from the most significant bit of the C register is shifted to the least significant bit of the B register arranged at the higher level. Always 1 because the A register value is SK-bit left logic shift 2 ^-SK.
It becomes 0. After the end of the normalization process in step S4, the process proceeds to step S8.

The processing of S5 to S7 is a case where it is determined that the match (T) is obtained in the processing S3, and indicates the encoding processing of the superior symbol. In the process S5, only the A register, which is the effective area width, is updated, and the 2- ^SK , which is the effective area width of the inferior symbol, is subtracted from the A register. The process S6 compares the A register value with 1.0. If the A register value is 1.0 or more, the process proceeds to a process S8, and if the A register value is less than 1.0, the process proceeds to a process S7. In the process S7, after performing a normalization process of shifting the B, C and A registers left by one bit, the process proceeds to a process S8.

In step S8, it is determined whether or not encoding has been performed on all input symbol sequences. If data input has not been completed, each process from step S2 is repeated, and if completed, the process proceeds to step S9. Process S9, all of the input symbol sequence is output the remaining codes for the encoding process after the end of the C register, to the value closest to the upper bound First B, and A-2 ^-4 in the C register is added , C
A left logical shift process of 5 bits, which is the register width, is performed.
Also, the code is output by packing the dummy bit '1' up to the boundary of the output unit (here, byte), and the arithmetic coding is completed. By adding the dummy bit '1',
Further, a value close to the upper bound value can be output as a code sequence.

In the arithmetic decoding, the effective area width for the decoded output symbol sequence s and the decoded output symbol (T or F) is A, and the code is D (the code initial value is the code C in the arithmetic coding). The decoding can be performed by repeating the arithmetic operation shown in (1) up to the final output symbol.
The code D is always updated sequentially from the lower bound of the effective area to the code C (initial value) by the following arithmetic operation. Initial state A (null) = 1.0 D (null) = C Area operation (multiplication can be realized by shift operation) Inferior symbol area width: A (s, F) = A (s) × 2 ^-SK superior symbol area Width: A (s, T) = A (s) −A (s, F) Decoding operation (output X) If D (s, X) ≧ A (s, T), decoding of inferior symbol X = F; D (S, F) = D (s) −A (s, F) If D (s, X) <A (s, T), dominant symbol decoding X = T; D (s, T) = D (s) )

FIG. 5 shows the flow of the algorithm of arithmetic decoding. Various settings and notations in the figure are the same as those in FIG.

The description will be made according to the numbers in the figure. The processing S1 is
Initialization of the D, B, and A register values. The D register is logically shifted left by 5 bits from the B register to fill the D register with the sign bit, and the A register value is set to 1.0. The process S2 sets a predicted SK value (the initial value is 1). In the process S3, the MOUT value to be decoded is the determination result of the match (T) / mismatch (F) between the output symbol and the predicted value. The processing is switched depending on which area is located. If the code D is equal to or ^larger than the area width for the superior symbol, ie, A−2− ^SK, it is determined that the symbol D is located within the area for the inferior symbol and less than A−2− ^SK .

The processing of S4 and S5 is a case where it is determined in the processing S3 that the code D is located within the area for the inferior symbol, and indicates the decoding processing of the inferior symbol. The process S4 sets that the MOUT value does not match (F). Step S5 is, D, updates the B register, since the effective area with respect to inferior symbol is arranged in the upper than the effective region for the MPS, an effective area width of the major symbol from D, B register A-2 ^- Reduce ^SK . The D and B registers are logically shifted left by SK bits, and the sign bit overflowing from the most significant bit of the B register is shifted to the least significant bit of the D register arranged at the upper position, thereby taking in the sign bit. A register value SK a 2 ^-SK
Since it is logically shifted left by bits, it always becomes 1.0. Processing S
After the normalization process of No. 5, the process proceeds to the process S10.

The processing of S6 to S9 is the case where it is determined in the processing S3 that the code D is located within the area for the dominant symbol, and indicates the decoding processing of the dominant symbol. The process S6 sets that the value matches (T) the MOUT value. The process S7 is performed in the D and B registers and the effective area width A
Only the register is updated, and 2- ^SK , which is the effective area width of the inferior symbol, is subtracted from the A register. The processing S8 is performed at A
The register value is compared with 1.0, and if the A register value is 1.0 or more, the process proceeds to step S10, and if it is less than 1.0, the process proceeds to step S9. The process S9 sets the D, B and A registers to 1
After performing the normalization process of shifting the bits left logically, the process S
Proceed to 10.

In step S10, it is determined whether or not decoding has been performed on all output symbol sequences. If decoding of output symbols has not been completed, each process from step S2 is repeated. If decoding has been completed, arithmetic decoding is terminated. I do.

The configuration and operation of the encoding apparatus and the configuration and operation of the decoding apparatus according to the second embodiment are the same as those of the first embodiment shown in FIGS. The same can be said.

In the first embodiment, there is a possibility that the inferior symbols are output in excess of seven at the time of decoding. In the second embodiment, since the region of the superior symbol is arranged below the region of the inferior symbol, if the code sequence sequentially corrected by the decoding operation becomes the lower bound, the superior symbol is continuously decoded. Become. However, since the shift process does not necessarily occur when the superior symbol is decoded, there is no guarantee that the number of extra symbols to be decoded is within 7 (the shift number is 7 bits). Therefore, the code sequence is set to the value closest to the upper bound value so that the symbols to be decoded are only the inferior symbols, and the dummy bits '1' are packed up to the byte boundaries to be located in the inferior symbol area. Can be. However, the code sequence is output with a control signal inserted when the byte X'FF 'appears, for example, and the last byte is X'F to fill the dummy bit' 1 'up to the last byte boundary.
It may be F '. At this time, the process of inserting the control signal into the next byte must be performed, but the process of inserting the control signal is not performed only on the last byte X'FF '. For example, assuming that the terminating code 12a added to the end of the code sequence is X'FF80 'as shown in FIG. 6, the code sequence terminating unit (3 bytes) including the terminating code 12a is X'.multidot.
··· FFFF80 'and byte X'FF' follows, but it is easy to determine that X'FF80 'is the terminal code 12a. Therefore, in the second embodiment, since the code sequence is set to a value closest to the upper bound of the final effective area, the D register does not become 0, but the processing procedure 2 (described in the first embodiment) The end of the decoding process can be accurately determined by the procedures 1 ′ to 3 ′).

Embodiment 3 FIG. As shown in FIG. 7, when the code sequence terminating unit including the terminating code 12a becomes X '... XxFFFF80', for example, the least significant bit of the terminating code 12a is set to a byte X.
If bits indicating the abbreviation of 'FF' (abbreviation: '1'; none: '0') are used, the code sequence end portion is X '
XxFF81 '. If the byte X'FF 'does not continue, it is not necessary to omit it.
'FF80' may be left as it is, and decoding processing may be performed up to the end code 5. When the byte X'FF 'is omitted, the decoding process must be performed until the last byte X'FF' of the code sequence which is also used as the first byte (end code 5) of the terminal code 12b.

Embodiment 4 FIG. In the above-described first embodiment, the case where a plurality of blocks are encoded / decoded consecutively has been described, but they need not be consecutive. For example, when encoding of one block is completed, the encoding side temporarily suspends the encoding process, outputs a code sequence up to that, adds a terminal code to distinguish whether or not the last block, and the decoding side Alternatively, when the end of one block is determined based on the end code, the decoding process may be temporarily suspended. If it is necessary for the encoding side to perform some processing before proceeding to the encoding of the next block, the desired processing is performed, and the decoding side performs similar processing before proceeding to the decoding of the next block, thereby achieving synchronization. It becomes possible. The processing to be executed includes, for example, a change in data unit length, correction of an error, reinitialization or switching of a prediction value table, and when a plurality of processings are conceivable, the terminal code is not used in the first embodiment. The processing to be executed can also be specified by bits that are not present (lower 6 bits in the first and second embodiments, 4 bits in the third embodiment).

Embodiment 5 FIG. In the first embodiment, the block size may be fixed or arbitrary. Even if the encoding side divides the block at an arbitrary location, the decoding side can correctly decode by using the above-described processing procedure. When the encoding side wants to arbitrarily divide the block of the input symbol sequence, that is, when it wants to execute the block division in the middle of the encoding process, it terminates after outputting a coded sequence up to the point where a certain data unit has been encoded. The end of the block is designated by adding a code, and the decoding side may decode while detecting the designated end of the block.

The coding described in the first to fifth embodiments
Method and decoding method and encoding / decoding method
In the stage and configuration, the control signal is applied to the code sequence on the encoding side and the decoding side.
By inserting, the encoding side terminates at the end of the code sequence.
A code is added, and the decoding side detects the added end code.
Data by referring to the decoding register value or
Discards extra decoded symbols that cannot satisfy the data unit
Input / output symbol shared by the encoding side
Data unit length (8 bits for character data,
Based on the number of horizontal pixels in image data)
Decode without erroneous output symbol sequence length
You. For example, 8 bits for character data and water for image data
The data which is a unit of the input / output symbol sequence such as the number of flat pixels
Data unit length is encoded / decoded by header notification etc.
Before the process starts, it must be shared between the encoding side and the decoding side
To control transmission on the encoding side.
The control signal added to the end of the inserted code sequence.
The end code is detected on the decoding side, and the decoding register value is referenced.
Or extra recovery that cannot fill the data unit
By discarding the symbol
The output symbol sequence length, which is a multiple of the
Thus, the decoding process can be terminated without performing any processing. Also, enter
There is no need to add the power symbol sequence length to the terminal code
With an input symbol sequence consisting of multiple blocks
End of block and end of last block even when encoding
Set the termination code by distinguishing the end (end of input symbol sequence)
Data unit length and block
Even if the clock length changes for each block, the encoding side and the decoding side
Output symbol by sharing only data unit length
The decoding process can be terminated without error in the sequence length
You.

Further , the input symbol sequence length is added to the terminal code.
Since there is no need to add
Even when encoding a power symbol sequence
Distinguishing between end and end of block (end of input symbol sequence)
To set and add a termination code,
The data unit length and block length change for each block.
Even if the data unit length is changed, only the data unit length is
With this, the output symbol sequence length can be restored without error.
The signal processing can be ended.

Also, a dummy bit is inserted at the end of the code sequence.
The same bit pattern as the end code of the terminal code.
Pattern does not continue when the pattern appears.
Abbreviations and by adding a terminal code
The total code length can be reduced.

[0075]

As described above, according to the present invention, the entrance / exit
In units of data units, which are constituent units of force symbol sequences
Processing, so output expressed as a multiple of the data unit length
Terminate the decoding process without erroneous symbol sequence length
Can be.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram of a code sequence in one embodiment (embodiments 1 and 2) showing the present invention.

FIG. 2 is a functional block diagram showing a configuration of an encoding device according to an embodiment (Embodiments 1 and 2) of the present invention.

FIG. 3 is a functional block diagram showing a configuration of a decoding device in one embodiment (Embodiments 1 and 2) showing the present invention.

FIG. 4 is a flowchart of an arithmetic coding algorithm in one embodiment (second embodiment) showing the present invention (located above inferior symbols).

FIG. 5 is a flowchart of an arithmetic decoding algorithm in one embodiment (embodiment 2) showing the present invention (located above inferior symbols).

FIG. 6 is a conceptual diagram of a code sequence in one embodiment (second embodiment) showing the present invention.

FIG. 7 is a conceptual diagram of a code sequence in one embodiment (third embodiment) showing the present invention (X'FF 'is omitted).

FIG. 8 is a flowchart of an arithmetic coding algorithm according to a conventional example and an embodiment (Embodiment 1) showing the present invention (located below inferior symbols).

FIG. 9 is a flowchart of an arithmetic decoding algorithm in a conventional example and an embodiment (Embodiment 1) showing the present invention (located below inferior symbols).

FIG. 10 is a conceptual diagram of a code sequence in a conventional example.

FIG. 11 is a functional block diagram showing a configuration of an encoding device in a conventional example.

FIG. 12 is a functional block diagram showing a configuration of a decoding device in a conventional example.

[Explanation of symbols]

 Reference Signs List 1 input symbol sequence (input data, original data) 2 code sequence (compressed data) 3 arithmetic code 4 terminal code (conventional example) 5 end code 6 control code (conventional example) 7 input symbol sequence length (number of original data) 10a terminal Code (with continuation) (Example) 10b Termination code (without continuation) (Example) 11a Control code (with continuation) (Example) 11b Control code (without continuation) (Example) 12a Termination code (Example) 12b Terminal code (X'FF 'omitted) (Example) 13a Control code (Example) 13b Control code (X'FF' omitted) (Example) 20 Unit end detector (Encoding side) 21 Encoding end Judgment unit 22 Termination code generator 30 Unit end detector (decoding side) 31 Decoding end judgment unit 40 Modeling converter 41 Arithmetic encoder 42 End detector (encoding side) 43 Mal Plexer (MPX) 44 Counter 45 End code generator 46 Input symbol sequence (input data, original data) 47 Code sequence (compressed data) 50 Arithmetic decoder 51 Modeling inverse converter 52 Termination detector 53 Register 54 Counter 55 Termination detector (Decoding side) (Comparator) 56 Code sequence (compressed data) 57 Output symbol sequence (decompressed data)

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Masayuki Yoshida 5-1-1, Ofuna Kamakura City Mitsubishi Electric Corporation Communication Systems Laboratory (56) References JP-A-3-44116 (JP, A) JP-A-3-247123 (JP, A) JP-A-4-277933 (JP, A) JP-A-5-341955 (JP, A) JP-A-5-30372 (JP, A) JP-A-56-30453 (JP , A) (58) Field surveyed (Int.Cl. ⁷ , DB name) H03M 7/40

Claims (13)

(57) [Claims] 1. An encoding method which has the following elements and receives an input symbol sequence composed of blocks each having a data unit as a constituent unit, and outputs an encoded code sequence. , performs coding by the arithmetic coding technique, the arithmetic coding means outputs a code sequence, (b) detection to Ruyu knit detector data unit is a structural unit from the input symbol sequence block, (c) above Coding end determining means for determining whether or not the data unit detected by the coding unit detecting means is the last data unit of the block; (d) appearing in a code sequence output from the arithmetic coding means Termination code addition for adding a specific bit pattern that cannot be obtained as a termination code to the end of the code sequence for the block determined by the coding end determination means. means. Wherein the control signal insertion means for inserting a control signal of a predetermined length just after the bit pattern when the predetermined pit pattern appeared on the output code sequence by 2. A top Symbol arithmetic encoding means Claim 1
Of marks Goka system. 3. A decoding method having the following elements and receiving a code sequence composed of blocks each having a data unit as a constituent unit and outputting a decoded output symbol sequence as an output. (A) Arithmetic decoding using a code sequence as an input performing decoding by techniques, the arithmetic decoding means for outputting an output symbol sequence, (b) detection to Ruyu knit detector data unit is a structural unit of a block of output symbol sequence, appeared in the (c) code sequence end code detecting means for detecting a specific bit pattern as a termination code is not obtained, (d) the termination code detecting means based on a detection result of the termination code by, upper Kiyu knit detected data unit by detecting means the block Decoding end determining means for determining whether or not the data unit is the last data unit. 4. Assume that the control signals above SL predetermined length just after the bit pattern when the predetermined bit pattern appeared to code sequence input in the arithmetic decoding means is inserted, the inserted predetermined decrypt scheme according to claim 3, wherein the control signal processing means for deleting the control signal length. Wherein said decoding end determination means, terminating code in the termination code detecting means is detected by the upper Kiyu knit detecting means, an output symbol to be decoded continuously by the arithmetic decoding means the following data unit 4. The decoding method according to claim 3, wherein when it is detected that the data unit cannot be satisfied, the last data unit filled with the output symbol is set as the last data unit of the block, and the output symbol that cannot satisfy the data unit is discarded. 6. The terminal code detecting means detects a terminal code.
And the arithmetic decoding means inputs the code sequence to the decoding register
To detect that the value of the decoding register becomes a predetermined value.
Thus, the decryption end determining means determines the end of decryption.
The decoding method according to claim 3, wherein the decoding method is set. 7. An encoding / decoding method having the following elements : (a) An input symbol sequence is input, and an arithmetic coding method is used.
Arithmetic coding that outputs a code sequence
Stage, (b) code sequence to be output in the arithmetic coding means
A predetermined length when a predetermined bit pattern appears in
Control signal for inserting the control signal of
Insertion means, data unit is a structural unit (c), the input symbol sequence
Encoding side unit detecting means for detecting the bets, blow represented by (d) Data unit length an integral multiple of the length of the
The encoding unit by the encoding unit detection means.
If the issued data unit is the last data unit
Whether to terminate arithmetic coding
Coding end determination means for determining, with respect to the code sequence output from the (e) the arithmetic coding unit
By using the control signal insertion means ,
Bit pattern is detected by the encoding end detecting means.
Indicates whether the last block is at the end of the code sequence of the
Terminal code addition method to add as a terminal code including
Stage, as input (f) code sequence, decoding by the arithmetic decoding method
And (g) an arithmetic decoding unit that outputs an output symbol sequence.
When a predetermined bit pattern appears, the bit pattern
As a control signal of a predetermined length inserted immediately after
Control signal processing means for deleting after a data unit is a structural unit of (h) output symbol sequence
Decoding side unit detecting means for detecting the door, control signals to be processed in (i) the control signal processing means
Signal is inserted into the code sequence,
A specific bit pattern that cannot appear in
End code detecting means for detecting, Bro represented by (j) Data Unit, an integral multiple of the length of the
The terminal code in the terminal code detection means.
Is detected, and the arithmetic decoding means
Updated code and decoding side unit detection means
From the data unit detected in
Output symbol cannot satisfy the next data unit
The last filled data unit to the last data unit.
It is determined as a block to be knitted, and the data unit is
Discard output symbols that cannot be satisfied and
The block is the last block from the terminal code detected in the stage.
Whether to end arithmetic decoding by obtaining information on whether or not a lock
Means for determining the end of decoding. 8. An input symbol sequence (encoded symbol)
Or the output symbol sequence (decoded symbol)
Arithmetic symbol, given either
Series (arithmetic code) handled by the conversion means and the arithmetic decoding means
Corresponds to the inferior symbol in the divided effective area.
The lower region of the selected final region
(Decoding register value) as a code sequence, and the terminating code adding means in the coding method uses the code sequence and the code sequence.
Between the end code added to the end of
Insert a number of dummy bits '0 ' that do not affect end code detection
The encoding / decoding method according to claim 7, wherein
formula. 9. An input symbol sequence (encoded symbol)
Or the output symbol sequence (decoded symbol)
Arithmetic symbol, given either
Series (arithmetic code) handled by the conversion means and the arithmetic decoding means
Corresponds to the inferior symbol in the divided effective area.
The region to be placed above and the lower bound of the selected final region
The value closest to the upper bound value with the same precision as (decoding register value)
And the terminating code adding means in the coding method uses the code sequence and the
Between the end code added to the end of
Insert a number of dummy bits '1' that do not affect end code detection
The encoding / decoding method according to claim 7, wherein
formula. 10. In the encoding / decoding method, the control signal inserting means in the encoding method is an arithmetic encoding means.
The carry generated in the code sequence output by
Output unit of code sequence occupied by all bits '1'
Is output from the most significant bit of the output unit immediately after
Insert control signal consisting of bit '0' of predetermined length
Performs transmission control of the control signal processing means in the decoding scheme input to the arithmetic decoding means
All input units of the input code sequence are occupied by bits '1'.
The most significant bit of the input unit immediately following it
And a control signal having a predetermined length bit '0' inserted from
A transmission control for judging and deleting is performed.
Item 10. The encoding / decoding method according to Item 8 or 9. 11. The encoding / decoding method according to claim 1, wherein the terminal code adding means in the encoding method determines whether the encoding has been completed.
Whether the block determined by the determination means is the last block
A coding system for a block with a terminal code including information indicating
At the end of the column, the decoding end determination means in the decoding method uses a terminal code detection method.
The block is the last block from the terminal code detected by the stage.
To obtain the information indicating whether the decoding
The encoding / decoding method according to claim 8 or 9, wherein
formula. 12. In the above-mentioned encoding / decoding system, the terminating code adding means in the encoding system comprises a code sequence and a code sequence.
Consists of end code and control code added to the end of
Impact on output termination code detection of the termination code detection means between the termination code
Insert dummy bits with no number and insert dummy bits
When the last part of the code sequence matches the end code
The final part of the code sequence can also be used as an end code to save
Abbreviation, omission of the same bit pattern as the end code in the control code
Is added to the end of the code sequence.
Then, the terminal code detection means in the decoding method uses
Contains information indicating the omission of the same bit pattern as the end code
The end code is detected, and only the number of bits that make up the end code
Judgment of decoding completion until arithmetic decoding means captures code sequence of
Delaying notification of termination code detection to the means.
The encoding / decoding method according to claim 9. 13. An encoding / decoding system having an encoding side and a decoding side.
In No. scheme, coding the length of the data unit is a structural unit of data
Side and the decoding side, and input data to the encoding side
Means for dividing into one or more blocks for encoding, and
End of block at the end of arithmetic code for block
Means for adding an identifiable terminal code; means for decoding the arithmetic code into output data on the decoding side;
The decoding process is performed by detecting the end of the block from the end code.
Means for terminating processing.
Decoding method.