JP3118955B2 - Gaming equipment controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a game machine control device for controlling the operation of a game machine, and more particularly to a game machine control device for inhibiting unauthorized modification.

[0002]

2. Description of the Related Art Conventionally, game machines such as pachinko machines and throttle machines have a control computer and a program to be executed by the control computer in order to accurately control the operation of various electronic devices constituting the game machine. The game machine control device including a program storage element (usually provided by a PROM, a mask ROM, or the like) that stores the game information is stored.

Therefore, if a predetermined program is stored in the program storage element of the game machine control device, various electronic devices constituting the game machine are controlled by a certain control procedure described by the program, and the game is controlled. You can enjoy. Further, the gaming machine control device configured as described above can easily change the control procedure of the various electrical components by changing the program stored in the program storage element, and has a so-called system flexibility. Therefore, various game machines can be produced without increasing the development load.

[0004]

However, conventional game machine control devices using such a control computer are liable to be fraudulent because of the system flexibility, which is a great feature of the game machine control device. There has been a problem that it is difficult to take sufficient preventive measures against systematic impropriety such as remodeling of equipment.

[0005] That is, if the regular ROM which is a program storage element attached to the game machine control device is removed and a modified ROM storing a modified program is attached instead, the game machine can be controlled under completely different control from before. It is possible to put in. As a result, for example, it is conceivable to create a game state in which the sense of excitement is excessively increased, or to perform fraud such as changing the payout rate of pachinko balls or the like.

[0006] In order to prevent such a misconduct from notifying the game machine unintended by the game machine manufacturer to the market, but also to prevent the production and use of illegally modified game machines ignoring various regulations. However, some defense measures were strongly required. The gaming machine control device of the present invention responds to such a demand, and manufactures an unauthorized gaming machine by changing its program while maintaining the flexibility of a system that can easily change the control procedure of various electrical components. The purpose is to prohibit and adopt the following structure.

[0007]

A game machine control device according to the present invention has a control computer which reads out a program stored in a program storage element according to a predetermined procedure and controls the operation of the game machine according to the program. In the gaming machine control device, the control computer is installed
A timing detecting means for detecting an instruction fetch cycle in which the control computer reads a program stored in the program storage element on a second substrate different from the first substrate, and When the control computer is determined to be in an instruction fetch cycle, address detection means for detecting an address signal output from the control computer to an address bus; and an address signal detected by the address detection means, Is determined to be outside the address area of
Detecting means for detecting this as an abnormal state , and
Connecting the first substrate and the second substrate;
On the substrate for a predetermined time by the control computer.
As long as the confirmation signal is output within
A watchdog circuit that allows the operation of the
When the second substrate is removed from the first substrate,
Note that the watchdog circuit is not connected
The gist is that the operation of the control computer is stopped .

Here, it is also preferable to provide a prohibition means for prohibiting or restricting the normal operation of the control computer when the detection means detects an abnormal state.

[0009]

In the gaming machine control apparatus according to the present invention having the above-described configuration, when the timing detection means determines that the control computer is in the instruction fetch cycle, the address detection means outputs the control computer output to the address bus. Detects the address signal that has been set. Then, when the address signal is out of the predetermined address area, this is detected as an abnormal state. Moreover, these processes are performed.
The control board is mounted on the second board on which the control means is mounted.
Receiving signals from the
There is a watchdog circuit that keeps permitting. This
The second substrate is a first substrate on which a control computer is mounted.
The second substrate is connected to the first substrate.
The above abnormal state cannot be detected
Lost connection to the watchdog circuit.
The control computer stops operating. When an abnormal state is detected, various measures can be taken.
For example, measures such as notifying the host computer, sounding an alarm, or prohibiting or restricting the operation of the control computer can be considered. If the operation of the computer is prohibited, the operation of the gaming machine stops. In addition, if the operation of the computer is restricted, it is possible to take measures such as disabling the substantial operation, for example, by continuing the game but not paying out prize balls.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to further clarify the structure and operation of the present invention described above, a preferred embodiment of a game machine control device of the present invention will be described below. FIG. 1 is a schematic configuration diagram showing a main part of a control system of a pachinko machine equipped with a pachinko machine control device as one embodiment of the present invention.

As shown in the figure, the pachinko machine control device 1 comprises:
According to the function, the circuit is divided into two circuit boards of a main control circuit board CB1 and a check circuit board CB2. MPU10,
A logic circuit centered at 20 is formed, and is interconnected by three sets of connectors CN1a, b, CN2a, b, CN3a, b, and exchange of necessary information is ensured. With these connectors CN1, the check circuit board CB2 is mounted on the upper part of the main control circuit board CB1.

First, the circuit configuration of the main control circuit board CB1 will be described. The MPU 10 mounted on the main control circuit board CB1 is a kind of 8-bit microcomputer "Z80", and like the normal "Z80", the MREQ 10 which is an input / output terminal of the control bus control circuit 10a.
(L), RD (L), M1 (L) and other control ports, and A0 serving as an input / output terminal of the address bus control circuit 10b.
Address bus of A15 to data bus control circuit 10c
Are provided with data ports D0 to D7, which serve as input / output terminals. In the following description, the symbol “(L)” appended to the port name means that the port is low active.

The control bus control circuit 10a, the address bus control circuit 10b, and the data bus control circuit 10c inside the MPU 10 are mutually connected to a control signal generation unit 10g via an internal bus IB.
The input / output ports are controlled based on commands and information given from g. Here, the control signal generator 10g is based on a signal from an instruction decoder 10f that decodes an instruction code set in an instruction register 10e, and executes processing necessary for each of the control circuits 10a to 10d to execute the instruction. Or a circuit for outputting necessary information. In addition, the NMI is
An interrupt control circuit 10d for inputting interrupt signals from (L) and INT (L) is provided, receives power from a power supply line Vc, and executes processing in synchronization with a clock signal input from a clock circuit 18. .

Further, the MPU 10 of the present embodiment opens the internal bus IB to the outside so that the connectors CN3a, b
Is connected to the check circuit board CB2 via the. On the other hand, on the check circuit board CB2, a watchdog circuit 24 necessary for operating the MPU 10 normally is mounted, and the MPU 1 is connected via the connectors CN3a and CN3.
0 as long as the confirmation signal is continuously transmitted to the watchdog circuit 24 at a predetermined timing.
4 permits the operation of the MPU 10. When this confirmation signal is not input from the MPU 10, the watchdog circuit 24 determines that some trouble has occurred in the MPU 10, prohibits the operation of the MPU 10, and stops its control function.

Each input / output port of the MPU 10 is connected to the control bus T routed to the main control circuit board CB1.
B, an address bus AB, and a data bus DB, and are in communication with a ROM 12, a RAM 14, and an input / output interface circuit (hereinafter, referred to as I / O) 16, which are program storage elements arranged on the board. Also,
The control bus TB is connected to the connector CN1a, and the address bus AB is connected to the connector CN2a.

The ROM 12 is an external storage element for nonvolatilely recording a control program executed by the MPU 10 and various data necessary for executing the program.
When an address is specified from the, the data stored at that address is output. That is, in this ROM 12,
Important information such as a game rule to be executed as the pachinko machine control device 1 and a payout rate is recorded.

The RAM 14 is an external storage device for temporarily storing information, and temporarily stores and stores necessary data when the MPU 10 executes the control program stored in the ROM 12. That is, MPU1
0 outputs data to be temporarily stored to the data bus TB, and puts an address to store the data on the address bus AB to store the data in the RAM 14. When the data stored in the RAM 14 becomes necessary, the MPU 10 specifies the address at which the data is stored via the address bus AB.
The data output from the AM 14 is fetched from the data bus DB.

The I / O 16 is a circuit for matching information between the pachinko machine control device 1 and various electronic devices provided in the pachinko machine. Therefore, the I / O 16 is connected to various buses TB, A
B and DB are connected to the logic circuit centering on the MPU 10, and are also provided in the pachinko machine, such as a waveform shaping circuit 37 directly connected to an electric device such as a main body winning switch 33, a digital start switch 35, etc., and a pachinko machine. It is connected via a connector CN4 to a driver 45 which is directly connected to a hit lamp 39 of the main body, a display device 41 which is a group of LEDs in a central part of the body, a solenoid 43 for opening a big winning opening, and the like.

Next, the circuit configuration of the check circuit board CB2 will be described. The MPU 20 that controls the check circuit board CB2 includes a ROM, a RAM, and an I / O
It is a so-called one-chip microcomputer with a built-in circuit, and a check program described later
It is non-volatilely baked on the OM. As described above, the control bus TB of the main control circuit board CB1 is connected to the connector CN1b provided on the check circuit board CB2.
Is connected, whereby the control state of the main control circuit board CB1 can be input. This control bus TB
Among them, a clock Φ related to an instruction fetch cycle of the MPU 10 and four control signals MREQ (L),
RD (L), M1 (L), and WAIT (L) are extracted and input to the decoder circuit 22.

FIG. 2 is an explanatory diagram for explaining the relationship between the decoding function of the decoder circuit 22 and the instruction fetch cycle of the MPU 10. As shown in the figure, the MPU 10 of the “Z80” system synchronizes with the clock Φ and starts the first cycle of the instruction fetch cycle (Machine cycle).
one), M1 (L) is set to low active to indicate that the request is an access request to the external storage element, and MREQ (L) is set to RD to indicate a read request. (L) is set to be low active. When the external storage element does not output WAIT (L) at the falling edge of the clock Φ, the external storage element does not interfere with data reading even if the access time of the external storage element is slow. Has a wait cycle,
It has a function of delaying the timing of reading data.

Therefore, the actual instruction fetch by the MPU 10 is executed when a certain condition determined by each of the above signals is satisfied, and is stored in the address AD specified by the address bus AB at that time. D
The data (hatched portion in FIG. 2) output to B is fetched as an instruction. As is well known, the instruction fetched in this manner is stored in the above-described instruction register 10e, and the operation of the MPU 10 in the next execution cycle is determined. The decoder circuit 22 detects the instruction fetch condition only when the instruction fetch condition is satisfied, and outputs a signal “H” to the input port PI of the MPU 20.

Connector CN2 of check circuit board CB2
b is connected to the address bus AB of the MPU 10 and its signal is directly input to the input ports P0 to P15 of the MPU 20. Thereby, the MPU 20 can directly monitor the address information put on the address bus AB of the main control circuit board CB1.

The other connector CN3b of the check circuit board CB2 is connected to the internal bus I of the MPU 10 as described above.
B is connected, and communication with the watchdog circuit 24 is ensured. The watchdog circuit 24 has another function different from a normal watchdog circuit. That is, when the prohibition signal is input from the output port PO1 of the MPU 20, the same operation is performed as if the confirmation signal was not input from the MPU 10, and the MPU 10
Is a function that prohibits the operation of and controls its control function.

The pachinko machine control device 1 configured as described above operates as follows. When the power supply circuit of the pachinko machine control device 1 is turned on, the MPU 10 of the main control circuit board CB1 is supplied with power, and sequentially reads out the control programs stored in the ROM 12 according to the above-described instruction fetch cycle procedure, and executes the program. Is loaded into the instruction register 10e and executed. Further, as long as such processing is smoothly executed, the MPU 10 outputs a confirmation signal to the internal bus IB at a predetermined timing. Therefore, the check circuit board C
The watchdog circuit 24 mounted on the B2
Continue to allow processing. By the processing of the MPU 10 based on this control program, the pachinko machine behaves in accordance with the game rules described in the control program of the ROM 12, and the game can be performed at the payout rate described in the control program.

Such control is performed by the main control circuit board CB1.
When executed in the MPU of the check circuit board CB2
At 20, a check program whose flowchart is shown in FIG. 3 is executed.

The check program shown in FIG.
20 is a program burned into the internal ROM,
As soon as the power supply to the MPU 20 is started, processing based on this check program is started. First, M
The PU 20 performs initialization (step 100) such as initializing the internal RAM and reading a constant “MAX” stored in advance at a predetermined address in the internal ROM into a register. Then, the state of the input port PI is read (step 110), and it is determined whether or not the state is "H" (step 120). Here, the constant “MAX” indicates a final address value in which an execution instruction of the control program described in the ROM 12 is described when the pachinko machine control device 1 is shipped. Therefore, in the address value exceeding "MAX" of the ROM 12, only data and the like necessary for executing the control program are described.

When the determination in step 120 is "false", that is, when the state of the input port PI is "L" and the MPU 10 of the main control circuit board CB1 is executing a cycle other than the instruction fetch cycle, the processing is performed. Returns to the step 110 to continue monitoring the state of the input port PI.

On the other hand, when it is determined in step 120 that the value is "true", that is, when MP of the main control circuit board CB1 is
When it is determined that U10 is the instruction fetch cycle, the state of the input ports P0 to P15 is subsequently input (step 130), and the MPU 10
Is fetching instruction at address AD (see Figure 2)
Is calculated, and this address AD and initial setting (step 10)
The magnitude relation with the constant “MAX” stored in the register at 0) is determined (step 150).

When it is determined that AD ≦ MAX as a result of the magnitude comparison, it is determined that the instruction fetch by the MPU 10 is an operation of reading the address range of the ROM 12 in which the control program is described, and the processing returns to step 110 again. Then, the next instruction fetch cycle is monitored. On the other hand, A
When it is determined that D> MAX, that is, when the instruction fetch by the MPU 10 is executed beyond the description range of the control program previously defined as the constant “MAX”, the processing proceeds to step 160.

Step 160 is a step of outputting a prohibition signal from the output port PO of the MPU 20.
When this processing is executed, a prohibition signal is output to the watchdog circuit 24 from the output port PO. afterwards,
The program exits to “END” and ends the processing. That is, by the processing of step 160, the MPU 10 of the main control circuit board CB1 becomes inoperable,
The function of the pachinko machine control device 1 is completely stopped, and the game using the pachinko machine becomes impossible.

The pachinko machine control device 1 of the present embodiment configured as described above has the same structure as the conventional game machine control device,
By replacing the ROM 12, the system can be used as various types of pachinko machine control devices. Of course, when this ROM 12 is replaced, the MPU 20
Is rewritten to the final address value describing the execution instruction of the control program described in the new ROM 12 from the check circuit board CB2 to the MPU of the main control circuit board CB1.
No prohibition signal for prohibiting the operation is output.

However, when an act of illegally replacing the ROM 12 of the pachinko machine control device 1 configured as described above is performed, the MPU 10 of the main control circuit board CB1 is changed according to the program described in the illegally replaced ROM 12. At the moment when an illegal instruction exceeding the range expected by the constant "MAX" described in the internal ROM is fetched, a prohibition signal is output from the MPU 20 of the check circuit board CB2, and the MPU 1
The operation of “0” is prohibited, and the illegal act can be defended. In the case of a pachinko machine, the size of a program for a normal game is limited by regulations or the like, and is described so as to be the shortest as a program for realizing the same function. When someone other than the manufacturer tries to create a new program on a real pachinko machine,
It can be said that it is impossible to write shorter than the original program. For this reason, if an unauthorized program including a program that operates like a pachinko machine including display control is described, it is inevitable that the program will be longer than the original program. Therefore, as in the present embodiment, the illegal alteration of the program can be easily detected only by checking the access to the area exceeding the maximum address "MAX" of the program. In this embodiment,
Only the program checks whether it exceeds the maximum address "MAX" of the program. However, actual programs such as a configuration in which the minimum address of the program is also checked, a configuration in which a predetermined range of addresses is set, and a detailed check are performed, etc. It is possible to change the manner of checking according to the described address.

The pachinko machine control device 1 of the present embodiment
Adopts a configuration in which the connection between the main control circuit board CB1 and the check circuit board CB2 is completed by three sets of connectors CN1 to CN3. For this reason, attachment and detachment of the check circuit board CB2 to / from the main control circuit board CB1 becomes extremely easy, and the versatility and handleability of the check circuit board CB2 are excellent.

The MPU of the main control circuit board CB1
10 is mounted on the check circuit board CB2, and the check circuit board CB2 is mounted on the main control circuit board CB1.
If you remove from the main control circuit board CB1 immediately
Operation becomes impossible, and illegal ROM replacement can be reliably prevented. In this embodiment, the operation of the MPU 10 is inhibited by the watchdog with a simple level signal. However, in the case of a level signal, the function of the watchdog can be avoided by pulling down or pulling up the signal. It is also possible to encrypt the watchdog signal between the main control circuit board CB1 and the check circuit board CB2, or to make the configuration meaningful for the first time by combining the two, and the reliability of the check function by the check circuit board CB2. It is suitable for increasing the value.

The pachinko machine control device 1 of the above embodiment
Connects the main control circuit board CB1 and the check circuit board CB2 by three sets of connectors CN1 to CN3.
Using an IC connector etc. directly connected to each pin of 0,
The MPU 10 may be configured so that the biggie back method can be adopted.

Although the embodiment of the gaming machine control apparatus of the present invention has been described in detail, the present invention is not limited to such an embodiment at all, and may be embodied in various modes without departing from the gist thereof. Things. For example, in the above embodiment, the main control circuit board C on which the control program is described
Although B1 and the check circuit board CB2 are directly connected by a signal line, the check circuit board CB2 may be arranged at a remote location using a communication line to enable remote check. . In addition, when an access beyond the permitted address range is made, control relating to the firing of pachinko balls is continued as it is, and a configuration in which a part of the functions of the MPU 10 is restricted, such as a configuration in which only payout of prize balls is stopped, is effective. is there.

[0037]

As described above, according to the gaming machine control apparatus of the present invention, when the timing detecting means determines that the control computer is in the instruction fetch cycle, the address detecting means outputs from the control computer to the address bus. The detected address signal is detected, and when the address signal is out of the predetermined address area, this is detected as an abnormal state. In addition, the means for detecting this abnormal state
If the board on which the step is mounted is removed, the control
Stop the computer operation. Therefore, only the illegal rewriting of the program can be easily detected
Instead, a substrate equipped with each means for performing such detection
It is possible to cope with the case where it is removed . Further, when such detection is performed, the operation of the control computer can be prohibited or restricted, and in this case, the occurrence of fraud can be prevented or invalidated.

Therefore, by replacing the program storage element of the control computer, it is possible to completely prevent systematic improper attempts to change the game rules or change the payout rate. Moreover, it is not prohibited to change the program storage element properly, and the flexibility of the system can be enjoyed as it is.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram showing a main part of a control system of a pachinko machine equipped with a pachinko machine control device as one embodiment of the present invention.

FIG. 2 is an explanatory diagram of an instruction fetch cycle executed by the pachinko machine control device and a timing of a decoder circuit output.

FIG. 3 is a flowchart of a check program that is also processed by the MPU 20 of the pachinko machine control device.

[Explanation of symbols]

 1 Pachinko machine control device 10 MPU 12 ROM 14 RAM 16 I / O 18 clock circuit 20 MPU 22 decoder circuit 24 watchdog circuit 10a control bus control circuit 10b address bus control circuit 10c data bus control circuit 10d control circuit 10e instruction register 10f instruction Decoder 10g Control signal generator CB1 Main control circuit board CB2 Check circuit board

Claims (2)

(57) [Claims] 1. A game machine control device having a control computer for reading a program stored in a program storage element according to a predetermined procedure and controlling an operation of the game machine according to the program, wherein the control computer is mounted. Different from the first substrate
A timing detecting means for detecting an instruction fetch cycle in which the control computer reads out a program stored in the program storage element on the second substrate; Address detecting means for detecting an address signal output to the address bus from the control computer; and determining that the address signal detected by the address detecting means is out of a predetermined address area. when, and detecting means for detecting this as an abnormal state, and the first
And the second board are connected to each other, and the control computer is provided on the second board.
As long as the confirmation signal is output within the specified time.
Watchdog circuit that allows the operation of the
Mounting and removing the second substrate from the first substrate
The watchdog circuit is not connected
Thereby stopping the operation of the control computer.
Gaming apparatus controller being characterized in that a formed. 2. The gaming machine control device according to claim 1, further comprising a prohibition unit for prohibiting or restricting a normal operation of the control computer when the detecting unit detects an abnormal state.