JP3115727B2 - Driving device for plasma display panel - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving apparatus for a plasma display panel.

[0002]

2. Description of the Related Art As is well known, various researches have recently been made on a plasma display panel as one of thin secondary screen displays, and one of them is an AC discharge type matrix type having a memory function. Plasma display panels are known. FIG. 1 shows a configuration of a display device including such a plasma display panel.

Such a display device comprises a signal processing unit 1 for processing a so-called composite video signal as an input signal, and a display unit 2 for receiving a drive signal from the signal processing unit 1 and displaying a two-dimensional screen. In the signal processing unit 1, A
The / D converter 3 converts the input composite video signal into, for example, 8-bit pixel data. On the other hand, the timing pulse generator 6 generates various timing pulses based on the horizontal and vertical synchronizing signals extracted from the input composite video signal by the sync separator 5. The A / D converter 3 operates in synchronization with these timing pulses.

A memory control circuit 7 supplies a write / read pulse synchronized with a timing pulse from a timing pulse generation circuit 6 to a frame memory 8 to provide an A / D converter 3
The pixel data is sequentially read into the frame memory 8 while being taken in, and supplied to the output processing circuit 9 in the next stage. The output processing circuit 9 supplies the pixel data to the pixel data pulse generation circuit 12 in synchronization with the timing pulse from the timing pulse generation circuit 6. The plasma display panel 11 has column electrodes D1, D2, D3... Dm-1, Dm
And row electrodes x1, x2, which constitute one row by a pair of x and y.
x3, x4 ... xn and y1, y2, y3, y4 ... yn-1, yn
It is composed of These column and row electrodes are configured with a dielectric (not shown) in between. Scanning / sustaining / erasing pulse generation circuit 10 applies a scanning pulse having a potential for starting discharge in response to a timing pulse from timing pulse generation circuit 6 to row electrodes x1 to xn of plasma display panel 11. Also, scan / maintain /
The erase pulse generation circuit 10 generates a sustain pulse having a potential for maintaining a discharge state in response to the timing pulse from the timing pulse generation circuit 6 to generate the row electrodes y1 to yn and the row electrode x1 of the plasma display panel 11.
To xn. At this time, the sustain pulse is applied to the x and y electrodes at timing shifted from each other. further,
The scan / sustain / erase pulse generator 10 applies a discharge erase pulse for stopping the discharge state to the row electrodes x1 to xn of the plasma display panel 11 in response to the timing pulse from the timing pulse generator 6. On the other hand, the pixel data pulse generation circuit 12 generates a pixel data pulse corresponding to each pixel data supplied from the output processing circuit 9 and applies it to the column electrodes D1 to Dm.

Next, a driving operation of the plasma display panel 11 having such a configuration will be described with reference to FIG. First, the pixel data pulse generation circuit 12 applies a positive pixel data pulse corresponding to the pixel data of each row to the column electrodes D1 to Dm. The scan / sustain / erase pulse generation circuit 10 applies a sustain pulse IA of negative polarity to the row electrodes y1 to y1.
yn at the same timing. further,
The scan / sustain / erase pulse generation circuit 10 applies the sustain pulse IB of the negative polarity to each of the row electrodes x1 to xn at the same timing, and applies the scan pulse SP of the negative polarity to the sustain pulses IA and IB. In a period during which the pixel data pulse is not applied, the pixel data pulse is applied in synchronization with the application timing. In a “row” to which the negative scan pulse SP and the positive pixel data pulse are simultaneously applied, discharge occurs because the potential difference between the scan pulse SP and the pixel data pulse exceeds the discharge start voltage, and light emission occurs. I do. Therefore, discharge light emission is generated only in the row to which the scanning pulse SP is applied. Here, the discharge as described above ends instantaneously, but even after the discharge is completed, for a predetermined period of time, the potential generated by the scan pulse SP and the pixel data pulse is applied. It remains on the boundary with the electrode to form wall charges. Since the wall charges exist in the dielectric, discharge occurs again at a voltage lower than the above-described discharge start voltage. Therefore, after the end of the discharge by the scan pulse SP, the discharge is generated again by the sustain pulse IA applied to the y electrode. At this time, the re-discharge ends instantaneously, but the sustain pulses IA and IB are alternately applied to the x and y electrodes as shown in FIG. This repetition of the discharge continues until the erase pulse EP is applied to the x electrode. Erase pulse E
When P is applied to the x electrode, the wall charge in the dielectric disappears,
Thereafter, no discharge occurs even if a sustain pulse is applied. Therefore, the luminance of the discharge light emission can be adjusted by the application timing of the erase pulse EP.

The above operation is sequentially performed from row 1 to row n to write pixel data for one field of an image for each row, and after the writing of the last row, the n-th row, the pixel data of the next field is written. Writing is performed from the first line. Here, in order to increase the brightness of the plasma display panel in such a conventional driving device, a method such as increasing the frequency of the applied pulse or increasing the pulse voltage as described above is used. However, there is a problem that the power consumption increases when the luminance of the device is increased.

[0007]

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object of the present invention is to provide a driving apparatus for a plasma display panel capable of obtaining a desired luminance without increasing power consumption. With the goal.

[0008]

A driving apparatus for a plasma display panel according to the present invention is based on a video signal.
A driving apparatus of a plasma display panel of matrix type for displaying images, screen of the said plasma display panel of the luminance signal included in said video signal
Reduces the level of the luminance signal corresponding to the peripheral part by a predetermined amount
A luminance signal correcting means for obtaining a corrected luminance signal; and a plasma signal for a time corresponding to the level of the corrected luminance signal.
Light emission driving means for driving the display panel to emit light .

[0009]

[Function] In the peripheral part of the screen of the plasma display panel
Reduce the level of the corresponding luminance signal by a predetermined amount.
Light emission driving of the plasma display panel is performed based on the corrected luminance signal .

[0010]

Embodiments of the present invention will be described below.
FIG. 3 shows a configuration of a plasma display panel driving device according to the present invention. In the figure, a luminance signal correction circuit 20
, Corrects the luminance signal level in the input composite video signal of one field as desired, and supplies it to the signal processing unit 1. The detailed operation will be described below.

The input composite video signal is supplied to a multiplier 21 and a sync separation circuit 22, respectively. Sync separation circuit 22
Extracts the horizontal synchronizing signal from the input composite video signal and supplies it to the horizontal luminance correction signal generating circuit 23. Further, the sync separation circuit 22 extracts a vertical sync signal from the input composite video signal and supplies it to the vertical luminance correction signal generation circuit 24.
The horizontal luminance correction signal generating circuit 23 generates a parabolic waveform signal having a level peak after 1/2 horizontal scanning time as shown in FIG.
5 The vertical luminance correction signal generation circuit 24 generates a parabolic waveform signal having a level peak after 1/2 vertical scanning time as shown in FIG. . The adder 25 adds the supplied parabolic waveform signals (a) and (b) respectively, and
(C) Obtain a correction signal indicated by a solid line and multiply this by a multiplier 2
Feed to 1. The multiplier 21 converts the composite video signal consisting of the corrected luminance signal obtained by multiplying only the luminance signal in the input composite video signal by the correction signal (c) and the synchronizing signal (vertical and horizontal) into the signal processing unit 1 Are supplied to the A / D converter 3 and the sync separation circuit 5, respectively.

Next, the A / D converter 3 of the signal processing unit 1
This composite video signal is converted into 8-bit pixel data. On the other hand, the timing pulse generator 6 generates various timing pulses based on the horizontal and vertical synchronizing signals extracted from the composite video signal by the sync separator 5. The A / D converter 3 operates in synchronization with these timing pulses. The memory control circuit 7 supplies write and read pulses synchronized with the timing pulse from the timing pulse generation circuit 6 to the frame memory 8 to read pixel data from the A / D converter 3 while sequentially taking the pixel data into the frame memory 8. To the next-stage output processing circuit 9.

The output processing circuit 9 supplies the pixel data to the pixel data pulse generation circuit 12 in synchronization with the timing pulse from the timing pulse generation circuit 6. Scanning / sustaining / erasing pulse generation circuit 10 applies a scanning pulse having a potential for starting discharge in response to a timing pulse from timing pulse generation circuit 6 to row electrodes x1 to xn of plasma display panel 11. or,
Scanning / sustaining / erasing pulse generating circuit 10 generates a sustain pulse having a potential for maintaining a discharge state in response to a timing pulse from timing pulse generating circuit 6 to generate row electrodes y1 to yn of plasma display panel 11. And to the row electrodes x1 to xn. Further, the scan / sustain / erase pulse generation circuit 10 outputs a discharge erase pulse for stopping the discharge state in response to the timing pulse from the timing pulse generation circuit 6 to the plasma display panel 1.
The voltage is applied to one row electrode x1 to xn. On the other hand, the pixel data pulse generation circuit 12 generates a pixel data pulse corresponding to each pixel data supplied from the output processing circuit 9 and
1 to Dm. In a “row” to which the scanning pulse and the pixel data pulse are simultaneously applied, the potential difference between the scanning pulse SP and the pixel data pulse exceeds the discharge starting voltage, so that a discharge occurs to emit light. This light emission state
The light emission is continued for a time corresponding to the luminance information of the corresponding pixel data, and the light emission is stopped by applying the erase pulse.
The above-described operation is sequentially performed on rows 1 to n to perform screen display based on pixel data for one field of an image.

At this time, according to the present invention, the luminance signal in the input composite video signal is multiplied by the correction signal (c) shown in FIG. An image is displayed on the signal processing unit 1 and the display unit 2 based on a composite video signal composed of a synchronization signal. As shown in FIG. 4, the correction signal (c) has a maximum peak during 1/2 vertical scanning, and has a maximum peak during 1/2 horizontal scanning in each horizontal scanning. Accordingly, the pixel data generated by the signal processing unit 1 based on the composite video signal multiplied by the correction signal (c) has high luminance in the pixel data corresponding to a position near the center of the screen. , The brightness becomes lower as the position becomes farther from the center.

Therefore, when an image is displayed based on the pixel data, the light emission time becomes longer near the center of the screen, and the light emission time becomes shorter as the distance from the center of the screen increases, so that the image display state is as shown in FIG. The brightness near the center of the screen becomes high and the brightness becomes low as the distance from the center of the screen increases. Here, since the image information in the central portion of the screen is visually more important than in the vicinity of the peripheral edge of the screen, the luminance in the central portion of the screen is high even when the luminance in the peripheral portion of the screen is low, so that a sense of high luminance is visually felt. You get it.

In the modified signal (c) shown in FIG. 4, if the level indicated by the one-dot chain line Q corresponds to the multiplier "1" in the multiplier 21, the total light emission luminance for displaying one screen is the same as the conventional one. That is, a high luminance feeling can be obtained while keeping the power consumption the same as the conventional one. In the above embodiment, the horizontal correction signal generation circuit 23 and the vertical correction signal generation circuit 24 generate a continuously changing parabolic waveform signal as shown in FIGS. 4A and 4B.
A rectangular pulse signal as shown in (a) and (b) may be generated. At this time, the correction signal obtained by the adder 25 is as shown in FIG. Here, for example, the amplitude levels of the rectangular pulse signals as shown in FIGS. 6A and 6B are set to the same level, and an image display is performed based on the luminance signal multiplied by the corrected signal (c) obtained at this time. Then, as shown in FIG. 7, the image display state has three stages (high, medium, and low) in which the central area of the screen has high luminance, the four corner areas of the screen have low luminance, and the other areas have medium luminance.

In the above embodiment, the timing pulse generating circuit 6 generates various timing pulses based on the horizontal and vertical synchronizing signals obtained by the synchronizing / separating circuit 5; The timing pulse may be generated by using the horizontal and vertical synchronization signals obtained by the synchronization separation circuit 22 provided at 20. With this configuration, the synchronization separation circuit 5 in the signal processing unit 1 becomes unnecessary.

[0018]

As is apparent from the above description, the driving apparatus for a plasma display panel according to the present invention has a
The configuration is such that the level of the luminance signal is corrected so as to reduce the luminance in the peripheral portion, and the light emission driving of the plasma display panel is performed based on the corrected video signal.

Therefore, according to the plasma display panel driving device of the present invention, a desired high brightness feeling can be provided.
While also than that Do is possible to achieve the suppression of the power consumption.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a conventional driving device for a plasma display panel.

FIG. 2 is an operation waveform diagram of the plasma display panel driving device.

FIG. 3 is a diagram showing a configuration of a driving device of a plasma display panel according to the present invention.

FIG. 4 is an operation waveform diagram of the luminance signal correction circuit 20.

FIG. 5 is a diagram showing a screen display state by the driving device of the plasma display panel according to the present invention.

FIG. 6 is an operation waveform diagram according to another embodiment of the luminance signal correction circuit 20.

FIG. 7 is a view showing a screen display state according to another embodiment of the driving apparatus of the plasma display panel according to the present invention.

[Description of Signs of Main Parts]

 Reference Signs List 1 signal processing unit 2 display unit 20 luminance signal correction circuit

Claims (1)

(57) [Claims] 1. A driving apparatus of a plasma display panel of matrix type for displaying images based on the video signal, corresponding to the screen peripheral portion of the inner said plasma display panel of the luminance signal included in said video signal Luminance signal
A luminance signal correction means for obtaining a corrected luminance signal brought reduced by a predetermined amount the level of the amount of time corresponding to the level of the modified luminance signal plasma
A driving device for driving the plasma display panel to emit light.