JP3072636B2 - Second generation EDTV pre-encoder / decoder - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a second generation EDTV encoding / decoding system.

[0002]

2. Description of the Related Art At present, the signal system of the second generation EDTV is under study, but 525 non-interlaced signals (hereinafter abbreviated as 525P signals) are generally used as image signal sources. Even when an HD (high definition) TV signal is used as a signal source, the signal is converted into a 525P signal before the EDTV encoder. The 525P signal cannot be handled by existing studio equipment, and can be handled only by future studio equipment-HDTV or 525 non-interlaced component studio. This requires enormous investment when introducing a second-generation EDTV in a broadcasting station, and lacks the attractiveness of an EDTV signal compatible with NTSC.

FIG. 8 is a layout diagram of a conventional second generation EDTV encoder.

[0004] In FIG. G. FIG. B signal source camera, etc., and generates a 525P signal. 1
01 is EDT which converts 525P signal to NTSC signal
A V encoder 102 is an existing sub-adjustment facility, and 103 is a synchronization signal generating circuit to be added.

In order to utilize existing studio equipment, ED
When examining where to place the TV encoder in the studio equipment, the following two types of placement locations can be considered.

Immediately after the sub-adjustment equipment Immediately after the camera output (FIG. 8) However, each of the above methods has problems.

[0007]

First, the following will be discussed.
Since only the NTSC signal can pass through the sub-adjustment facility, the signal source may be a wide NTSC signal having a wide aspect while being an NTSC signal (525/2: 1). This signal is converted to a 4: 3 interlaced NTS
When displayed on the C monitor, the circle becomes a vertically long ellipse. Since this signal is not already a 525P signal, the second generation EDTV encoder can extract as a high resolution component
Only horizontal high frequency components of 4.2 MHz or more are included. At present, components (line difference signal, vertical-time augmentation signal, etc.) for making a 525P signal are also generally used as additional information for increasing the resolution. In the above-described method, only the interlace signal can be reproduced on the receiving side, and the degree of improvement is low. it is conceivable that.

The following is considered. As shown in FIG. 9, the encoder output is a signal compatible with the NTSC signal in which all additional information for wide aspect ratio and high resolution is multiplexed. Therefore, it is considered possible to pass through the existing sub-coordination equipment. However, when special effects such as image wiping, reduction, and rotation are performed in the sub-adjustment facility, the receiving side cannot decode the additional information multiplexed by the EDTV encoder. Therefore, there is a problem that a special effect cannot be used for a wide image.

Therefore, there is a problem that it is difficult to utilize existing studio facilities only by changing the location of the second generation EDTV encoder.

The present invention has been made in view of the above-mentioned problems, and has as its object to provide a second generation EDTV encoding / decoding system that enables a 525P signal to be processed by existing NTSC signal system studio equipment. And

[0011]

SUMMARY OF THE INVENTION Second generation EDT of the present invention
The V pre-encoder / decoder encodes 525 non-interlaced signals, which are the signal sources of the second generation EDTV, so that they can be processed by the existing NTSC sub-adjustment facility of the broadcasting station, and decodes them at the output of the sub-adjustment facility. In the encoding / decoding method for restoring 525 non-interlaced signals in this way, the encoder performs two sets of interlaced sub-samples having a phase difference of π in the vertical direction on the 525 non-interlaced signals to perform each phase. Is converted to an NTSC signal, and the converted NTS
In the sub-adjustment equipment to which the C signal is input, the same processing is performed on the two sets of signals, and the resulting two sets of NTSC signals are output by the decoder to one NTSC signal for the other NTS signal.
It is characterized in that 525 non-interlaced signals are restored by interpolating the C signal by shifting the phase by π in the vertical direction.

[0012]

According to the above arrangement, the 525P signal is interlaced subsampled with a phase different by π in the vertical direction,
The signal of each phase is converted into an NTSC signal, and the sub-adjustment equipment performs the same processing on the two sets of signals and processes them. Then, the decoder performs interpolation by inverse processing of the encoder to restore the 525P signal. 525P with auxiliary adjustment equipment
Signal processing becomes possible.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an encoder in a second generation EDTV pre-encoder / decoder according to an embodiment of the present invention.

In the drawing, 1 is the R.P. of 525P. G. FIG. B signal is Y. I. Matrix circuit for converting to Q signal, 2-4
Is an A / D conversion circuit for converting to digital signals, 5 to 10 are memory sections for storing Y ₁ Y ₂ , I ₁ I ₂ , and Q ₁ Q ₂ for channels 1 and ₂ , respectively. A memory control unit for controlling the write / read timing of Y ₁ Y ₂ , I ₁ I ₂ , Q ₁ Q ₂ to perform a signal division phase shift operation; 12, a clock recovery circuit for intra-station synchronization;
Reference numeral 4 denotes an NTSC encoder for channels 1 and 2, which encodes a 525P signal into an interlaced NTSC signal, and 15 denotes an NTSC which controls the operation of the NTSC encoder.
SC encoder control units, 16 and 17 are SYNC / burst MIX circuits for synchronization and burst addition for channels 1 and 2, respectively, and 18 and 19 are D / A conversion circuits for channels 1 and 2.

FIG. 2 is a block diagram of a decoder in a second generation EDTV pre-encoder / decoder according to one embodiment of the present invention.

In FIG. 2, reference numerals 20 and 23 denote SYNCS for separating synchronization signals of channels 1 and ₂ in the D2 format.
The EP circuits 21 and 22 are provided with A /
D conversion circuits, 24 and 39 are NTSC of channels 1 and 2.
Decoder 25, a control unit for NTSC decoders 24 and 39; 26, an intra-station synchronization signal generation circuit; 27 to 32, memory units for channels 1 and 2; 33, a timing control unit for memory units 27 to 32; A race synchronizing signal generation circuit, 35 to 37 are D / A conversion circuits for channels 1 and 2, and 38 is a matrix circuit for converting Y, I, Q into R, G, B analog display.

FIG. 3 is a conceptual diagram of a second generation EDTV pre-encoder / decoder according to the present invention.

In FIG. 3, reference numeral 104 denotes an encoder of the present invention, and 105 denotes a decoder.

The encoder of the present invention receives RGB component signals from 525 non-interlaced (wide-aspect image) signal sources and converts them into 2-channel NTSC signals according to the concept shown in FIG. The two sets of NTSC signals perform exactly the same special effects and switching processing in the sub-adjustment facility. As a result, at the output of the sub-adjustment facility, two sets of signals having the same delay time locked to intra-station synchronization can be extracted. These signals are restored to 525 non-interlaced signals by the decoder of the present invention, and are used as a signal source of a second generation EDTV encoder.

The problem above is that the secondary adjustment equipment is
It is whether the same processing can be performed.

FIG. 4 is a system diagram of the NTSC video sub-adjustment device.

Since there are usually three systems of MK video mixing keyer amplifiers, it is conceivable that two of these systems correspond to channels 1 and 2 of the encoder of the present invention, respectively.
However, this method has a slight performance penalty. Therefore, it is considered that having two MK units that perform the same control is a fundamental solution. Since hardware is currently collected on one shelf for each MK, it is considered that a sub-adjustment facility corresponding to the present encoder / decoder can be realized with negative changes in cost and technology.

It is natural that the encoder / decoder has a D2 format input / output so as to be compatible with the digital sub-adjustment equipment.

As described above, if the encoder / decoder of the present invention is used, the above-mentioned problem that the existing equipment cannot be used when a 525P signal is used as a signal source can be solved by slightly changing the existing equipment.

FIG. 5 is an explanatory diagram of channel assignment of the 525P signal in the second generation EDTV pre-encoder / decoder of the present invention.

FIG. 6 shows NTSC of channel 1 of the present invention.
FIG. 9 is a diagram illustrating line assignment to a format. FIG. 7 is an allocation diagram of channel 2.

Next, the encoding / decoding method of the present invention will be described in detail. The basic idea is that as shown in FIG. 5, the effective scanning line (4
83) are subjected to two sets of interlaced subsamples having phases different by π in the vertical direction, and each is assigned to channels 1 and 2. 6 and 7 show phase shift positions of the horizontal lines 1 to 483 and are assigned to an actual NTSC signal format.

FIG. 1 and FIG. 2 show concretely the hardware for performing the assignment as a circuit block.

On the encoder 104 side shown in FIG.
The GB signal is converted into a YIQ signal by the matrix circuit 1, and the signal is converted into a digital signal by the A / D conversion circuits 2 to 4, respectively. The A / D-converted signal is controlled by the odd / even of the field number and the line number in the memory control unit 11, and is written separately to the memories 5 to 10 of the channels 1 and 2. On the read side of the memory, each image data is N
Assigned to the TSC signal format. This is performed by controlling the timing of the memories 5 to 10 by the memory control unit 11. The YIQ signal of each channel is NTSC-encoded by NTSC encoders 13 and 14, and then SYNC
The burst mix circuits 16 and 17 add an NTSC burst and a synchronization signal to become a signal conforming to the D2 format. This signal is output as D2 signal,
The signals are converted into analog signals by the D / A conversion circuits 18 and 19.

The clock recovery circuit 12 recovers a clock locked to the intra-station synchronization signal and generates HV timing pulses. The NTSC encoder control unit 15 controls to perform encoding in accordance with the subcarrier phase of intra-station synchronization.

The decoder 105 shown in FIG. 2 can obtain a 525P signal by performing a process reverse to that of the encoder.

[0033]

As described above, according to the present invention, the encoder performs interlaced sub-sampling of the 525P signal with a phase different by π in the vertical direction, and converts each phase signal into two sets of NTSC signals. The sub-adjustment facility applies the same processing to the two sets of signals, and the decoder performs the processing opposite to that of the encoder, interpolates and interpolates one NTSC signal by π phase in the vertical direction to restore the 525P signal. The non-interlaced signal can be processed by existing studio equipment.

[Brief description of the drawings]

FIG. 1 is a block diagram of an encoder in a second generation EDTV pre-encoder / decoder according to an embodiment of the present invention.

FIG. 2 is a block diagram of a decoder in a second generation EDTV pre-encoder / decoder according to one embodiment of the present invention.

FIG. 3 is a conceptual diagram of a second generation pre-encoder / decoder according to the present invention.

FIG. 4 is a system diagram of an NTSC video sub-adjustment device.

FIG. 5 is an explanatory diagram of channel assignment of a 525P signal in a second generation EDTV pre-encoder / decoder of the present invention.

FIG. 6 is a diagram showing a line assignment to the NTSC format of channel 1 of the present invention.

FIG. 7 is a diagram illustrating a line allocation to the NTSC format of channel 2 of the present invention.

FIG. 8 is a layout diagram of a conventional second generation EDTV encoder.

[Explanation of symbols]

 1,38 matrix circuit 2-4,21,22 A / D conversion circuit 5-10,27-32 memory 11,33 memory control unit 12,26 clock reproduction circuit 13,14 NTSC encoder 15 NTSC encoder control unit 16-17 SYNC burst MIX circuit 18, 19, 35 to 37 D / A conversion circuit 20, 23 SYNC SEP circuit 24, 39 NTSC decoder 25 NTSC decoder control unit 34 PSYNC generator 104 Second generation EDTV pre-encoder 105 Second generation EDTV decoder

Claims (1)

(57) [Claims] 1. A signal source for a second generation EDTV, 525.
This non-interlaced signal is transmitted to the broadcaster's existing NTSC
In an encoding / decoding method in which 525 non-interlaced signals are restored by encoding so as to be processed by the sub-adjustment facility and decoding at the output of the sub-adjustment facility, the encoder converts the 525 non-interlaced signals. Two sets of interlaced sub-samples having phases different by π in the vertical direction are performed, the signals of each phase are converted into NTSC signals, and the converted NTSC signals are converted into two sets of signals by the input sub-adjustment equipment. The same processing is performed, and the two sets of NTSC signals output as a result are decoded by one of the N
A second generation EDTV pre-encoder / decoder for restoring 525 non-interlaced signals by interpolating the other NTSC signal with respect to the TSC signal by shifting the phase by π in the vertical direction and interpolating.