JP3067316B2 - Method of forming semiconductor memory cell - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of forming a one-transistor one-capacitor type semiconductor memory cell.

[0002]

2. Description of the Related Art MOS dynamic memories are available in 1970.
1kbit dynamic random access of the year
With the launch of memory as a starting point, the scale has been increased by a factor of four in three years, and the area of the memory cell has been reduced to 0.3 to 0.4 times in one generation. In order not to reduce the soft error resistance even if the memory cell is reduced, securing the cell capacity is an important issue. As a method for solving this problem, there is a method presented in the spring of 1990, the 37th JSAP Conference on Applied Physics 29a-SB-3 [stack cell having a ring structure]. In this method, a first conductive member 8 having a predetermined shape is formed as a storage electrode on one N-type source / drain region 5-1 of a MOS transistor formed on a P-type silicon substrate 1 as shown in FIG. Further, a second conductive member 9 is provided therearound, and a groove between the first conductive member 8 and the second conductive member 9 is also used as a capacitance part, thereby securing a large capacitance while suppressing an increase in cell area. In the drawing, 1 is a P-type silicon substrate, 2 is a silicon oxide film, 3 is a gate oxide film, 4
, A gate electrode; 5-2, an N-type source / drain region;
Is a first interlayer insulating film, 10 is a capacitor insulating film, 11 is a cell plate, 12 is a third interlayer insulating film, 13 is a contact hole,
4 is a bit line.

[0003]

In order to secure the capacity required for the memory operation and to reduce the cell area in this structure, the height of the storage electrodes, that is, the first conductive member 8 and the second conductive member 9 is considered. The only option is to increase the height and increase the capacity available from the side. However, in such a method, the height of the element is increased only in the portion having the storage electrode, and a large step is formed between the portion having the storage electrode and the portion not having the storage electrode. Is very difficult to form.

An object of the present invention is to provide a semiconductor memory cell capable of securing a larger capacity without increasing the height of the storage electrode and forming a large step on the element surface.
It is to provide a method of forming.

[0005]

SUMMARY OF THE INVENTION According to the present invention ,
Semiconductor memory cell includes one MOS transistor,
One of the source / drain regions of the MOS transistor is connected to a capacitor, and the other is connected to a bit line .
A column-shaped and hollow first conductive member in which the capacitance portion is formed on the one source / drain region; a first conductive member concentric with the column-shaped hollow conductive member; A third electrically connecting the conductive member to the first conductive member;
It has a conductive member . Further, the first, second and third
On the surface of the conductive member, and has a dielectric film is formed, the dielectric film, a counter electrode is formed.

That is, according to the present invention , such a feature is provided.
A method of forming a MOS transistor on a semiconductor substrate, comprising the steps of:
A first conductive film and a first conductive film on the interlayer insulating film of the OS transistor;
Successively depositing and patterning an insulator film to form a first conductive member and a first insulating member only on one of the source / drain regions of the MOS transistor; Penetrate the member and the interlayer insulating film, and
Providing an opening reaching one of the source / drain regions of the OS transistor; forming a second member on the side wall of the opening; and forming a third conductive member on the side wall of the first conductive member and the first insulating member simultaneously. a step, a step of removing the first insulating member, and forming the first, second, dielectric film on the surface of the third conductive member, and forming a counter electrode on the dielectric film Semiconductor memory characterized by including:
A method for forming a cell is provided.

[0007]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of a memory cell according to the present invention. The memory cell has a MOS transistor and a capacitor. MOS transistors include N-type source / drain regions 5-1 and 5-2 formed on a P-type silicon substrate 1.
And a gate electrode 4 laminated with a gate oxide film 3 interposed therebetween. The gate electrode 4 is formed of a first interlayer insulating film 6, a second
The bit line 14 and the N-type source / drain region 5-2 are connected through contact holes 13 formed in the interlayer insulating film 7 and the third interlayer insulating film 12.

The capacitance portion is composed of N-type source / drain regions 5-
The second conductive member 9b is connected to the first conductive member 8b and the storage electrode composed of the first conductive member 8b and the third conductive member 9c connected thereto, a cell plate 11, and a capacitive insulating film 10 for isolating the two. . The cell plate 11 and the bit line 14 are separated by a third interlayer insulating film 12, and element isolation is performed by a silicon oxide film 2 formed on a silicon substrate 1.

FIGS. 2, 3 and 4 are sectional views of a semiconductor chip shown in the order of steps for explaining one embodiment of a method of forming a semiconductor memory cell according to the present invention.

First, as shown in FIG.
00), a thermal oxide film is formed on the P-type silicon substrate 1 and then a silicon nitride film (not shown) is
m, and by photolithography technology,
After patterning so that a mask oxide film and a silicon nitride film remain on a predetermined region, thermal oxidation is performed to a thickness of about 6
An element region is partitioned by forming a silicon oxide film 2 of 00 nm. Then, the silicon nitride film and the mask oxide film are removed by wet etching.

Next, oxidation is performed in an oxidizing atmosphere at 950.degree. C. to form a gate oxide film 3 having a thickness of about 20 nm in the element region.
A polycrystalline silicon film is deposited to a thickness of 500 nm by a CVD method, and a gate electrode 4 is formed by a usual photolithography technique and a dry etching technique.

Next, as shown in FIG. 2B, arsenic is accelerated at an energy of 100 keV and a dose of 5 × 10 ¹⁵ cm ^2.
Implantation is performed to form N-type source / drain regions 5-1 and 5-2. Next, the other portions are removed by wet etching, leaving only the gate oxide film 3 immediately below the gate electrode. Then CV
A silicon oxide film is deposited by the method D, and this is used as a first interlayer insulating film 6. Subsequently, a silicon nitride film is deposited by a CVD method, and this is used as a second interlayer insulating film 7.

Next, as shown in FIG. 2C, a polycrystalline silicon film is deposited by a CVD method, and a first conductor film 8a is formed by thermally diffusing phosphorus, and then a silicon oxide film is formed by a CVD method. A film 15 is deposited. Further, the resist 16 is patterned using a normal photolithography technique. Next, the silicon oxide film 15 and the first conductor film 8a are etched into a shape shown in FIG. Subsequently, the resist 17 is patterned into a shape shown in FIG. 3D using a normal photolithography technique, and the silicon oxide film 15, the first conductor film 8a, and the second interlayer insulating film 7 are formed by using a dry etching technique. An opening is formed through the first interlayer insulating film 6 and reaches the N-type source / drain region 5-1. In this state, a silicon polycrystalline film is deposited on the entire surface of the wafer including the side wall of the opening by the CVD method, and phosphorus is thermally diffused to obtain a second conductor film 9a having a shape shown in FIG. From this state, the silicon oxide film 1 is anisotropically etched back by dry etching technology.
5, leaving only the side walls of the first conductive member 8b, the second interlayer insulating film 7, and the first interlayer insulating film 6, and subsequently wet etching the silicon oxide film 15 to obtain the shape of FIG.

Next, as shown in FIG. 4G, after the first conductive member 8b, the second conductive member 9b, and the third conductive member 9c are thermally oxidized, a polycrystalline silicon film is deposited by a CVD method. Then, phosphorus is thermally diffused and patterned by a photolithography technique and a dry etching technique to obtain a capacitor insulating film 10 and a cell plate 11 having the shapes shown in the figure. Then CV
Third interlayer insulating film 1 made of a silicon oxide film by D method
After depositing 2, a contact hole 13 is opened, and the aluminum film is formed into the shape of the bit line 14, whereby the memory cell having the structure shown in FIG. 1 is obtained.

In the above description, a thermal oxide film of silicon is used as the capacitor insulating film 10. However, the main purpose is to increase the capacity and increase the reliability of the silicon oxide film and the silicon nitride film. One or three layers may be used by using one or both of them.

In this embodiment, the bit line 15
Is an aluminum film and passes over the storage electrode. However, aluminum may be changed to polycide or the like having a higher melting point and pass through the lower side of the storage electrode.

[0018]

As described above, according to the present invention,
Since two pillar-shaped and hollow conductive members are used as components of the storage electrode, the inner wall and the outer wall thereof, the portion connecting the two conductive members, and the inner wall of the conductive member connected to the source / drain region Can also be used as the capacitance portion, so that an effect is obtained that a large capacitance can be secured without increasing the height of the storage electrode and keeping the step on the element surface small.

[Brief description of the drawings]

FIG. 1 is a sectional view of one embodiment of a memory cell of the present invention.

FIG. 2 is a cross-sectional view illustrating a method of forming a memory cell according to an embodiment of the present invention in the order of steps for explaining the embodiment.

FIG. 3 is a cross-sectional view illustrating a method of forming a memory cell according to an embodiment of the present invention in the order of steps for explaining the embodiment.

FIG. 4 is a cross-sectional view showing the order of steps for describing one embodiment of a method of forming a memory cell according to the present invention.

FIG. 5 is a cross-sectional view showing an example of a conventional memory cell.

[Explanation of symbols]

 Reference Signs List 1 P-type silicon substrate 2 Silicon oxide film 3 Gate oxide film 4 Gate electrode 5-1, 5-2 N-type source / drain region 6 First interlayer insulating film 7 Second interlayer insulating film 8 First conductive member 8a First conductivity Member 9 Second conductive member 9a Second conductive film 9b Second conductive member 9c Third conductive member 10 Capacitive insulating film 11 Cell plate 12 Third interlayer insulating film 13 Contact hole 14 Bit line 15 Silicon oxide film 16, 17 Resist

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-3-91957 (JP, A) JP-A-3-127859 (JP, A) JP-A-4-171759 (JP, A) JP-A-4-191 218954 (JP, A) JP-A-4-61374 (JP, A) JP-A-4-99373 (JP, A) JP-A-4-37062 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 27/108 H01L 21/822 H01L 21/8242 H01L 27/04

Claims (1)

(57) [Claims] 1. One MOS transistor and this MOS transistor
One of the source and drain regions of the transistor
Semiconductor memory with bit lines connected to the other end
A method for forming a cell, comprising: forming a MOS transistor on a semiconductor substrate; successively applying and patterning a first conductor film and a first insulator film on an interlayer insulating film of the MOS transistor;
Forming a first conductive member and a first insulating member only on one of the source / drain regions of the OS transistor; and penetrating the first conductive member, the first insulating member, and the interlayer insulating film;
Providing an opening reaching one of the source / drain regions of the MOS transistor; forming a second member on a side wall of the opening; and forming a third conductive member on side walls of the first conductive member and the first insulating member at the same time. a step, a step of removing the first insulating member, and forming the first, second, dielectric film on the surface of the third conductive member, and forming a counter electrode on the dielectric film method for forming a semiconductor memory cell which comprises a.