JPH0982912A - Semiconductor storage device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor storage device which facilitates the flattening of the surface of a cell and simplifies the manufacturing process, in a DRAM using an SOI substrate. SOLUTION: In a semiconductor storage device wherein a dynamic type memory cell constituted of an MOS transistor and a capacitor is formed on an SOI substrate wherein an Si layer 3 is formed on an Si substrate 1 via an SiO2 buried oxide film 2, a side wall insulating films 6 is formed on the gate side surface of the MOS transistor, a trench 10 reaching the Si substrate 1 is formed in the self-alignment manner with the side wall insulating films 6, and a storage electrode 13 of the capacitor is buried in the trench 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device using an SOI substrate in which a semiconductor layer is formed on a supporting substrate with an insulating layer interposed therebetween, and more particularly to a semiconductor memory device with an improved capacitor structure and The manufacturing method is related.

[0002]

2. Description of the Related Art Recently, highly integrated DRAM of 1 Gbit or more
As a strong candidate for realization, a dynamic RAM (DRAM) using an SOI substrate is drawing attention. Since this SOI-DRAM has the following features,
It is expected that further miniaturization will be possible. (1) Since the transistor and the capacitor are formed on the insulating film, the path through which the charge stored in the capacitor leaks to the substrate is completely cut off. Therefore, even if the storage capacity of the capacitor is small, not only is the data retention characteristic good,
Strong resistance to soft errors. (2) Since the channel of the transistor is a thin film, the short channel effect can be suppressed.

However, the conventional SOI-DRAM generally adopts the same capacitor structure as that of the bulk Si cell (T. Eimori et al., "ULSI DRAM / SIMOX wit").
h Stacked Capacitor Cells for Low-Voltage Operatio
n ", International ElectronDevices Meeting, Technic
al Digest, p.45-48,1993). Therefore, even when the SOI substrate is used, the step on the wafer surface is still severe,
The problem that the photolithography process and the wiring are difficult to process still exists.

[0004]

As described above, the conventional SO
Even in the DRAM using the I substrate, the step on the wafer surface is still severe, and there is a problem that the photolithography process and the wiring process are difficult.

The present invention has been made in consideration of the above circumstances, and an object of the present invention is to use an SOI substrate for D
It is an object of the present invention to provide a semiconductor memory device in which the cell surface is easily flattened in a RAM and the manufacturing process is simple, and a manufacturing method thereof.

[0006]

[Means for Solving the Problems]

(Summary) In order to solve the above problems, the present invention employs the following configuration. That is, the present invention (claim 1)
SO in which a semiconductor layer is formed on a supporting substrate via an insulating layer
A semiconductor memory device in which a dynamic memory cell is formed on an I substrate is characterized in that a capacitor of the memory cell is formed at a boundary portion between the supporting substrate and an insulating layer.

Further, the present invention (claim 2) is a semiconductor memory in which a dynamic memory cell including a MOS transistor and a capacitor is formed on an SOI substrate formed by forming a semiconductor layer on a supporting substrate with an insulating layer interposed therebetween. In the device, a sidewall insulating film is formed on a side surface of the gate of the MOS transistor, a trench reaching the supporting substrate in a self-alignment manner with the sidewall insulating film is formed, and a storage electrode of the capacitor is embedded in the trench. It is characterized by

According to the present invention (claim 3), there is provided a method for manufacturing a semiconductor memory device, wherein a dynamic memory cell is formed on an SOI substrate formed by forming a semiconductor layer on a supporting substrate with an insulating layer interposed therebetween. Forming an element isolation region in a semiconductor layer of an SOI substrate, forming a MOS transistor in an element formation region surrounded by the element isolation region of the SOI substrate, and forming a sidewall insulating film on a gate side surface of the MOS transistor. And forming a trench reaching the support substrate using the wall insulating film as a mask, forming an insulating film for a capacitor at the bottom of the trench, and embedding a storage electrode for the capacitor in the trench. And a process.

The following are preferred embodiments of the present invention. (1) The storage electrode of the capacitor must be connected to one of the source and drain of the MOS transistor. (2) The support substrate is a semiconductor substrate, and a diffusion layer is formed on the surface of the semiconductor substrate exposed in the trench, and a storage electrode is embedded and formed on the diffusion layer via a capacitor insulating film. In addition, the capacitor insulating film is also formed on the side surface of the insulating layer forming the SOI. (3) The first metal layer, the capacitor insulating film, and the second metal layer are stacked in this order from the bottom of the trench, and the storage electrode is embedded and formed thereon. (4) A hemispherical capacitor should be provided at the boundary between the supporting substrate and the insulating layer. More specifically, a semiconductor substrate as a supporting substrate is hemispherically etched under a trench portion, a diffusion layer is formed on the etched surface, and a storage electrode is embedded on the surface via a capacitor insulating film. There is. The etching surface of the semiconductor substrate should be roughened. (5) A trench is formed up to the middle of the insulating layer of the SOI substrate, a cylindrical storage electrode is formed on the inner surface of the trench, and a conductive layer is embedded on the inner surface of the storage electrode via a capacitor insulating film.
This conductive layer is electrically connected to the semiconductor substrate as a supporting substrate. (Operation) According to the present invention, since the capacitor is formed at the boundary between the supporting substrate of the SOI substrate and the insulating layer, the unevenness due to the capacitor formation can be reduced, and the surface step of the memory cell can be minimized. It becomes possible to suppress it. As a result, it becomes possible to easily perform the photolithography process and the wiring process.

[0010]

DETAILED DESCRIPTION OF THE INVENTION The details of the present invention will be described below with reference to the illustrated embodiments. (Embodiment 1) FIG. 1 is a sectional view showing a cell structure of an SOI-DRAM according to a first embodiment of the present invention.

Si is formed on a support substrate 1 made of an n-type Si substrate.
A Si layer (semiconductor layer) 3 is formed via a buried oxide film (insulating layer) 2 of O ₂ or the like, thereby forming an SOI substrate. An element isolation layer 4 for element isolation is formed on the semiconductor layer 3 of the SOI substrate. In each of the element formation regions separated from each other, a gate electrode (word line WL) 6 is formed on the semiconductor layer 3 via the gate oxide film 5, and n serving as a source / drain is formed on both sides of the gate electrode 6.
The mold diffusion layer 7 is formed. This constitutes a MOS transistor that functions as a switching element. A protective insulating film 8 is formed on the upper and side portions of the gate electrode 6,
9 are formed.

A shallow trench 10 penetrating the semiconductor layer 3 and the insulating layer 2 of the SOI substrate and reaching the surface of the supporting substrate 1 is provided. An n-type diffusion layer 11 is formed on the surface of the support substrate 1 exposed in the trench 10, and the diffusion layer 11 acts as a plate electrode. In the exposed part of the support substrate 1,
A conductive material 13 serving as a storage electrode (storage node) is filled through the capacitor insulating film 12, and an upper side surface of the conductive material 13 is in contact with one of the n-type diffusion layers 7 of the transistor. The insulation of the storage electrode 13 is maintained by the insulating film 9 on the side surface of the gate.

An interlayer insulating film 14 is formed on the substrate having the above structure, and the bit line (BL) 1 is formed thereon.
5 are formed. The bit line 15 is connected to the other of the n-type diffusion layers 7 of the transistor by a bit line contact 16.

FIG. 2 is a plan view of the trench pattern shown in FIG. 1 seen from above. In the present embodiment, the trench pattern is formed in a self-aligned manner with respect to the gate electrode 6, and as a result, the trench 10 has a pattern as shown by the diagonal lines (only part of which is shown) in the figure.

According to the structure of the present embodiment, since the SOI substrate is used, the resistance to soft error is strong, the short channel effect can be suppressed, and the following effects can be obtained. That is, since the capacitor is formed at the boundary between the supporting substrate 1 and the insulating layer 2 of the SOI substrate, the surface step of the memory cell can be minimized. Therefore, the cell surface is easily flattened and the manufacturing process is simplified. Further, in order to form the capacitor after the gate electrode 6 is formed, the heat load related to the formation of the gate electrode causes
The characteristics of the capacitor insulating film 12 do not deteriorate.

Further, since the plate electrode does not extend above the gate electrode 6, there is no risk of short circuit between the bit line and the plate. Further, since the facing area between the bit line and the plate is small, the bit line capacitance can be reduced.

Next, the manufacturing process of this embodiment will be briefly described. First, the element isolation layer 4 is formed on the Si layer 3 of the SOI substrate. Next, the gate oxide film 5, the gate electrode 6, the upper insulating film 8 and the sidewall insulating film 9 are formed, and the n-type diffusion layer 7 is formed using the gate electrode 6 and the insulating films 8 and 9 as a mask. After the interlayer insulating film 14 is formed, the trench is patterned to form the shallow trench 10 that contacts the gate portion and reaches the surface of the supporting substrate portion.

Next, the supporting substrate 1 is formed on the exposed portion of the supporting substrate 1.
After implanting the same type of impurities, a capacitor insulating film 12 is deposited. Various insulators can be selected as the capacitor insulating film 12, but a high dielectric film such as Ta ₂ O ₃ is desirable. Further, a conductive material 13 to be a storage electrode is deposited,
The trench 10 is filled by etching back, and the diffusion layer 7 is formed.
Form a contact point with. After that, after the interlayer insulating film 14 is deposited again, the bit line 15 is formed.

According to this step, since the shallow trench 10 is formed in self-alignment with the gate electrode 6, it becomes possible to realize a finer memory cell. (Embodiment 2) FIG. 3 is a sectional view showing a cell structure of an SOI-DRAM according to a second embodiment of the present invention. The same parts as those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted.

This embodiment is a variation of the first embodiment, in which the capacitor insulating film 12 is formed in the trench 10.
Not only the bottom surface of the trench 10 but also the side surface of the trench 10. This further ensures the insulation between the storage electrode forming the capacitor and the plate. (Embodiment 3) FIG. 4 is a sectional view showing a cell structure of an SOI-DRAM according to a third embodiment of the present invention. The same parts as those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted.

This embodiment is a variation of the first embodiment, and a capacitor is formed by forming a metal film with an insulating film sandwiched therebetween. That is, the first metal film 21 is formed on the bottom of the trench 10, and the capacitor insulating film 2 is formed on the first metal film 21.
The second metal film 23 is formed via the via 2, and the storage electrode 13 is buried and formed on the second metal film 23.

Even with this structure, the same effect as that of the first embodiment can be obtained. Note that W, Mo, Ti or the like may be used for the metal films 21 and 23 forming the capacitors. Further, instead of the metal film, it is possible to use the same Si as that of the storage electrode 13 and the support substrate 1. (Embodiment 4) FIG. 5 is a sectional view showing a cell structure of an SOI-DRAM according to a fourth embodiment of the present invention. The same parts as those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted.

The present embodiment is an example in which the surface of a supporting substrate to be a capacitor is formed in a hemispherical shape to increase the surface area of the capacitor. That is, a hemispherical dome is formed on the supporting substrate 1, and the diffusion layer 31 is formed on the surface of the supporting substrate 1 exposed on the dome.
Is formed, the storage electrode 33 is buried and formed on the capacitor insulation film 32, and the storage electrode 13 is further buried and formed thereon.

With such a structure, the same effect as in the first embodiment can be obtained, and a capacitor area several times as large as the opening area of the trench 10 can be realized.

The steps will be briefly described with reference to FIG. First, as shown in FIG. 6 (a), contacting the gate electrode portion,
After forming the shallow trench 10 reaching the surface of the support substrate 1, an insulating film 35 such as an oxide film is formed on the side surface of the trench 10.

Next, as shown in FIG. 6B, Si of the exposed portion of the supporting substrate 1 is selectively removed by chemical dry etching or the like, and the supporting substrate surface exposed in the trench 10 is dome-shaped. To etch.

Next, as shown in FIG. 6 (c), a thin film (PS) is formed on the exposed portion as a diffusion source of impurities of the same type as the supporting substrate 1.
G, AsSG, etc.) 36, and the diffusion layer 31 is formed on the support substrate 1 by solid phase diffusion.

Next, as shown in FIG. 6 (d), after forming the capacitor insulating film 32, the conductive material 3 to be the storage electrode is formed.
3 is deposited and filled in the dome by etch back.
Then, the capacitor insulating film 3 is formed using the conductive material 33 as a mask.
After removing 2, the conductive material 13 is embedded in the trench 10 to form a contact with the diffusion layer 7.

According to such a process, the capacitor area can be expanded while the damage to the substrate is minimized. (Embodiment 5) FIG. 7 is a sectional view showing a cell structure of an SOI-DRAM according to a fifth embodiment of the present invention. The same parts as those in FIG. 5 are designated by the same reference numerals, and detailed description thereof will be omitted.

This embodiment is a variation of the fourth embodiment, and has a cell structure arranged in a NAND layout. That is, a plurality of MOS transistors are connected in series, the trench 10 and the hemispherical dome as described in the fourth embodiment are formed in each connection portion, and the capacitor is formed in that portion. (Sixth Embodiment) FIG. 8 is a sectional view showing a cell structure of an SOI-DRAM according to a sixth embodiment of the present invention. The same parts as those in FIG. 5 are designated by the same reference numerals, and detailed description thereof will be omitted.

This embodiment is a variation of the fourth embodiment, in which the exposed portion of the support substrate 1 is etched into a dome shape and then the surface is roughened by wet etching or the like. This makes it possible to further increase the surface area of the capacitor. (Embodiment 7) FIG. 9 is a sectional view showing a cell structure of an SOI-DRAM according to a seventh embodiment of the present invention. The same parts as those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted.

The present embodiment is an example in which the inner wall of the cylindrical electrode is a capacitor. That is, the trench 10 is formed up to the middle of the insulating layer 2 of the SOI substrate, and the cylindrical storage electrode 41 is formed on the inner surface of the trench 10. Then, the capacitor insulating film 42 is formed on the inner wall of the storage electrode 41,
A conductive material 43 is filled in the cylinder through the capacitor insulating film 42. The conductive material 43 is electrically connected to the support substrate 1 through the contact 44 and serves as a plate electrode.

According to this embodiment, the area of the capacitor can be expanded similarly to the stack type capacitor,
Moreover, the surface irregularities due to the formation of the capacitor can be reduced, and the surface step of the memory cell can be minimized. Further, since the facing area between the bit line and the plate is smaller than that in the first embodiment, the bit line capacitance can be further reduced.

The process will be briefly described with reference to FIG.
First, as shown in FIG. 10A, a shallow trench 10 that contacts the gate electrode portion and reaches the insulating layer 2 of the SOI substrate is formed.

Next, as shown in FIG. 10B, a first conductive material 41 to be a storage electrode is formed on the side surface of the trench 10. Next, as shown in FIG. 10C, a capacitor insulating film 42 is deposited, and a second conductive material 43 which will be a plate electrode is deposited.

Next, as shown in FIG. 10D, a contact 44 penetrating the bottom surface of the trench 10 and reaching the support substrate 1 is formed. After that, the trench 10 is filled with the third conductive material 45 and then etched back to complete the capacitor structure. (Embodiment 8) FIGS. 11 and 12 are sectional views of a cell portion showing a manufacturing process of an SOI-DRAM according to an eighth embodiment of the present invention. The same parts as those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 11A, the interlayer insulating film 1
After forming the trench 10 in 4 in a self-aligned manner with respect to the gate portion, a spacer 52 is formed in a manner to leave the side wall. As the spacer 52, for example, a BPSG film or C
A VD film or the like is used. Since the spacer 52 is formed, the sidewall insulating film 51 may be made sufficiently thinner than the sidewall insulating film 9 shown in FIG.

Next, as shown in FIG. 11B, the capacitor insulating film 12 and the storage electrode 13 are buried in the trench 10 and left inside the trench by etching back.
The storage electrode 13 may be made of doped poly Si, W or the like.

Next, as shown in FIG. 12C, after removing the spacer 52, a strap 55 made of poly-Si, W or the like is buried by an etch-back method to connect the storage electrode to the drain of the transistor. To form. At this time, the strap 55 is formed not only on the side surface of the trench but also on the Si
The upper surface of the layer 3 is also in contact with the drain.

Next, as shown in FIG. 12D, after the interlayer insulating film 14 is formed again, the bit line 15 and the bit line contact 16 are formed. In the SOI-DRAM thus manufactured, the same effect as that of the first embodiment can be obtained, and since the storage electrode and the drain are in contact with each other even on the upper surface of the Si layer 3, the trench is formed. It becomes possible to lower the contact resistance as compared with the structure in which the strap is provided on the side surface of 10.

The present invention is not limited to the above embodiments. As the capacitor insulating film, Ta
_{In addition to 2} O ₃ , STO, BSTO, PZT, etc. may be used.
Further, the conductive material to be the storage electrode is W, Ti, Pt, Ru.
Or a metal compound such as TiN, WN or RuO ₂ , or a silicon compound such as polysilicon or WSi. In addition, various modifications can be made without departing from the scope of the present invention.

[0042]

As described in detail above, according to the present invention, S
Since the capacitor is formed at the boundary between the supporting substrate of the OI substrate and the insulating layer, the surface step of the memory cell can be minimized. As a result, it becomes possible to easily perform the photolithography process and the wiring process. Therefore, it is possible to provide a high-density memory device at low cost.

[Brief description of drawings]

FIG. 1 is a sectional view showing a memory cell configuration of a DRAM according to a first embodiment.

FIG. 2 is a plan view showing a layout of the DRAM of FIG.

FIG. 3 is a sectional view showing a memory cell configuration of a DRAM according to a second embodiment.

FIG. 4 is a sectional view showing a memory cell configuration of a DRAM according to a third embodiment.

FIG. 5 is a sectional view showing a memory cell configuration of a DRAM according to a fourth embodiment.

FIG. 6 is a cross-sectional view showing the manufacturing process of the DRAM of the fourth embodiment.

FIG. 7 is a sectional view showing a memory cell configuration of a DRAM according to a fifth embodiment.

FIG. 8 is a sectional view showing a memory cell configuration of a DRAM according to a sixth embodiment.

FIG. 9 is a sectional view showing a memory cell configuration of a DRAM according to a seventh embodiment.

FIG. 10 is a cross-sectional view showing the manufacturing process of the DRAM according to the seventh embodiment.

FIG. 11 is a cross-sectional view showing the first half of the manufacturing process of the DRAM according to the eighth embodiment.

FIG. 12 is a cross-sectional view showing the latter half of the manufacturing process of the DRAM according to the eighth embodiment.

[Explanation of symbols]

1 ... Support substrate 2 ... SiO ₂ buried oxide film (insulating layer) 3 ... Si layer (semiconductor layer) 4 ... Element isolation layer 5 ... Gate oxide film 6 ... Gate electrode (word line) 7 ... N-type diffusion layer 8 ... Upper part Insulating film 9,51 ... Side wall insulating film 10 ... Trench 11, 31 ... N-type diffusion layer 12, 32, 42 ... Capacitor insulating film 13, 33, 41 ... Conductive material (storage electrode) 14 ... Interlayer insulating film 15 ... Bit line 16 ... Bit line contact 21 ... First metal film 22 ... Capacitor insulating film 23 ... Second metal film 52 ... Spacer 55 ... Strap

Claims (3)

[Claims] 1. A semiconductor memory device in which a dynamic memory cell is formed on an SOI substrate in which a semiconductor layer is formed on a supporting substrate via an insulating layer, wherein the memory is provided at a boundary between the supporting substrate and the insulating layer. A semiconductor memory device comprising a cell capacitor formed therein. 2. A semiconductor memory device in which a dynamic memory cell including a MOS transistor and a capacitor is formed on an SOI substrate in which a semiconductor layer is formed on a supporting substrate with an insulating layer interposed therebetween, and a gate side surface of the MOS transistor is provided. A side wall insulating film is formed on the side wall, a trench reaching the supporting substrate in a self-aligned manner with the side wall insulating film is formed, and a storage electrode of the capacitor is embedded in the trench. 3. A method of manufacturing a semiconductor memory device, wherein a dynamic memory cell is formed on an SOI substrate formed by forming a semiconductor layer on a supporting substrate with an insulating layer interposed therebetween, in a semiconductor layer of the SOI substrate. Forming a MOS transistor in a device formation region surrounded by a device isolation region of the SOI substrate;
Forming a sidewall insulating film on the gate side surface of the OS transistor, forming a trench that reaches the supporting substrate using the wall insulating film as a mask, and forming an insulating film for a capacitor at the bottom of the trench. And a step of burying a storage electrode for a capacitor in the trench.