JP3067222B2 - Digital demodulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to, for example, a PSK signal and
The present invention relates to a digital demodulator used in a receiving unit of a wireless device that performs communication using an ASK signal or a QAM signal combining the two.

2. Description of the Related Art In recent years, a digital communication system has been developed, and a demodulator on the receiving side must also be constituted by a digital system. However, as a demodulator, it is possible to reduce the circuit scale and increase the speed. is necessary.

[0003]

2. Description of the Related Art FIG. 6 is a block diagram of a conventional storage unit, FIG. 7 is an operation explanatory diagram of FIG. 6, FIG. 8 is an example of a block diagram of a digital demodulator to which the conventional storage unit is applied, and FIG. Diagram illustrating the principle of a digital filter, where (A) is the principle component and (B)
FIG. 7 is an impulse response diagram of a filter. Note that the reference numerals on the left side of FIG. 7 indicate the waveforms of the same reference numerals in FIG.

[0004] The operation of FIG. 8 will be described below with reference to FIG. 9. The digital demodulator shown in FIG. 8 is a digital demodulator that was filed on August 23, 1990 by the present applicant. Since the operation of the digital demodulator is the same as that described in claim 1 and the operation of this digital demodulator has been described in detail in the specification already filed, a brief explanation will be given.

[0005] First, analog / digital converters (hereinafter abbreviated as A / D converters) 11 and 12 convert input Ich and Qch baseband signals into, for example, 8-bit digital data and convert them into digital filters. (Hereinafter abbreviated as DF).

The DFs 13 and 14 use the applied tap coefficients to remove noise components and waveform shaping contained in the input digital data, so that the noise components are reduced and the waveforms are shaped to form clear contours. The digitalized eye pattern is added to the phase difference detector 15.

Here, for example, as shown in FIG. 9A, an input signal is applied to a shift register 131, and a tap coefficient is shifted by one bit every time a bit is shifted,..., A ₃ , a _4, a ₅ , .. Are multiplied and added by an adder 134 to perform a filtering operation on the input signal.

When an impulse is applied to a filter having a desired frequency characteristic, an impulse response characteristic as shown in FIG. 9B is obtained on the time axis. sampling points _{·· S 4, S 5, S} 6 values in _{·· ·· a 4, a 5,} a 6 ·· are tap coefficients.

The phase difference detector 15 detects the position shift between the digitized eye pattern opening and the bit timing, that is, the phase difference by using the outputs of the DFs 13 and 14, and then detects the phase difference by the loop filter 16. The noise component included in the detection result from the phase difference detector is removed and sent to the storage unit 3 and the control circuit 2.

The oscillator 17 generates a clock having a bit rate, for example, twice the bit rate of the clock extracted from the baseband signal to generate A / D converters 11 and 12.
And DFs 13 and 14, and also directly to the phase difference detector 15, the loop filter 16, and the control circuit 2 through the prohibition circuit 18 or through the frequency divider 19.

Here, various tap coefficients corresponding to the above detection results are written in the storage unit 3 in advance. For example, looking at the sampling points S ₅ in (B) Figure 9, the detection result, i.e. the phase difference x is the tap coefficient a ₅ is 0, the tap coefficients a ₅₁₁ when the x _{11 is,} when x ₂₁ Is the tap coefficient a ₅₂₁ , and when x ₁₀ is the tap coefficient a
₅₁₀ are written so as to be read out respectively. This is performed for all sampling points.

Therefore, the tap coefficient corresponding to the applied detection result is read from the storage unit 3 and sent to the DFs 13 and 14, so that the bit timing position matches the eye pattern opening.

That is, since the bit timing does not coincide with the eye pattern opening at first, this portion is not hit. Therefore, the bit timing is shifted by an amount corresponding to the detection result so that the bit timing hits the eye pattern opening. Thereby, noise removal and waveform shaping are performed effectively.

The control circuit 2 adds the detection result from the phase difference detector, that is, the detected phase difference, and inhibits the control signal when the sum of the phase differences becomes (360/2) = 180 degrees.
18 to stop the clock sent from the inhibition circuit by one clock.

[0015] This is, in FIG. 9 in (B), for example, when the sampling point S ₅ coincides with S ₆ is shifted to the right, to shift the sampling point S ₆ next if one clock stops Thus, the frequency of the bit timing can be forcibly adjusted.

Next, the operation of the storage unit 3 in FIG. 8 will be described with reference to FIGS. 6 and 7. For simplicity, the written tap coefficient (having an 8-bit configuration) is a _{0 to} a ₃ of 4
Number.

As shown in FIG. 6, the storage section 3 includes a ROM 32 in which four types of tap coefficients are written, a counter 31 for controlling the address of the ROM, and a D-type flip-flop (hereinafter referred to as D-type flip-flop). FF) 33-36. Although there are eight D-FFs 33 to 36, each is represented by one.

The detection result x ₁ from the phase difference detector shown in FIG. On the other hand, the counter also applies the count value incremented by the clock to the ROM, and the detection result and the count value are read and addressed (C in FIG. 7).
K reference _5, x _1).

[0019] Therefore, as shown in FIG. 7-O _1, sequentially tap coefficients a ₀ ~a ₃ corresponding the ROM 32, is read out, Fig. 7-O
D-FF 3 corresponding to clocks CK ₁ to CK ₄ as shown in _{2 to} O ₅
After being latched by 3-36, it is applied to DF13.

In FIG. 6, four tap coefficients are sequentially read from one ROM, but if four ROMs are used, four tap coefficients can be read by one access. BR in FIG. 7 is a bit rate.

[0021]

Here, since the storage unit stores tap coefficients of an 8-bit configuration corresponding to all values of the detection result x, the memory capacity is increased.

Also, since tap coefficients required for one DF calculation must be read within one bit time, when high-speed operation is required, a plurality of ROMs are prepared and divided and stored, and the tap coefficients are stored in parallel. Must be accessed at the same time.

That is, if the circuit scale is reduced, high-speed operation becomes difficult, and if high-speed operation is enabled, the circuit scale increases. An object of the present invention is to reduce the circuit scale and increase the speed.

[0024]

FIG. 1 is a block diagram showing the principle of the present invention. In the figure, reference numerals 13 and 14 denote noise removal / waveforms for input Ich and Qch digital data using a tap coefficient applied and a clock having a bit rate twice or more the bit rate of the digital data. Reference numeral 5 denotes a phase difference detection unit for detecting a phase difference using two outputs of the digital filter, removing noise of the detected phase difference, and outputting the result.

Reference numeral 4 denotes storage means for reading out tap coefficients corresponding to the output of the phase difference detection section so that the output phase of the digital filter becomes optimum. Reference numeral 41 denotes ± m sampling periods from the sampling point s. Is a storage portion where the difference tap coefficient of the difference between the maximum value and the minimum value of the tap coefficient up to the sampling point separated by is written in the corresponding area as the tap coefficient of the sampling point s, and 42 is the storage portion from the storage portion. This is an output part that adds the read difference tap coefficient and the minimum value of the tap coefficient and outputs the result as the tap coefficient at the sampling point s.

[0026]

DETAILED DESCRIPTION OF THE INVENTION The present invention sampling point in FIG. 2 (hereinafter, the point abbreviated) (corresponding to m = 1 in the scope of the claims) If S ₄ is shifted to point S _5, the tap of the point S ₄ coefficient does not become smaller than the tap coefficients of the point S _5.

[0027] The sampling of the point S ₄ value b ₄ = Δb ₄₅ +
Although shown in b _5, [Delta] b ₄₅ is the value corresponding to the detection result is variable portion which changes, b ₅ is the value is fixed a fixed part (minimum value).

Therefore, only Δb ₄₅ (corresponding to the difference tap coefficient in the claims) is stored in the storage section 41 of the storage means, and b ₅ is not stored because b ₅ is a fixed part. Also stores only tap coefficients [Delta] b ₄₃ of the variable portion in the same manner as described above if the point S ₄ is shifted towards the point S _3. The fixed portion may be formed by a circuit that generates a corresponding pattern.

It should be noted, has been conventionally stores all represent both variable and fixed parts as the sampling value b ₄ of the point S _4, for example, 8-bit ROM. Therefore, if the difference tap coefficient can be represented by 4 bits, by storing only this difference tap coefficient, it becomes possible to write two difference tap coefficients in the same address area.

That is, since two tap coefficients can be read by one access, the circuit scale is reduced. Conversely, high speed operation is possible with the same circuit scale.

[0031]

FIG. 3 is a block diagram of an embodiment of the present invention, FIG. 4 is an operation explanatory diagram of FIG. 2, and FIG. 5 is an example of a block diagram of a digital demodulator to which a storage section of the present invention is applied.

The reference numeral on the left side of FIG. 4 indicates the waveform of the same reference numeral in FIG. The same reference numerals indicate the same objects throughout the drawings. Here, the phase difference detector 15 and the loop filter 16 are components of the phase difference detection unit 5, a storage unit 41,
The output part 42 indicates a constituent part of the storage means 4. Hereinafter, FIG.
5 will be described, but FIG.
However, since this is a part of the present invention, and other parts are the same as those of the conventional example, they will be described briefly, and the storage part will be described in detail.

First, the A / D converters 11 and 12 in FIG. 5 convert the input Ich and Qch baseband signals into digital data and send them to the DFs 13 and 14, where the noise components of the digital data are converted. After removal and waveform shaping, the output (eye pattern) is sent to the phase difference detector 15.

Then, after detecting the phase difference x between the opening of the eye pattern and the bit timing, the phase difference detector 15
The noise component is removed by the loop filter 16 and the detection result (phase difference) is sent to the storage means 4 and the control circuit 2.

The oscillator 17 generates a clock having, for example, a double bit rate of the clock extracted from the baseband signal and sends it to the A / D converters 11 and 12 and the DFs 13 and 14. Directly via or divider by 2
The signal is sent to the phase difference detector 15, loop filter 16, and control circuit 2 via 19.

Since various tap coefficients corresponding to the above-mentioned phase difference x are written in the storage means 4 in advance,
By outputting the tap coefficient corresponding to the input phase difference, the bit timing hits the opening of the eye pattern.

Now, the control circuit 2 determines that the sum of the phase differences is (360 /
2) When it reaches 180 degrees, a control signal is sent to the prohibition circuit 18 and the clock sent from the prohibition circuit is stopped by one clock. As a result, the sampling point shifts to the next sampling point, and the frequency of the bit timing can be forcibly adjusted.

Next is a description of operation of Figure 3 with reference to FIG. 4, (a 8-bit configuration) tap coefficients in order to simplify the explanation and four b ₀ ~b _3. Also, D-FF 421 ~
Each 424 is composed of eight D-FFs, but one
It is represented by D-FF.

Further, reference numeral 412 in the figure denotes a ROM for storing tap coefficients, and it is assumed that two differential tap coefficients (each 4 bits) are written at the same address. For example, the difference tap coefficients Δb ₀ and Δb ₁ correspond to the upper 4 bits and lower 4 bits of the area corresponding to address 1, and Δb ₂ and Δb ₃ correspond to the upper 4 bits and lower 4 bits of the area corresponding to address 2. The data is written in four bits.

Reference numeral 411 denotes a counter for controlling the address of the ROM. Reference numerals 421 to 424 denote D-FFs for latching the tap coefficients (the above-described difference tap coefficients) read from the ROM 412.

Further, DF 13 is a digital filter for performing calculations using the read tap coefficients.
Specific pattern K ₁ ~K ₄ for providing a tap coefficient of the fixed portion is applied to the ～424.

Now, the detection result x ₁ from the phase difference detector 6 in FIG. 5 is applied to the ROM 412. On the other hand, since the counter 411 is also applied to the ROM using the count value incremented by the clock CK _5, 2 inputs is a read address preparative (see CK _5, x in FIG. 4).

Therefore, as indicated by O ₁ in FIG. 2, 8 bits of the difference tap coefficients Δb ₀ and Δb ₁ are read in parallel from the ROM 412, and the upper 4 bits (Δb ₀ ) are stored in the D-FF 421 and Four bits (Δb ₁ ) are added to D-FF 422.

On the other hand, here, the dap coefficient of the fixed portion is set in advance.
Since K ₁ and K ₂ (4 bits each) are applied, when the clock CK ₁ is applied, the differential tap coefficient Δ is added to the D-FF 421.
b ₀ and tap coefficient K _{1 of} fixed part are taken in and tap coefficient
It is latched as b _0.

At the same time, the difference tap coefficient Δb ₁
And the tap coefficient K _{2 of the} fixed part is taken in and the tap coefficient b ₁
(See O ₂ and O _{3 in} FIG. 2). Also, CK ₅
One clock after, the difference tap coefficients Δb ₂ and Δ
b ₃ is read out in parallel as above and Δb ₂ is D-FF 423
Then, Δb ₃ is applied to D-FF 424.

Here, as the tap coefficient of the fixed part,
Since K ₃ and K ₄ are applied, respectively, Δb ₂ and K ₂ are applied to D-FF 423 and Δb ₃ and K ₃ are applied to D-FF 424 by application of clock CK _2.
Are simultaneously captured and latched as tap coefficients b ₂ and b ₃ (see O ₄ and O _{5 in} FIG. 2).

Therefore, the tap coefficients b _{0 to} b ₃ latched by the D-FFs 421 to 424 at the rising point of the bit rate (BR) shown in FIG. Incidentally, the tap coefficients K ₁ ~K ₄ fixed part using the hard grounded and the power supply voltage may be set as, for example, 1011.

That is, since the tap coefficients written in the ROM 412 may be differences, for example, two tap coefficients can be written with one address, and the circuit scale is reduced. In addition, since reading from the ROM reads two tap coefficients with one clock, high-speed operation is possible.

[0049]

As described in detail above, according to the present invention, there is an effect that the circuit scale can be reduced and the speed can be increased.

[Brief description of the drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is an operation explanatory diagram of FIG. 1;

FIG. 3 is a block diagram of an embodiment of the present invention.

FIG. 4 is an operation explanatory diagram of FIG. 2;

FIG. 5 is an example of a block diagram of a digital demodulator to which the storage unit of the present invention is applied.

FIG. 6 is a block diagram of a storage unit of a conventional example.

FIG. 7 is an operation explanatory diagram of FIG. 6;

FIG. 8 is an example of a block diagram of a digital demodulator to which a storage unit of a conventional example is applied.

FIGS. 9A and 9B are explanatory diagrams of the principle of a digital filter, wherein FIG. 9A is a diagram showing the principle components and FIG. 9B is an impulse response diagram of the filter.

[Explanation of symbols]

 4 Storage means 5 Phase difference detection unit 13, 14 Digital filter 15 Phase difference detection unit 41 Storage unit 42 Output unit

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-63-139451 (JP, A) JP-A-61-198848 (JP, A) JP-A-4-104542 (JP, A) JP-A-3- 262235 (JP, A) JP-A-3-4647 (JP, A) JP-A-61-199349 (JP, A) JP-A-4-107703 (JP, A) JP-A-2-126293 (JP, A) JP-A-1-221000 (JP, A) JP-A-2-301873 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 27/00-27/38

Claims (1)

(57) [Claims] 1. An I-channel reception signal and a Q-channel reception signal.
A / D converter that converts each signal into digital data
And a digital filter that shapes each digital data waveform
And the bit rate to the A / D converter and the digital filter.
Oscillator that gives a clock more than twice the clock, and the eye opening obtained from the output waveforms of both digital filters
Difference detection unit that detects the phase difference between the unit and the bit timing
And a loop filter for removing a noise component in the detected phase difference
And an impulse response for each of a plurality of phase differences of the digital filter.
Storage means for holding a set value of a tap coefficient for an answer;
And outputs the phase difference output of the loop filter to an address of the storage means.
The phase difference output value approaches zero.
The tap coefficient of the impulse response is
In the digital demodulator which performs read control of the digital demodulator, the storage means stores ± m samplings from the sampling point s.
Up to sampling points separated by a period (m is a positive integer)
Tap coefficient of the difference between the maximum and minimum values of the tap coefficient between
Number corresponds to the tap coefficient of the sampling point.
Area, a difference tap coefficient read from the storage section, and the tap
Tap the sampling point s by adding the minimum value of the coefficient.
Having an output part for outputting as a coefficient
Digital demodulator .