JP3067133B2 - Display device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device for displaying text and graphic information such as a text broadcast.

2. Description of the Related Art Teletext is transmitted by multiplexing a text signal during a vertical blanking period of a television wave. Usually, a program is broadcast repeatedly at a cycle of 20 to 30 seconds.

For this reason, as a countermeasure for the waiting time, a character signal is fetched into the buffer memory, a character broadcast program is searched from the buffer memory, the character broadcast data is processed, and written into the video RAM.

A conventional teletext display device will be described with reference to FIG.

In FIG. 4, reference numeral 1 denotes a clock generator for generating various video signals and various clock signals.

 Reference numeral 2 denotes a CPU unit that performs various control processes.

Reference numeral 3 denotes an I / O unit corresponding to input / output with respect to the CPU unit 2,
Sends and receives various processing requests and data.

Reference numeral 4 denotes a counter for generating various clock signals and various video synchronizing signals in response to the clock signal from the clock generator 1, and outputs a CPU clock signal CPUCLK 1 synchronized with the display readout signal to the CPU unit 1.

Reference numeral 5 denotes a video RAM which stores video data for performing display reading.

Reference numeral 6 denotes a switching unit which switches between an address signal and a control signal from the counter 4 for performing display reading to the video RAM 5 and an access address signal and a control signal from the CPU unit 2.

Reference numeral 7 denotes a data bus gate used for separating signals on the data bus. The data bus gate 7 is closed when the video RAM 5 is read out for display, and is opened when the CPU 2 accesses the video RAM 5 to control these signals. Is performed by control signals from the counter 4 and the CPU unit 2.

Reference numeral 8 denotes a video converter for performing parallel conversion of data from the video RAM 5 and outputting the data during a display valid period according to a control signal from the counter 4.

Reference numeral 9 denotes a program RAM, which is used as a work RAM by which the CPU unit 2 performs various program processes.

 Next, the operation will be described.

Data such as teletext broadcasts taken in from the I / O unit 3 is stored in a buffer memory set in the program RAM 9,
The data is processed by the CPU 2 and written into the video RAM 5. CPU
The unit 2 is provided with 1/1 of one dot clock generated by the counter 4.
The CPU unit 2 is operated by the CPU clock CPUCLK1 which is four times the frequency, and the CPU unit 2 can access only when the display read address signal from the counter 4 is not switched to the counter 4 side by the switching unit 6 by the CPUCLK1. The data on the data bus is accessed by the data bus gate 7 with the video RAM 5 without overlapping the data at the time of display reading.

FIG. 5 shows a timing chart of the CPUCLK1 and the dot clock.

Problems to be Solved by the Invention In a conventional display device, a video RAM 5 and a program RAM
There is a problem that it is necessary to have the RAM 9 individually, and the mounting efficiency of the electronic circuit cannot be improved.

Furthermore, in order to display and read the video RAM 5 in synchronization with the video signal, the clock of the entire system is limited by the access clock of the video RAM 5, which limits the processing time of the CPU unit 2. there were.

An object of the present invention is to solve the above-mentioned conventional problems, and an object of the present invention is to provide a display device that can increase the efficiency of mounting on a substrate and that can perform high-speed processing by a CPU unit.

Means for Solving the Problems In order to solve the above problems, the display device of the present invention includes one memory used for a plurality of purposes such as a video RAM and a RAM for program processing, and reads and writes this one memory as a video RAM. In the case where the clock signal is synchronized with the video signal, the clock signal is accessed, and when the clock signal is used for other purposes, the clock signal can be accessed using a clock having a higher frequency than the clock signal. CPU clock 1 more synchronized with video signal
And CPU clock 2 with a higher frequency than this CPU clock 1
Means for generating video RAM and R for program processing
One memory used for multiple purposes such as AM, and the above CP immediately after the start of the vertical display effective period and immediately before the horizontal display effective period
Switching means for outputting the U clock 1 so as to output the CPU clock 2 immediately after the end of the vertical display effective period and immediately before the horizontal display effective period, and reading and writing the memory as a video RAM. Is accessed using a CPU clock 1 synchronized with a video signal, and is accessed using a CPU clock 2 having a higher frequency than the CPU clock 1 when used for other purposes.

According to the present invention, the CPU system operates with the clock signal 1 of the CPU synchronized with the video signal only during the period corresponding to the vertical display valid period by the means described above, and otherwise operates with the clock signal 2 having a higher frequency. Will work. Since the video RAM and the program processing RAM are the same memory, the mounting efficiency on the substrate can be increased, and the CPU can be processed at high speed.

Embodiment Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a display device according to an embodiment of the present invention.

In FIG. 1, components having the same numbers as those in the conventional example shown in FIG. 4 have the same functions, and detailed descriptions thereof will be omitted.

10 is a counter, in addition to the function of the conventional counter,
CPU clock, CPUC higher in frequency than CPUCLK1, to realize faster processing time of CPU unit 2.
LK2 is output, and a pulse DSP1 indicating an arbitrary period immediately after the start of the vertical display effective period and immediately before the horizontal display effective period, and a pulse DSP2 indicating an arbitrary period immediately after the end of the vertical display effective period and immediately before the horizontal display effective period. Each occurs.

Reference numeral 11 denotes a clock switch, which outputs CPUCLK1 and C
The switching of PUCLK2 is performed using the signals of the pulses DSP1 and DSP2, and the switching clock CPUCLK3 is output.

Reference numeral 12 denotes a RAM, which is a highly integrated memory.
M, video RAM is selected.

Each signal in the counter 10 will be described with reference to FIG. 2 (a) shows the vertical synchronizing signal and the vertical display valid period signal, FIG. 2 (b) shows the horizontal synchronizing signal and the horizontal display valid period signal, and FIG. 2 (c) shows the relation between the vertical synchronizing signal and the horizontal synchronizing signal. Show.

FIG. 2 (d) shows the relationship between the vertical display effective period signal and the horizontal display effective period signal and the timing relationship between the pulses DSP1 and DSP2 which are apparent from FIGS. 2 (a), 2 (b) and 2 (c).

The pulse DSP1 can generate a horizontal synchronizing signal from a signal obtained by using a shift register of an arbitrary stage, for example, triggered by a rise of a vertical display valid period signal. Pulse DSP2
Similarly, the falling signal of the vertical display effective period is used as a trigger
It can be created by the same means as when DSP1 is obtained.

FIGS. 3A and 3B show the output timing of the CPUCLK3 obtained from the clock switching unit 11. FIG.

The falling of CPUCLK2 is detected at the broken line portion of the pulse DSP1 in FIG. Until the falling edge is detected, CPUCLK3 remains
CLK2 signal. After detecting the falling edge of CPUCLK2, D
During the “H” period of SP1, CPUCLK3 becomes “L”, and becomes a signal of CPUCLK1 synchronized with this signal when the horizontal display valid period signal is “H”.

On the other hand, CPUCLK2 is indicated by the broken line of the pulse DSP2 in FIG.
Is detected. Until the "H" part other than the broken line part of DSP2 matches the "L" part of CPUCLK1, CPUCLK3
Is the same as CPUCLK1, and after detecting the rising edge of CPUCLK2, CPUC
LK2.

As a result, only during the period corresponding to the vertical display valid period, the CPU unit 2 operates with the CPU clock CLK1 of the CPU synchronized with the video signal and accesses the RAM 12. Otherwise, CPU
CLK3 becomes the clock CPUCLK2, enabling high-speed processing.

According to the present invention, the video RAM and the program RAM are configured on the same chip select, the same block of RAM, and the video R
In the AM display read section, a clock synchronized with the video signal is used as a reference signal, and in other sections, a clock that can perform higher-speed processing can be used as a reference signal. The effect can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram of a display device according to an embodiment of the present invention, FIG. 2 and FIG. 3 are timing charts of signals used in the embodiment of the present invention, FIG. FIG. 5 is a timing chart of signals used in the conventional example. 1 clock generator, 2 CPU unit, 6 switching unit, 7 data bus gate, 8 video conversion unit, 10
…… Counter, 11… Clock switching unit, 12… RAM.

──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Satoshi Sakamoto 1006 Kazuma Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Takashi Morii 1006 Kazama Kazuma Kadoma, Osaka Matsushita Electric Industrial Co. In-company (72) Inventor Toshikatsu Kawakami 1006 Kadoma, Kazuma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. (56) References JP-A-57-198595 (JP, A) JP-A-59-154487 (JP, A) JP-A-54-44440 (JP, A) JP-A-57-105781 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N ⁷ /025-7/088 G09G 1 / 00-1/28 G11C 11/00-11/56 G06F 3/14-3/153

Claims (2)

(57) [Claims] 1. A memory used for a plurality of purposes such as a video RAM and a program processing RAM for storing a text signal of a received teletext program, a CPU for controlling the memory, and a CPU clock synchronized with a video signal 1, a clock generating means for generating a CPU clock 2 having a higher frequency than the CPU clock 1, and a clock supplied from the clock generating means to the CPU is switched to the CPU clock 1 only during a period corresponding to a vertical display effective period. First switching means, and second switching means for switching access to the memory from the clock generating means and the CPU, wherein when the memory is read / written as a video RAM, the first switching means is provided. Switching means so that the CPU clock 1 is output only during the period corresponding to the vertical display validity period, and the image is switched by the second switching means. When the memory is switched so as to access the memory with a clock signal synchronized with an image signal, and when the memory is used for a purpose such as a program RAM, the first switching means is switched so that the CPU clock 2 is output, and the second clock is switched. 2. A display device according to claim 2, wherein the switching means is switched to access with a clock signal having a higher frequency than a clock signal synchronized with the video signal. 2. A memory used for a plurality of purposes such as a video RAM and a program processing RAM for storing a text signal of a received teletext program, a CPU controlling the memory, and a CPU clock synchronized with a video signal. 1, a clock generating means for generating a CPU clock 2 having a frequency higher than the CPU clock 1, a pulse DSP1 indicating an arbitrary period immediately after the start of the vertical display effective period and immediately before the horizontal display effective period, and the end of the vertical display effective period Immediately thereafter, a pulse generating means for generating a pulse DSP2 indicating an arbitrary period immediately before the horizontal display effective period, and a clock supplied from the clock generating means to the CPU is switched to the CPU clock 1 only during a period corresponding to the vertical display effective period. Switching means controlled to be switched by the pulse generation means as described above, and the clock generation means and the CPU to the memory A second switching unit for switching access, wherein when reading and writing the memory as a video RAM, the first switching unit outputs the CPU clock 1 only during a period corresponding to a vertical display valid period. In addition to the switching, the second switching unit switches to access the memory with a clock signal synchronized with the video signal. When the memory is used for a program RAM or the like, the CPU clock 2 is switched by the first switching unit. In order to switch so that the clock signal is output and to switch so as to access with a clock signal having a higher frequency than the clock signal synchronized with the video signal by the second switching means, the pulses DSP1 and DSP2 output from the pulse generating means are used. The output from the clock generating means is displayed vertically by the first switching means controlled by the first switching. Switching to the CPU clock 1 immediately after the start of the effective period and immediately before the horizontal display effective period, and switching to the CPU clock 2 immediately after the end of the vertical display effective period and immediately before the horizontal display effective period. A display device characterized by the above-mentioned.